19-1838; Rev 6; 1/11 µP Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset The MAX6323/MAX6324 microprocessor (µP) supervisory circuits monitor power supplies and µP activity in digital systems. A watchdog timer looks for activity outside an expected window of operation. Six lasertrimmed reset thresholds are available with ±2.5% accuracy from +2.32V to +4.63V. Valid RESET output is guaranteed down to VCC = +1.2V. The RESET output is either push-pull (MAX6323) or open-drain (MAX6324). RESET is asserted low when VCC falls below the reset threshold, or when the manual reset input (MR) is asserted low. RESET remains asserted for at least 100ms after VCC rises above the reset threshold and MR is deasserted. The watchdog pulse output (WDPO) utilizes an opendrain configuration. It can be triggered either by a fast timeout fault (watchdog input pulses are too close to each other) or a slow timeout fault (no watchdog input pulse is observed within the timeout period). The watchdog timeout is measured from the last falling edge of watchdog input (WDI) with a minimum pulse width of 300ns. WDPO is asserted for 1ms when a fault is observed. Eight laser-trimmed timeout periods are available. The MAX6323/MAX6324 are offered in a 6-pin SOT23 package and operate over the extended temperature range (-40°C to +125°C). Applications Automotive Industrial Medical Embedded Control Systems Features o Min/Max (Windowed) Watchdog, 8 Factory-Trimmed Timing Options o Pulsed Open-Drain, Active-Low Watchdog Output o Power-On Reset o Precision Monitoring of +2.5V, +3.0V, +3.3V, and +5.0V Power Supplies o Open-Drain or Push-Pull RESET Outputs o Low-Power Operation (23µA typ) o Debounced Manual Reset Input o Guaranteed Reset Valid to VCC = +1.2V Ordering Information PART Watchdog Timeout TOP VIEW GND 2 6 MAX6323 MAX6324 WDI 3 RESET 5 WDPO 4 VCC SOT23 PINRESET PACKAGE OUTPUT MAX6323_UT_ _-T -40°C to +125°C 6 SOT23 Push-Pull Ordering Information continued at end of data sheet. *These devices are factory trimmed to one of eight watchdogtimeout windows and one of six reset voltage thresholds. Insert the letter corresponding to the desired watchdog-timeout window (A, B, C, D, E, F, G, or H) into the blank following the number 6323 or 6324 (see Watchdog Timeout table). Insert the two-digit code (46, 44, 31, 29, 26, or 23) after the letters UT for the desired nominal reset threshold (see Reset Threshold Range table at end of data sheet). /V denotes an automotive qualified part. Devices are available in both leaded and lead-free packaging. Specify lead-free by replacing “-T” with “+T” when ordering. Note: There are eight standard versions of each device available (see Standard Versions table). Sample stock is generally held on standard versions only. Standard versions have an order increment requirement of 2500 pieces. Nonstandard versions have an order increment requirement of 10,000 pieces. Contact factory for availability of nonstandard versions. Pin Configuration MR 1 TEMP RANGE SUFFIX A B C D E F G H WATCHDOG TIMEOUT* FAST SLOW MAX MIN UNITS UNITS 1.5 ms 10 15 ms 100 ms 15 ms 300 15 ms 10 s 15 ms 60 23 ms 47 ms 39 ms 82 719 ms 1.3 s Typical Operating Circuit appears at end of data sheet. *See Figure 1 for operation. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX6323/MAX6324 General Description MAX6323/MAX6324 µP Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset ABSOLUTE MAXIMUM RATINGS Terminal Voltage (with respect to GND) VCC ..................................................................-0.3V to +6.0V MR, RESET (MAX6323), WDI................-0.3V to (VCC + 0.3V) WDPO, RESET (MAX6324) ..............................-0.3V to +6.0V Input Current, VCC, WDI, MR ..............................................20mA Output Current, RESET, WDPO ..........................................20mA Rate of Rise, VCC ............................................................100V/µs Continuous Power Dissipation (TA = +70°C) 6-Pin SOT23 (derate 8.7mW/°C above +70°C) ..........696mW Operating Temperature Range .........................-40°C to +125°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) Lead(Pb)-Free ............................................................+260°C Containing Lead.........................................................+240°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = full range, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VCC = 3V, TA = +25°C.) (Note 1) PARAMETER SYMBOL Operating Voltage Range VCC Supply Current ICC Reset Threshold Voltage Reset Timeout Delay VTH tRP VCC to RESET Delay WDPO, RESET Output Voltage MIN VOL VOH WDPO, RESET Output Leakage ILKG TYP 1.2 No load, RESET deasserted MAX UNITS 5.5 V VCC = 2.5V or 3.3V 23 45 VCC = 5.5V 27 57 MAX632_ _UT46 4.50 4.63 4.75 MAX632_ _UT44 4.25 4.38 4.50 MAX632_ _UT31 3.00 3.08 3.15 MAX632_ _UT29 2.85 2.93 3.00 MAX632_ _UT26 2.55 2.63 2.70 MAX632_ _UT23 2.25 2.32 2.38 RESET deasserted 100 180 280 10mV/ms, VTH +100mV to VTH - 100mV RESET Output Voltage (MAX6323) 2 CONDITIONS 20 µA V ms µs ISINK = 1.2mA, VCC = 2.25V (MAX632_ _UT23, MAX632_ _UT26, MAX632_ _UT29, MAX632_ _UT31) 0.4 ISINK = 3.2mA, VCC = 4.25V (MAX632_ _UT44, MAX632_ _UT46) 0.4 ISINK = 100µA, VCC > 1.2V, RESET asserted 0.4 V ISOURCE = 500µA, VCC = 3.15V, RESET deasserted (MAX632_ _UT23, MAX632_ _UT26, 0.8 x VCC MAX632_ _UT29, MAX632_ _UT31) V ISOURCE = 800µA, VCC = 4.75V, RESET V - 1.5 deasserted, (MAX632_ _UT44, MAX632_ _UT46) CC V RESET = V WDPO = +5.5V, RESET, WDPO deasserted _______________________________________________________________________________________ 1 µA µP Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset MAX6323/MAX6324 ELECTRICAL CHARACTERISTICS (continued) (VCC = full range, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VCC = 3V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS WATCHDOG INPUT AND OUTPUT Watchdog Timeout (Fast) (Notes 2, 3) Watchdog Timeout (Slow) (Note 4) tWD1 tWD2 MAX632_AUT_ _ 1 1.5 MAX632_BUT_ _ 10 15 MAX632_CUT_ _ 10 15 MAX632_DUT_ _ 10 15 MAX632_EUT_ _ 10 15 MAX632_FUT_ _ 17 23 MAX632_GUT_ _ 29 39 MAX632_HUT_ _ 543 719 MAX632_AUT_ _ 10 15 MAX632_BUT_ _ 100 150 MAX632_CUT_ _ 300 450 MAX632_DUT_ _ 10 15 MAX632_EUT_ _ 60 90 MAX632_FUT_ _ 47 63 MAX632_GUT_ _ 82 108 MAX632_HUT_ _ 1.3 1.8 Minimum Watchdog Input Pulse Width 300 WDI Glitch Immunity VCC = 5.5V VIH WDI Input Voltage 100 0.8 -1.5 VWDI = VCC WDPO Pulse Width VIL = 0.8V, VIH = 0.75V x VCC 0.5 s ms s ns 0.75 x VCC VWDI = 0V ms ns VIL WDI Input Current ms -1 1 1.5 1 3 V µA ms MANUAL RESET INPUT VIH MR Input Voltage 0.7 x VCC VIL 0.3 x VCC MR Minimum Pulse Width 1 V µs MR Glitch Immunity VCC = 2.5V 100 MR to Reset Delay VCC = 2.5V 120 ns 85 kΩ MR Pullup Resistance 50 ns Note 1: Devices are tested at TA = +25°C and guaranteed by design for TA = TMIN to TMAX, as specified. Note 2: WDPO will pulse low if a falling edge is detected on WDI before this timeout period expires. Note 3: To avoid a potential fake fault, the first WDI pulse after the rising edge of RESET or WDPO will not create a fast watchdog timeout fault. Note 4: WDPO will pulse low if no falling edge is detected on WDI after this timeout period expires. _______________________________________________________________________________________ 3 Typical Operating Characteristics (VCC = full range, TA = +25°C, unless otherwise noted.) 20 VCC = 3.3V 15 10 VCC = 1.0V 5 15 VOD = 100mV 5 -20 0 20 40 60 40 -20 0 20 40 60 -40 80 -20 0 20 40 60 80 NORMALIZED RESET THRESHOLD vs. TEMPERATURE NORMALIZED POWER-UP RESET TIMEOUT vs. TEMPERATURE NORMALIZED WATCHDOG TIMEOUT PERIOD (FAST) vs. TEMPERATURE POWER-UP RESET TIMEOUT 1.006 0.9995 0.9990 1.004 1.002 1.000 0.998 0.996 0.9980 0.994 -20 0 20 40 60 80 -40 -20 0 20 40 60 1.008 MAX6323/24-06 MAX6323/24-04 1.008 NORMALIZED WATCHDOG TIMEOUT PERIOD (FAST) TEMPERATURE (°C) 0.9985 1.006 1.004 1.002 1.000 0.998 0.996 0.994 0.992 -40 80 -20 0 20 40 60 80 TEMPERATURE (°C) TEMPERATURE (°C) NORMALIZED WATCHDOG TIMEOUT PERIOD (SLOW) vs. TEMPERATURE NORMALIZED WATCHDOG OUTPUT PULSE WIDTH vs. TEMPERATURE MAXIMUM TRANSIENT DURATION vs. RESET THRESHOLD OVERDRIVE 1.001 1.000 0.999 0.998 0.997 0.996 0.995 -20 0 20 40 60 80 1.006 1.004 1.002 1.000 0.998 0.996 0.994 0.992 400 MAXIMUM TRANSIENT DURATION (µs) 1.002 1.008 MAX6323/24-08 MAX6323/24-07 1.003 NORMALIZED WATCHDOG OUTPUT PULSE WIDTH (µs) TEMPERATURE (°C) TEMPERATURE (°C) 4 60 TEMPERATURE (°C) 1.0000 -40 80 TEMPERATURE (°C) 1.0005 -40 100 0 -40 80 120 20 MAX6323/24-05 -40 MAX6323/24-03 MAX6323/24-02 20 10 140 0 0 RESET THRESHOLD VOD = 20mV VOD = VTH - VCC 350 MAX6323/24-09 25 25 160 MR TO RESET DELAY (ns) 30 30 POWER-DOWN RESET DELAY (µs) VCC = 5.5V 35 SUPPLY CURRENT (µA) MAX6323/24-01 40 MR TO RESET DELAY vs. TEMPERATURE POWER-DOWN RESET DELAY vs. TEMPERATURE SUPPLY CURRENT vs. TEMPERATURE NORMALIZED WATCHDOG TIMEOUT PERIOD (SLOW) MAX6323/MAX6324 µP Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset 300 250 RESET ASSERTED ABOVE THIS LINE 200 150 100 50 MAX632_AUT23 0 -40 -20 0 20 40 TEMPERATURE (°C) 60 80 1 10 100 RESET COMPARATOR OVERDRIVE (mV) _______________________________________________________________________________________ 1000 µP Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset FAST WATCHDOG TIMEOUT PERIOD SLOW WATCHDOG TIMEOUT PERIOD MAX6323/24-10 MAX6323/24-11 WDI 2V/div WDI 2V/div WDPO 2V/div WDPO 2V/div MAX6323AUT23 MAX6323AUT23 500µs/div 5ms/div Pin Description PIN NAME FUNCTION 1 MR 2 GND Ground 3 WDI Watchdog Input. The internal watchdog timer clears to zero on the falling edge of WDI or when RESET goes high. If WDI sees another falling edge within the factory-trimmed watchdog window, WDPO will remain unasserted. Transitions outside this window, either faster or slower, will cause WDPO to pulse low for 1ms (typ). 4 VCC Supply Voltage for the Device. Input for VCC reset monitor. For noisy systems, bypass VCC with a 500pF (min) capacitor. 5 WDPO Watchdog Pulse Output. The open-drain WDPO output is pulsed low for 1ms (typ) upon detection of a fast or slow watchdog fault. WDPO is only active when RESET is high. 6 RESET Active-Low. Reset is asserted when VCC drops below VTH and remains asserted until VCC rises above VTH for the duration of the reset timeout period. The MAX6323 has a push-pull output and the MAX6324 has an open-drain output. Connect a pullup resistor from RESET to any supply voltage up to +6V. Active-Low, Manual Reset Input. When MR is asserted low, RESET is asserted low, the internal watchdog timer is reset to zero, and WDPO is reset to high impedance (open drain). After the rising edge of MR, RESET is asserted for at least 100ms. Leave MR unconnected or connect to VCC if unused. _______________________________________________________________________________________ 5 MAX6323/MAX6324 Typical Operating Characteristics (continued) (VCC = full range, TA = +25°C, unless otherwise noted.) MAX6323/MAX6324 µP Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset tWD1 (min) ) tWD1 (max) tWD2 (min) tWD2 (max) POSSIBLE STATES GUARANTEED TO ASSERT WDPO GUARANTEED NOT TO ASSERT WDPO *UNDETERMINED GUARANTEED TO ASSERT WDPO *UNDETERMINED CONDITION 1 FAST FAULT CONDITION 2 NORMAL OPERATION CONDITION 3 SLOW FAULT *UNDETERMINED STATES MAY OR MAY NOT GENERATE A FAULT CONDITION. Figure 1. Detailed Watchdog Input Timing Relationship Detailed Description The MAX6323/MAX6324 µP supervisory circuits maintain system integrity by alerting the µP to fault conditions. In addition to a standard V CC monitor (for power-on reset, brownout detect, and power-down reset), the devices include a sophisticated watchdog timer that detects when the processor is running outside an expected window of operation for a specific application. The watchdog signals a fault when the input pulses arrive too early (faster than the selected tWD1 timeout period) or too late (slower than the selected tWD2 timeout period) (Figure 1). Incorrect timing can lead to poor or dangerous system performance in tightly controlled operating environments. Incorrect timing could be the result of improper µP clocking or code execution errors. If a timing error occurs, the MAX6323/MAX6324 issue a watchdog pulse output, independent from the reset output, indicating that system maintenance may be required. Watchdog Function A pulse on the watchdog output WDPO can be triggered by a fast fault or a slow fault. If the watchdog input (WDI) has two falling edges too close to each 6 other (faster than tWD1) (Figure 2) or falling edges that are too far apart (slower than tWD2) (Figure 3), WDPO is pulsed low. Normal watchdog operation is displayed in Figure 4 (WDPO is not asserted). The internal watchdog timer is cleared when a WDI falling edge is detected within the valid watchdog window or when the device’s RESET or WDPO outputs are deasserted. All WDI input pulses are ignored while either RESET or WDPO is asserted. Figure 1 identifies the input timing regions where WDPO fault outputs will be observed with respect to tWD1 and tWD2. After RESET or WDPO deasserts, the first WDI falling edge is ignored for the fast fault condition (Figure 2). Upon detecting a watchdog fault, the WDPO output will pulse low for 1ms. WDPO is an open-drain output. Connect a pullup resistor on WDPO to any supply up to +6V. VCC Reset The MAX6323/MAX6324 also include a standard VCC reset monitor to ensure that the µP is started in a known state and to prevent code execution errors during power-up, power-down, or brownout conditions. RESET is asserted whenever the VCC supply voltage _______________________________________________________________________________________ µP Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset MAX6323/MAX6324 tWDI < tWD1 (min) RESET WDI WDPO FAST FAULT Figure 2. Fast Fault Timing RESET tWDI < tWD2 (max) WDI WDPO SLOW FAULT Figure 3. Slow Fault Timing tWD1 (max) < tWDI < tWD2 (min) RESET WDI H WDPO L NORMAL OPERATION (NO PULSING, OUTPUT STAYS HIGH) Figure 4. Normal Operation, WDPO Not Asserted _______________________________________________________________________________________ 7 MAX6323/MAX6324 µP Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset VTH VCC 100ms (min) 100ms (min) 120ns (typ) 20µs (typ) RESET MR 1µs (min) Figure 5. RESET Timing Relationship falls below the preset threshold or when the manual reset input (MR) is asserted. The RESET output remains asserted for at least 100ms after VCC has risen above the reset threshold and MR is deasserted (Figure 5). For noisy environments, bybass VCC with a 500pF (min) capacitor to ensure correct operation. The MAX6323 has a push-pull output stage, and the MAX6324 utilizes an open-drain output. Connect a pullup resistor on the RESET output of the MAX6324 to any supply up to +6V. Select a resistor value large enough to register a logic low (see Electrical Characteristics) and small enough to register a logic high while supplying all input leakage currents and leakage paths connected to the RESET line. A 10kΩ pullup is sufficient in most applications. Manual Reset Input Many µP-based products require manual reset capability to allow an operator or external logic circuitry to initiate a reset. The manual reset input (MR) can connect directly to a switch without an external pullup resistor or debouncing network. MR is internally pulled up to VCC and, therefore, can be left unconnected if unused. MR is designed to reject fast, negative-going transients (typically 100ns pulses), and it must be held low for a minimum of 1µs to assert the reset output (Figure 5). A 0.1µF capacitor from MR to ground provides additional noise immunity. After MR transitions from low to high, reset will remain asserted for the duration of the reset timeout period, at least 100ms. 8 Applications Information Negative-Going VCC Transients The MAX6323/MAX6324 are relatively immune to shortduration negative-going V CC transients (glitches), which usually do not require the entire system to shut down. Typically, 200ns large-amplitude pulses (from ground to VCC) on the supply will not cause a reset. Lower amplitude pulses result in greater immunity. Typically, a VCC transient that falls 100mV below the reset threshold and lasts less than 20µs will not trigger a reset (see Typical Operating Characteristics ). An optional 0.1µF bypass capacitor mounted close to VCC provides additional transient immunity. Ensuring a Valid Reset Output Down to VCC = 0V When VCC falls below +1.2V, the MAX6323 RESET output no longer sinks current; it becomes an open circuit. Therefore, high-impedance CMOS logic inputs connected to RESET can drift to undetermined voltages. This does not present a problem in most applications, since most µPs and other circuitry are inoperative with V CC below + 1.2V. However, in applications where RESET must be valid down to 0, adding a pulldown resistor to RESET causes any stray leakage currents to flow to ground, holding RESET low (Figure 6). R1’s value is not critical; 100kΩ is large enough not to load RESET and small enough to pull RESET to ground. This scheme does not work with the open-drain output of the MAX6324. _______________________________________________________________________________________ µP Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset VCC VCC VCC MAX6323 MAX6324 VCC µP RESET INPUT RESET RESET GND MAX6323/MAX6324 VCC R1 100k Figure 6. RESET Valid to VCC = Ground Circuit Interfacing to µPs with Bidirectional Reset Pins Since the RESET output on the MAX6324 is open-drain, this device easily interfaces with µPs that have bidirectional reset pins, such as the Motorola 68HC11. Connecting the µP supervisor’s RESET output directly to the microcontroller’s (µC’s) RESET pin with a single pullup resistor allows either device to assert reset (Figure 7). MAX6324 Open-Drain RESET Output Allows Use with Multiple Supplies Generally, the pullup resistor connected to the MAX6324 will connect to the supply voltage that is being monitored at the IC’s VCC pin. However, some systems may use the open-drain output to level-shift from the monitored supply to reset circuitry powered by some other supply (Figure 8). Keep in mind that as the MAX6324’s VCC decreases below +1.2V, so does the IC’s ability to sink current at RESET. Also, with any pullup resistor, RESET will be pulled high as VCC decays toward 0. The voltage where this occurs depends on the pullup resistor value and the voltage to which it is connected. Watchdog Software Considerations To help the watchdog timer monitor software execution more closely, set and reset the watchdog input at different points in the program, rather than “pulsing” the watchdog input high-low-high or low-high-low. This technique avoids a “stuck” loop in which the watchdog GND GND Figure 7. Interfacing to µPs with Bidirectional Reset Pins +3.3V +5.0V RPULLUP VCC VCC 5V SYSTEM MAX6324 RESET GND RESET INPUT GND Figure 8. MAX6324 Open-Drain RESET Output Allows Use with Multiple Supplies time would continue to be reset within the loop, keeping the watchdog from timing out. Figure 9 shows an example of a flow diagram where the I/O driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subroutine or loop, then set high again when the program returns to the beginning. If the program should “hang” in any subroutine, the problem would be quickly corrected, since the I/O is continually set low and the watchdog time is allowed to time out, causing a reset or interrupt to be issued. _______________________________________________________________________________________ 9 µP Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset MAX6323/MAX6324 WDPO to MR Loopback An error detected by the watchdog often indicates that a problem has occurred in the µP code execution. This could be a stalled instruction or a loop from which the processor cannot free itself. If the µP will still respond to a nonmaskable input (NMI), the processor can be redirected to the proper code sequence by connecting the WDPO output to an NMI input. Internal RAM data should not be lost, but it may have been contaminated by the same error that caused the watchdog to time out. If the processor will not recognize NMI inputs, or if the internal data is considered potentially corrupted when a watchdog error occurs, the processor should be restarted with a reset function. To obtain proper reset timing characteristics, the WDPO output should be connected to the MR input, and the RESET output should drive the µP RESET input (Figure 10). The short 1ms WDPO pulse output will assert the manual reset input and force the RESET output to assert for the full reset timeout period (100ms min). All internal RAM data is lost during the reset period, but the processor is guaranteed to begin in the proper operating state. START SET WDI LOW SUBROUTINE OR PROGRAM LOOP SET WDI HIGH RETURN END Figure 9. Watchdog Flow Diagram VCC 500pF VCC VCC *RPULLUP µP MAX6323 MAX6324 RESET MR WDI GND RESET I/O WDPO *MAX6324 ONLY Figure 10. WDPO to MR Loopback Circuit 10 ______________________________________________________________________________________ µP Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset MAX6323AUT29 MAX6324AUT29 MAX6323AUT46 MAX6324AUT46 MAX6323CUT29 MAX6324BUT29 MAX6323CUT46 MAX6324BUT46 MAX6323DUT29 MAX6324EUT29 MAX6323DUT46 MAX6324EUT46 MAX6323HUT29 MAX6324HUT29 MAX6323HUT46 MAX6324HUT46 Reset Threshold Range (-40°C to +125°C) SUFFIX 46 44 31 29 26 23 MIN 4.50 4.25 3.00 2.85 2.55 2.25 TYP 4.63 4.38 3.08 2.93 2.63 2.32 TEMP RANGE PINRESET PACKAGE OUTPUT -40°C to +125°C 6 SOT23 Open Drain MAX6324_UT_ _/V-T -40°C to +125°C 6 SOT23 Open Drain MAX6324_UT_ _/V+T -40°C to +125°C 6 SOT23 Open Drain MAX6324_UT_ _-T UNITS V Chip Information Ordering Information (continued) PART MAX 4.75 4.50 3.15 3.00 2.70 2.38 TRANSISTOR COUNT: 1371 PROCESS: BiCMOS *These devices are factory trimmed to one of eight watchdogtimeout windows and one of six reset voltage thresholds. Insert the letter corresponding to the desired watchdog-timeout window (A, B, C, D, E, F, G, or H) into the blank following the number 6323 or 6324 (see Watchdog Timeout table). Insert the two-digit code (46, 44, 31, 29, 26, or 23) after the letters UT for the desired nominal reset threshold (see Reset Threshold Range table at end of data sheet). /V denotes an automotive qualified part. Devices are available in both leaded and lead-free packaging. Specify lead-free by replacing “-T” with “+T” when ordering. Note: There are eight standard versions of each device available (see Standard Versions table). Sample stock is generally held on standard versions only. Standard versions have an order increment requirement of 2500 pieces. Nonstandard versions have an order increment requirement of 10,000 pieces. Contact factory for availability of nonstandard versions. ______________________________________________________________________________________ 11 MAX6323/MAX6324 Standard Versions µP Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset MAX6323/MAX6324 Typical Operating Circuit VCC 500pF VCC VCC *RPULLUP µP MAX6323 MAX6324 RESET MR RESET WDI GND I/O WDPO NMI *MAX6324 ONLY Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. 12 PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 6 SOT23 U6-1 21-0058 90-0175 ______________________________________________________________________________________ µP Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset REVISION NUMBER REVISION DATE 0 10/00 Initial release 5 5/10 Updated the Ordering Information and Absolute Maximum Ratings. 6 1/11 Corrected placement of /V in the Ordering Information section DESCRIPTION PAGES CHANGED — 1, 2, 10 11 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX6323/MAX6324 Revision History