19-1634; Rev 0; 1/00 KIT ATION EVALU E L B A AVAIL 2.125Gbps/1.063Gbps, 3.3V Fibre Channel Repeaters Features The MAX3770 is a 2.125Gbps Fibre Channel repeater IC. The MAX3771 provides a pin-compatible solution for 1.063Gbps Fibre Channel. Both devices are optimized for use in Fibre Channel arbitrated-loop applications and operate from a 3.3V supply. The MAX3770 is compatible with Fibre Channel jitter tolerance requirements and can recover data signals with up to 0.7 unit interval (UI) jitter. The circuit’s fully integrated phase-locked loop (PLL) provides a frequency lock indication and does not need an external reference clock. The MAX3770 provides low-jitter CML clock and data outputs. To reduce the external parts count, all signal inputs and outputs are internally terminated. The MAX3770/MAX3771 are available in 16-pin QSOP packages. ♦ Meet Fibre Channel Jitter Tolerance Requirements ♦ 3.0V to 3.6V Operation ♦ Internally Terminated Data and Clock I/O ♦ Reference Clock Not Required ♦ Frequency Lock Indication ♦ Low Power Consumption 215mW at 3.3V (MAX3770) 190mW at 3.3V (MAX3771) Pin Configuration TOP VIEW ________________________Applications FILT+ 1 16 LOCK 2.125Gbps Fibre Channel Storage Area Networks FILT- 2 15 CLK+ 1.063Gbps Fibre Channel Fibre Channel Hubs GND 3 14 CLK- Fibre Channel Storage Systems IN+ 4 IN- 5 Ordering Information PART TEMP. RANGE MAX3770CEE 0°C to +70°C PIN-PACKAGE MAX3770 MAX3771 13 CLKEN 12 GND GND 6 11 OUT+ VCC 7 10 OUT- VCC 8 9 LOCKEN 16 QSOP QSOP MAX3771CEE* 0°C to +70°C 16 QSOP *Future product—contact factory for availability. Typical Application Circuit 0.22µF LIN+ LIN- LOUT- LOUT+ FILT- FILT+ LOCK LIN+ LIN- LOUT- LOUT+ CLK+ CLK- IN+ OUT+ MAX3750 MAX3751 IN- OUT- Zo = 75Ω Zo = 75Ω MAX3770 MAX3771 IN- OUT- Zo = 75Ω OUT+ MAX3750 MAX3751 IN- OUTGND SEL 3.3V 0.1µF PORT BYPASS CIRCUIT IN+ VCC 3.3V 0.1µF Zo = 75Ω GND LOCKEN CLKEN VCC GND SEL VCC 3.3V OUT+ IN+ 0.1µF DATA REPEATER PORT BYPASS CIRCUIT ________________________________________________________________ Maxim Integrated Products 1 For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX3770/MAX3771 General Description MAX3770/MAX3771 2.125Gbps/1.063Gbps, 3.3V Fibre Channel Repeaters ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC..............................................-0.5V to +5.0V Pin Voltage Levels (IN+, IN-, FILT+, FILT-, LOCKEN, CLKEN, LOCK) ....................-0.5V to (VCC + 0.5V) LOCK Output Current .........................................-1mA to +10mA CML Output Currents OUT+, OUT-, CLK+, CLK-.................................................-22mA to +22mA Continuous Power Dissipation (TA = +70°C) 16-Pin TQFP (derate 6.7mW/°C above +70°C)..........533mW Operating Temperature Range...............................0°C to +70°C Storage Temperature Range .............................-55°C to +150°C Processing Temperature (die) .........................................+400°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = 0°C to +70°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER CONDITIONS CLKEN = VCC Supply Current (Note 1) CLKEN = GND Differential Voltage Signal at OUT or CLOCK RLOAD = 150Ω, Figure 1 Output Current at OUT or CLOCK Sum of IOUT+ and IOUT- LOCK Output Low IOL = +1mA LOCK Output High IOH = -100µA Differential Input Voltage Swing MIN TYP MAX MAX3771 63 MAX3770 81 MAX3771 57 MAX3770 67.5 91 780 1000 400 112 10.5 UNITS mA mVp-p mA 0.7 V 2200 mVp-p 2.4 V 200 Input Common-Mode Voltage VCC - 0.45 V Voltage at FILT+, FILT- VCC - 1.03 V CLOCKEN and LOCKEN Input Current -5 Differential Input Resistance Differential Output Resistance OUT+, OUT-, CLK+, CLK- µA 132 150 181 Ω 132 150 181 Ω Note 1: Supply current includes output currents. 2 +5 _______________________________________________________________________________________ 2.125Gbps/1.063Gbps, 3.3V Fibre Channel Repeaters (VCC = +3.0V to +3.6V, TA = 0°C to +70°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER CONDITIONS MIN TYP MAX UNITS OPERATION AT 2.125Gbps Edge Speed 20% to 80% Random Jitter Generation at Data Output TA = +25°C Deterministic Jitter Generation TA = +25°C Jitter Tolerance TA = +25°C (Note 5), input = CJTPAT (Note 6) CDR Lock Time from Start Input = CJTPAT (Note 6) 135 170 Input = K28.7+ (Note 2) 3.4 5.3 Input = CRPAT (Note 3) 2.3 3.1 Input = CRPAT (Notes 3, 5) 3.9 7.3 Input = K28.5± (Note 4) 15.6 22 27 48 Input = CRPAT (Notes 3, 5) f = 85kHz (Note 7) 1.5 4.22 f = 1270kHz (Note 7) 0.1 0.89 f = 10MHz psRMS psp-p UI 0.36 4.4 Propagation Delay Clock to Q Delay ps 50 ms 1000 1500 ps 240 300 ps OPERATION AT 1.063Gbps Random Jitter Generation at Data Output TA = +25°C Deterministic Jitter Generation TA = +25°C Jitter Tolerance TA = +25°C (Note 5), input = CJTPAT (Note 6), BER = IE-12 Input = K28.7+ (Note 2) 3.9 Input = CRPAT (Note 3) 2.3 Input = CRPAT (Notes 3, 5) 3.4 Input = K28.5± (Note 4) 17 psp-p Input = CRPAT (Notes 3, 5) 36 psp-p f = 42.5kHz 3.1 f = 635kHz 0.54 f = 5MHz 0.3 psRMS ps/rms UI Note 2: K28.7+ pattern: 0011111000 Note 3: Compliant random pattern (CRPAT) in hex: Pattern No. of Occurrences 3EAA2AAAAA 6 3EAAA6A5A9 1 86BA6C6475 D0E8DCA8B4 7949EAA665 16 72319A95AB 1 C16AAA9AA6 1 Note 4: K28.5± pattern: 00111110101100000101 Note 5: Random and deterministic jitter generation at 2.125Gbps is measured with 0.38UI deterministic jitter, and 0.22UI random jitter (BER = 1 x 10-12) applied to the input. Random and deterministic jitter generation at 1.063Gbps is measured with 0.18UI deterministic jitter, and 0.08UI random jitter (BER = 1 x 10-12) applied to the input. Jitter tolerance at 2.125Gbps is measured with 0.38UI deterministic jitter and 0.22UI random jitter (BER = 1 x 10-12) applied to the input. Jitter tolerance at 1.063Gbps is measured with 0.18UI deterministic jitter, and 0.08UI jitter (BER = 1 x 10-12) applied to the input. Note 6: Compliant jitter tolerance pattern in hex (CJTPAT): Pattern No. of Occurrences 3EAA2AAAAA 6 3EAAA6A5A9 1 871E3871E3 41 871E3870BC78F4AAAAAA 1 AAAAAAAAAA 12 AAA15555E3 871E3871E1 1 AB9C9686E6 1 C16AAA9AA6 1 Note 7: Jitter tolerance measurements at 85kHz and 1270kHz are limited by test equipment. Actual jitter tolerance > indicated. _______________________________________________________________________________________ 3 MAX3770/MAX3771 AC ELECTRICAL CHARACTERISTICS Pin Description PIN NAME 1 FILT+ PLL Loop Filter Connection. Connect a 0.22µF capacitor between FILT+ and FILT-. 2 FILT- PLL Loop Filter Connection. Connect a 0.22µF capacitor between FILT+ and FILT-. 3, 6, 12 GND Ground 4 IN+ Positive CML Data Input (Figure 3) 5 IN- Negative CML Data Input (Figure 3) 7, 8 VCC Supply Voltage 9 LOCKEN 10 OUT- Negative 75Ω CML Data Output (Figure 4) 11 OUT+ Positive 75Ω CML Data Output (Figure 4) 13 CLKEN When this input is forced high, the clock output is enabled. Ground for normal operation. 14 CLK- Negative 75Ω CML Clock Output (Figure 4). Enabled when CLKEN is forced high; disabled when CLKEN is forced low. 15 CLK+ Positive 75Ω CML Clock Output (Figure 4). Enabled when CLKEN is forced high; disabled when CLKEN is forced low. 16 LOCK Frequency Lock Indicator. High level indicates the PLL is frequency-locked. Disabled when LOCKEN is forced low. The output of the LOCK pin may chatter when large jitter is applied to the input. FUNCTION When this input is forced high, the lock indicator is enabled. Ground for normal operation. Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) -5 -10 -15 CJTPAT VCC = 3.3V CF = 0.1µF -25 10k 100k 1M 10M JITTER FREQUENCY (Hz) 4 100M 1G VCC = 3.3V CJTPAT MAX3770/1 toc03 CJTPAT VCC = 3.3V CF = 0.1µF DATA 1 0.1 FIBRE CHANNEL SINUSOIDAL JITTER MASK CLOCK ADDITIONAL 0.6UI DJ AND RJ APPLIED ABOVE 10MHz 0.01 1k MAX3770/1 toc02 0 10 SINUSOIDAL INPUT JITTER (UI) MAX3770/1 toc01 5 -20 MAX3770 RECOVERED DATA AND CLOCK SIGNALS MAX3770 JITTER TOLERANCE MAX3770 JITTER TRANSFER JITTER TRANSFER (dB) MAX3770/MAX3771 2.125Gbps/1.063Gbps, 3.3V Fibre Channel Repeaters 10k 100k 1M 10M 100M VCLK100ps/div JITTER FREQUENCY (Hz) _______________________________________________________________________________________ 2.125Gbps/1.063Gbps, 3.3V Fibre Channel Repeaters MAX3770/MAX3771 VOUT+ 200mVp-p MIN 500mVp-p MAX VOUT- (VOUT+) - (VOUT-) 400mVp-p MIN 1000mVp-p MAX Figure 1. Example of Output Signal with RLOAD = 150Ω 0.22µF FILT+ FILT- LOCKEN LOCK VCC MAX3770 MAX3771 LOCK IN+ 75Ω 75Ω CLK+ PHASE/FREQ DETECTOR 150Ω LOOP FILTER VCO IN- CLKCLKEN TTL VCC 75Ω 75Ω OUT+ D LATCH Q OUT- Figure 2. Functional Diagram _______________________________________________________________________________________ 5 MAX3770/MAX3771 2.125Gbps/1.063Gbps, 3.3V Fibre Channel Repeaters Detailed Description Figure 2 shows the functional diagram of the MAX3770 Fibre Channel repeater IC. The MAX3770 consists of a fully integrated phased-lock loop (PLL), CML input and output buffers, and a data latch. The PLL consists of a phase/frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO). The input and output signal buffers employ low-noise CML architecture and are terminated on-chip. Phase and Frequency Detector The phase/frequency detector generates an output signal that reflects the phase relationship between the incoming data and the internal clock generated by the VCO. Data recovery is accomplished by feedback in the PLL, which drives the error voltage to zero, aligning the falling edge of the recovered clock to the center of the data eye. The phase frequency detector generates a frequency lock indication that can be monitored at the LOCK pin (Table 1). When the PLL is frequency-locked onto the incoming data, lock transitions high. VCC PACKAGE ESD STRUCTURES 1kΩ 1.5nH IN+ 0.2pF 0.4pF 1.5nH 0.2pF 0.4pF 75Ω 75Ω VCC - 0.450V Figure 3. Input Structure VCC VCO and Latch The fully integrated VCO contains an internal current reference and filter circuitry to minimize the influence of V CC noise. The VCO is trimmed to 2.125GHz (MAX3770) and creates a clock output with frequency proportional to the control voltage applied by the loop filter. Data recovery is accomplished by using the recovered clock signal to latch the incoming data to the CML output buffers, significantly reducing the output jitter. PACKAGE 75Ω 75Ω 1.5nH OUT+ 0.4pF 1.5nH 0.4pF Applications Information Figures 3 and 4 show models for the MAX3770/MAX3771 inputs and outputs, including package parasitics. Figure 5 shows typical 50Ω termination applications. 0.2pF OUT0.2pF ESD STRUCTURES 10.5mA Design Procedure The MAX3770’s performance can be greatly affected by circuit board layout and design. Use good high-frequency design techniques, including minimizing ground inductance and using fixed-impedance transmission lines on the data and clock signals. All IN, OUT, and CLK pins can be connected with 0.1µF or 0.01µF coupling capacitors. If DC coupling is desired, pay particular attention to the DC voltage and current requirements at the pins of interest (see DC Electrical Characteristics). The MAX3750/MAX3751 port bypass circuit can be DC-coupled to the MAX3770/MAX3771 repeater. A 0.22µF capacitor should be used for the loop filter. 6 Figure 4. Output Structure Control Functions The lock enable (LOCKEN) and clock enable (CLKEN) pins can be configured to control the PLL’s clock. Table 1 shows the operational modes available. _______________________________________________________________________________________ 2.125Gbps/1.063Gbps, 3.3V Fibre Channel Repeaters MAX3770/MAX3771 75Ω DIFF (LOOKING OUT) 0.1µF 0.1µF Zo = 50Ω IN+ Zo = 50Ω OUT+ MAX3770 MAX3771 300Ω Zo = 50Ω 300Ω OUT- IN- Zo = 50Ω 0.1µF 0.1µF 100Ω DIFF (LOOKING IN) 150Ω DIFF (LOOKING OUT) 43Ω 43Ω Zo = 50Ω IN+ Zo = 50Ω OUT+ MAX3770 MAX3771 176Ω Zo = 50Ω IN- 176Ω OUT- Zo = 50Ω 43Ω 43Ω 100Ω DIFF (LOOKING IN) Figure 5. 50Ω Termination Applications Chip Topography Table 1. Output States When Using Control Functions INPUT PIN LEVEL LOCKEN CLKEN GND GND OUTPUT FUNCTION LOCK CLOCK Disabled Disabled GND VCC Disabled Enabled VCC VCC GND VCC Enabled Enabled Disabled Enabled FILT+ LOCK FILT- CLK+ GND CLK- IN+ CLKEN IN- GND 0.066" (1.676mm) GND OUT+ VCC OUT- VCC LOCKEN 0.067" (1.702mm) TRANSISTOR COUNT: 1217 SUBSTRATE CONNECTED to GND _______________________________________________________________________________________ 7 2.125Gbps/1.063Gbps, 3.3V Fibre Channel Repeaters QSOP.EPS MAX3770/MAX3771 Package Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.