19-2098; Rev 1; 1/02 Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater Features ♦ Pin Selectable 1.0625Gbps/2.125Gbps Dual-Rate Operation ♦ Meets Fibre Channel Jitter Tolerance ♦ 1400mV Typical Differential Output Swing ♦ 3.0V to 3.6V Operation ♦ No Reference Clock Required ♦ Frequency Lock Indication ♦ 1W Power Consumption (MAX3754) at +3.3V ♦ 150Ω or 100Ω Differential L-Port Impedance Available Pin Configuration LIN337 38 LOUT3GND LIN3+ 39 40 41 GND GND LOUT3+ 42 43 44 GND LIN2+ LIN245 46 Storage Area Networks LOUT2+ LOUT2- Fibre Channel Data Storage Systems 47 1.0625Gbps/2.125Gbps Dual-Rate Fibre Channel 48 Applications Fibre Channel Hubs 1 36 2 35 3 34 GND LOUT1- 4 33 LOUT1+ GND GND 6 8 29 ININ+ GND CLKEN 9 28 10 27 11 26 12 25 5 32 23 24 VCC 22 CDREN RATESEL 21 30 20 19 31 SEL3 SEL4 VCC 18 16 15 14 VCC SEL1 SEL2 13 VCC 7 17 MAX3754 MAX3755 CF+ CF- Typical Operating Circuit appears at end of data sheet. GND LIN1LIN1+ GND LOUT4+ LOUT4GND LIN4+ LIN4GND GND OUTOUT+ GND LOCK TQFP-EP* *EXPOSED PAD MUST BE CONNECTED TO GROUND Ordering Information PART TEMP RANGE PIN-PACKAGE DIFFERENTIAL LIN AND LOUT TERMINATION DIFFERENTIAL IN AND OUT TERMINATION MAX3754CCM 0°C to +70°C 48 TQFP-EP 150Ω 100Ω MAX3755CCM 0°C to +70°C 48 TQFP-EP 100Ω 100Ω ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3754/MAX3755 General Description The MAX3754/MAX3755 quad-port bypass circuits (PBCs) are designed for use in Fibre Channel Arbitrated Loop applications. Each consists of four serially connected port bypass circuits and a repeater that provides clock and data recovery. The quad-PBC allows connection of up to four Fibre Channel L-ports; each can be enabled or bypassed by individual logic inputs. To reduce the external parts count, all signal inputs and outputs have internal termination resistors. The MAX3754/MAX3755 comply with Fibre Channel jitter tolerance requirements and can recover data signals with up to 0.7 unit intervals (UIs) of high-frequency jitter. These devices operate from a single +3.3V supply. MAX3754/MAX3755 Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater ABSOLUTE MAXIMUM RATINGS VCC ...........................................................................-0.5V to +5V Current into OUT±, LOUT1±, LOUT2±, LOUT3±, LOUT4±.......................................................... 22mA Voltage at OUT±, LOUT1±, LOUT2±, LOUT3±, LOUT4± .....................(VCC - 1.65V) to (VCC + 0.5V) Voltage at IN±, LIN1±, LIN2±, LIN3±, LIN4±......................................................-0.5V to (VCC + 0.5V) Voltage at CLKEN, CF+, CF-, CDREN, RATESEL, SEL_, LOCK............................................-0.5V to (VCC + 0.5V) Current into LOCK...............................................-1mA to +10mA Continuous Power Dissipation (TA = +70°C) 48-Pin TQFP-EP (derate 30.0mW/°C above +70°C) ...........2W Operating Junction Temperature Range ...........-55°C to +150°C Operating Temperature Range .........................-55°C to +110°C Storage Temperature Range .............................-55°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, CLKEN = GND, 8B/10B data coding, CF = 0.047µF, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) PARAMETER CONDITIONS CDREN = GND Supply Current (Note 1) CDREN = VCC Input Data Rate Range MIN MAX MAX3754 245 285 MAX3755 285 334 MAX3754 308 362 MAX3755 349 -100 +100 2.125Gbps operation, RATESEL = VCC -100 +100 200 2200 VCC 0.45 Input Common-Mode Voltage RLOAD = RSOURCE UNITS mA 411 1.0625Gbps operation, RATESEL = GND Differential Input Voltage Swing Differential Output Voltage Swing TYP ppm mVP-P V 1000 1400 1800 mVP-P Differential L-Port Input Resistance MAX3754 118 150 182 MAX3755 78 100 122 Differential L-Port Output Resistance MAX3754 118 150 182 MAX3755 78 100 122 Differential Input Resistance at IN± 78 100 122 Ω Differential Output Resistance at OUT± 78 100 122 Ω 0.8 V 50 µA TTL Low Input Voltage TTL High Input Voltage 2 TTL Input Current 0 ≤ TTL input voltages ≤ VCC LOCK Output Low Voltage IOL = +1mA (sinking) LOCK Output High Voltage IOH = -100µA (sourcing) -50 Data Propagation Delay 2 0.4 V V VCC IN± to OUT±, SEL_ = GND, CDREN = VCC 3 LIN(n)± to LOUT(n+1)±, LIN4± to OUT± 1 _______________________________________________________________________________________ Ω V 2.4 Differential Voltage across CF± Ω V ns Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater (VCC = +3.0V to +3.6V, CLKEN = GND, 8B/10B data coding, CF = 0.047µF, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) PARAMETER CONDITIONS Channel Select Delay to Data Valid SEL(n)± to LOUT(n+1)± , SEL4 to OUT± Data Transition Time 20% to 80% Supply Noise Tolerance (Note 2) MIN TYP MAX 9 65 110 10Hz ≤ f < 100Hz 100 100Hz ≤ f < 1MHz 40 1MHz ≤ f < 2.5GHz 10 CDR Lock Time ns 160 Deterministic Jitter at OUT±, L-Port Outputs± µs 1.6 4.1 psRMS 3 Pattern = K28.5+, CDREN = GND (Note 7) 29 60 Pattern = K28.5+, CDREN = VCC 19 50 Pattern = RPAT, CDREN = VCC (Notes 6, 8, 9) 28 50 Total Jitter at OUT±, LOUT_± Pattern = RPAT, CDREN = VCC (Notes 6, 8, 9) Sinusoidal Component of Jitter Tolerance (BER = 10-12) Pattern = CJTPAT (Notes 6, 10) f = 85kHz sine wave ps mVP-P 530 OPERATION AT 2.125Gbps (Note 3) Pattern = K28.7, CDREN = GND (Note 4) Random Jitter at OUT±, Pattern = K28.7, CDREN = VCC L-Port Outputs± Pattern = CRPAT, CDREN = VCC (Notes 5, 6) UNITS 105 psP-P psP-P 1.5 f = 1.27MHz sine wave 0.1 f = 10MHz sine wave 0.1 UI Deterministic Jitter Tolerance CJTPAT (Note 10) 0.4 UI Total High-Frequency Jitter Tolerance Pattern = CJTPAT (Notes 6, 10, 11) 0.7 UI Jitter Transfer Bandwidth Jitter Transfer Peaking 6 (Note 12) OPERATION AT 1.0625Gbps (Note 3) Pattern = K28.7, CDREN = GND (Note 4) Random Jitter at OUT±, Pattern = K28.7, CDREN = VCC L-Port Outputs± Pattern = CRPAT, CDREN = VCC (Notes 5, 6) Deterministic Jitter at OUT±, L-Port Outputs± 10 MHz 0.05 dB 1.7 psRMS 5.4 3.8 Pattern = K28.5+, CDREN = GND (Note 7) 27 60 Pattern = K28.5+, CDREN = VCC 19 50 Pattern = RPAT, CDREN = VCC (Notes 6, 8, 9) 37 75 Total Jitter at OUT±, LOUT_± Pattern = RPAT, CDREN = VCC (Notes 6, 8, 9) Sinusoidal Component of Jitter Tolerance (BER = 10-12) Pattern = CJTPAT (Notes 6, 10) 135 f = 42.5kHz sine wave 1.5 f = 635kHz sine wave 0.1 f = 5MHz sine wave 0.1 psP-P psP-P UI _______________________________________________________________________________________ 3 MAX3754/MAX3755 ELECTRICAL CHARACTERISTICS (continued) MAX3754/MAX3755 Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, CLKEN = GND, 8B/10B data coding, CF = 0.047µF, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) PARAMETER Deterministic Jitter Tolerance Total High-Frequency Jitter Tolerance CONDITIONS CJTPAT (Note 10) MIN 0.4 Pattern = CJTPAT (Notes 6, 10, 11) 0.7 Jitter Transfer Bandwidth Jitter Transfer Peaking TYP MAX UNITS UI UI 3 (Note 12) 5 MHz 0.05 dB Includes output currents. Meets jitter output specifications with noise applied. AC characteristics are guaranteed by design and characterization. K28.7 Pattern: 00 1111 1000 Compliant Random Pattern in hex (CRPAT): Pattern Sequence: Repetitions: 3E AA 2A AA AA 6 3E AA A6 A5 A9 1 86 BA 6C64 75 D0 E8 DC A8 B4 79 49 EA A6 65 16 72 31 9A 95 AB 1 C1 6A AA 9A A6 1 Note 6: Parameter measured with 0.40UI deterministic and 0.20UI random jitter (BER = 10-12 ) applied to the input. All ports are bypassed, SEL_ = TTL low. Jitter is in compliance with the inter-enclosure, Fibre Channel jitter tolerance (at compliance point αR) and jitter output (at compliance point αT) specifications (FC-PI rev 10.0). Output jitter is specified as an output total given a non-zero jitter input. Note 7: K28.5± Pattern: 00 1111 1010 11 0000 0101 Note 8: Random Pattern in Hex (RPAT): 3EB0 5C67 85D3 172C A856 D84B B6A6 65 Note 9: Using differential drive over the entire input amplitude range. The input signal bandwidth is limited to 0.75 ✕ (bit-rate) by a 4th-order Bessel-Thompson filter or equivalent. Total jitter (TJ) is the range of the eye pattern where the bit error rate exceeds 10-12. TJ can be estimated as TJ = DJ + (14 ✕ RJ). DJ is deterministic jitter. RJ is one sigma distribution (RMS) of random jitter. Note 10: Compliant Jitter Tolerance Pattern in Hex (CJTPAT): Pattern Sequence: Repetitions: 3E AA 2A AA AA 6 3E AA A6 A5 A9 1 87 1E 38 71 E3 41 87 1E 38 70 BC 78 F4 AA AA AA 1 AA AA AA AA AA 12 AA A1 55 55 E3 87 1E 38 71 E1 1 AB 9C 96 86 E6 1 C1 6A AA 9A A6 1 Note 11: Parameter measured with 0.1UI sinusoidal jitter at 10MHz for 2.125Gbps data rate, or 5MHz for 1.0625Gbps. Note 12: Simulation shows peaking of 0.01dBm max. Characterization results limited by test equipment. Note 1: Note 2: Note 3: Note 4: Note 5: 4 _______________________________________________________________________________________ Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater OUTPUT EYE DIAGRAM AT OUT± (1.0625Gbps CRPAT, CDR ENABLED) CDR ENABLED 300 280 INPUT = 400mVP-P DJ = 0.4UI RJ = 0.2UI 200mV/ div 260 INPUT = 400mVP-P DJ = 0.4UI RJ = 0.2UI 200mV/ div CDR DISABLED 240 220 200 20 30 40 50 60 100ps/div 200ps/div 70 TEMPERATURE (°C) 1.0625Gbps CRPAT AT INPUT (DJ = 0.4UI, RJ = 0.2UI) 0.2 0.4 0.6 0.8 2.125Gbps CRPAT AT INPUT (DJ = 0.4UI, RJ = 0.2UI) 0 1.0 0.2 0.4 0.6 0.8 DATA SAMPLING TIME RELATIVE TO FIRST ZERO CROSSING (UI) DATA SAMPLING TIME RELATIVE TO FIRST ZERO CROSSING (UI) JITTER TOLERANCE 1.0625Gbps JITTER TOLERANCE 2.125Gbps 10 CJTPAT DJ = 0.4UI RJ = 0.2UI 10 SINUSOIDAL JITTER (UIP-P) 0 1 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 1 FIBRE CHANNEL MASK 0.1 0.01 CJTPAT DJ = 0.4UI RJ = 0.2UI 1.0 MAX3754 toc07 BIT ERROR RATE MAX3754 toc04 1 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 MAX3754 toc05 OUTPUT JITTER BATHTUB PLOT (2.125Gbps) OUTPUT JITTER BATHTUB PLOT (1.0625Gbps) MAX3754 toc06 10 BIT ERROR RATE 0 SINUSOIDAL JITTER (UIP-P) SUPPLY CURRENT (mA) 320 MAX3754 toc03 MAX3754 toc01 340 OUTPUT EYE DIAGRAM AT OUT± (2.125Gbps CRPAT, CDR ENABLED) MAX3754 toc02 SUPPLY CURRENT vs. TEMPERTURE (MAX3754) 1 FIBRE CHANNEL MASK 0.1 0.01 10k 100k 1M FREQUENCY (Hz) 10M 10k 100k 1M 10M FREQUENCY (Hz) _______________________________________________________________________________________ 5 MAX3754/MAX3755 Typical Operating Characteristics (VCC = +3.3V, CF = 0.047µF, TA = +25°C, unless otherwise noted.) Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater MAX3754/MAX3755 Pin Description 6 PIN NAME DESCRIPTION 1, 4, 7, 8, 11, 26, 29, 30, 33, 36, 39, 42, 43, 46 GND Electrical Ground 2 LIN1- Inverted Data Input for L-Port 1 3 LIN1+ Noninverted Data Input for L-Port 1 5 LOUT1- Inverted Data Output for L-Port 1 6 LOUT1+ Noninverted Data Output for L-Port 1 9 IN- Inverted Data Input 10 IN+ Noninverted Data Input 12 CLKEN Clock Enable. A TTL high level enables clock output at L-Port 1. 13, 16, 21, 24 VCC 14 CF+ Supply Voltage CDR Filter Capacitor Positive Connection. CF = 0.047µF. 15 CF- CDR Filter Capacitor Negative Connection. CF = 0.047µF. 17 SEL1 Select 1. A TTL low on SEL1 selects data from IN. TTL high on SEL1 selects data from LIN1. 18 SEL2 Select 2. A TTL low on SEL2 selects data from the previous port bypass circuit. A TTL high on SEL2 selects data from LIN2. 19 SEL3 Select 3. A TTL low on SEL3 selects data from the previous port bypass circuit. A TTL high on SEL3 selects data from LIN3. 20 SEL4 Select 4. A TTL low on SEL4 selects data from the previous port bypass circuit. A TTL high on SEL4 selects data from LIN4. 22 CDREN CDR Enable Input (TTL). A high input enables the CDR for data recovery. A low input disables the CDR (no data recovery). 23 RATESEL Rate Select Pin. TTL low selects 1.0625Gbps operation. TTL high selects 2.125Gbps operation. 25 LOCK 27 OUT+ Noninverted Data Output 28 OUT- Inverted Data Output 31 LIN4- Inverted Data Input for L-Port 4 32 LIN4+ Noninverted Data Input for L-Port 4 34 LOUT4- Inverted Data Output for L-Port 4 35 LOUT4+ Noninverted Data Output for L-Port 4 Frequency Lock Indicator. When data is present, a high level indicates the PLL is frequencylocked. The output of the LOCK pin may chatter when large jitter is applied to the input. 37 LIN3- Inverted Data Input for L-Port 3 38 LIN3+ Noninverted Data Input for L-Port 3 40 LOUT3- 41 LOUT3+ 44 LIN2- Inverted Data Input for L-Port 2 45 LIN2+ Noninverted Data Input for L-Port 2 Inverted Data Output for L-Port 3 Noninverted Data Output for L-Port 3 47 LOUT2- Inverted Data Output for L-Port 2 48 LOUT2+ Noninverted Data Output for L-Port 2 EP Exposed Pad The exposed pad must be soldered to the circuit board ground for proper thermal performance. _______________________________________________________________________________________ Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater MAX3754/MAX3755 0.047µF CF+ CF- RATESEL LOCK IN+ IN- LOOP FILTER PHASE/FREQ DETECTOR 100Ω 1 VCO CDREN CLKEN D Q 0 ÷2 1 0 0 1 0 0 0 0 1 1 1 1 SEL4 LIN4+ LIN4- LOUT4+ LOUT4- SEL3 LIN3+ LIN3- SEL2 LOUT3+ LOUT3- LIN2+ LIN2- LOUT2+ LOUT2- SEL1 LIN1+ LIN1- LOUT1+ LOUT1- 100Ω OUT+ OUT- OPTIONAL 100Ω OR 150Ω TERMINATION FOR LOUT AND LIN Figure 1. MAX3754/MAX3755 Functional Diagram Detailed Description The MAX3754/MAX3755 quad port bypass circuits (PBCs) consist of an input buffer, a rate-selectable clock and data recovery (CDR) circuit (for optional jitter attenuation), four serially connected port bypass circuits, and an output buffer (Figure 1). The circuit design is optimized for both 1.0625Gbps and 2.125Gbps operation at 3.3V. Input Buffer The input buffer provides line termination and level conversion. It accepts a differential input voltage of 200mV to 2200mV at IN±. Internal resistors terminate the inputs to 100Ω differentially eliminating the need for external resistors. Clock and Data Recovery The purpose of the CDR is to improve jitter transfer performance by attenuating jitter that may be present in the input data. The CDR can recover 1.0625Gpbs or 2.125Gbps data signals that are corrupted by up to 0.7UI of high-frequency jitter (BER = 10-12 ). When jitter attenuation is not needed, the CDR may be disabled in order to save power. The input buffer drives the CDR circuit, as well as one input of a 2:1 multiplexer. A TTL high on CDREN enables the CDR and connects the CDR data output to the port bypass circuits. The recovered clock signal is available for test purposes at LOUT1 when CLKEN is asserted high. A TTL low on CDREN disables the CDR and connects the output of the input buffer directly to the port bypass circuits. A RATESEL pin is included to switch the CDR between data rates. The VCO output has a divide-by-2 block that is switched into the PLL when RATESEL is TTL low for 1.0625Gbps operation (see Figure 1). Phase and Frequency Detector The frequency difference between the VCO clock and the received data is derived by sampling the in-phase and quadrature VCO outputs on the edges of the input data signal. The frequency detector drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition is complete, the phase detector produces a voltage proportional to the phase difference between the incoming data and the internal clock. The PLL drives this error voltage to zero, aligning the recovered clock to the center of the incoming eye. _______________________________________________________________________________________ 7 MAX3754/MAX3755 Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater Loop Filter, VCO, and Latch The phase detector and frequency detector outputs are summed into a loop filter. An external capacitor (between CF+ and CF-) is required to set the PLL damping factor. The fully integrated VCO contains an internal current reference and filter circuitry to minimize the influence of VCC noise. The VCO creates a clock output with frequency proportional to the control voltage applied by the loop filter. Data recovery is accomplished by using the recovered clock signal to latch the incoming data to the CML output buffers, significantly reducing output jitter. LOCK Output An active high LOCK output monitor derived from the frequency detector indicates that the PLL is frequency locked onto the input data. Without input data, the LOCK signal may settle at TTL High or TTL Low. The use of a low-pass RC filter is recommended to reduce the effects of chatter that could be caused by a high input jitter content. RATESEL Input The RATESEL input is used to select between input data rates of 2.125Gbps and 1.0625Gbps. This function allows the repeater to sample data at the correct data rate by selecting an optional a divide-by-2 network. RATESEL selects between the VCO tuned frequency and half that frequency, allowing maximum jitter tolerance at both data rates. The loop bandwidth of the repeater scales with the selected frequency; i.e., the loop-bandwidth at an input rate of 1.0625Gbps is half that at the input rate of 2.125Gbps. Port Bypass Circuits The output of the 2:1 input multiplexer drives a cascaded series of four PBCs. Each PBC consists of a differential output buffer, a differential input buffer, and a 2:1 multiplexer. The multiplexer select input (SEL_) controls whether a port is included in the loop. A TTL low on a multiplexer select pin routes the data signal from the previous stage to the multiplexer output (port bypass mode). A TTL high on the multiplexer select pin routes the data signal from the input buffer to the multiplexer output (port enable mode). The output of the last PBC drives the output buffer. The MAX3754 has 150Ω differential termination on the inputs and 75Ω single-ended terminations to VCC on the outputs (see Input/Output Structures for specifics) of the L-ports to match Fibre Channel Arbitrated Loop specifications. The MAX3755 is terminated with 100Ω and 50Ω, respectively. Testing a MAX3754 using standard 50Ω test equipment requires an impedance matching network 8 Output Buffer The output signal of the last PBC drives the differential high-power output buffer. The output buffer drives the output port (OUT±). Internal resistors terminate each output with 50Ω to VCC (100Ω differentially), eliminating the need for external termination resistors. The output buffer produces a differential peak-to-peak output voltage of 1V to 1.8V when driving a differential load. Applications Information The MAX3754/MAX3755 quad-PBC is designed for hard-disk array applications using the Fibre Channel Arbitrated Loop network protocol. In applications where data storage reliability is critical, it may be desirable to create a disk array where the data is stored redundantly on more than one physical drive. The Fibre Channel Arbitrated Loop protocol enables multiple physical drives to be connected in a loop topology. Each physical drive is connected to the Fibre Channel loop through an L-port that may be individually addressed and controlled to create an array of logical drives. Data is transmitted over the loop as an encoded serial bit stream. Using the Fibre Channel Arbitrated Loop protocol, the configuration of the disk array can be rearranged under software control to achieve desired objectives (such as data reliability or fast access). The port bypass circuit allows any L-port to be enabled (connected to the loop) or bypassed (disconnected from the loop) while the loop is operating. This enables hot swapping of physical drives (inserting or removing physical drives while the loop is operating) so that drives may be replaced with minimal disruption to the disk array system. Figure 2 shows a disk array. Filter Capacitor Requirements The MAX3754/MAX3755 phase lock loop’s (PLL) filter capacitor is required to be supplied in a port bypass design. This capacitor sets the damping factor of the device. It also determines how fast the PLL can acquire initial lock. This device is specified and tested with the recommended filter capacitor value of 0.047µF that limits transfer peaking. Input/Output Structures Figures 3 and 4 show models for the MAX3754/ MAX3755 inputs and outputs, modeling package parasitics, and ESD diodes. Cascading Port Bypass Circuits Two or more MAX3754/MAX3755 quad-PBCs can be cascaded by directly connecting the OUT± pins of one _______________________________________________________________________________________ Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater MAX3754/MAX3755 IN± IN± MAX377x MAX377x MAX377x MAX377x MAX377x MAX377x MAX377x MAX377x MAX377x MAX377x MAX377x MAX377x PRIMARY LOOP MAX377x 1 MAX3750 PBC 0 MAX377x MAX375x PBC MAX375x PBC MAX377x REPEATER REPEATER MAX377x MAX375x PBC MAX375x PBC MAX377x REPEATER REPEATER MAX377x MAX375x PBC MAX375x PBC MAX3750 PBC MAX377x REPEATER PORT CONTROL FC-AL DRIVES PORT CONTROL REPEATER FAIL-OVER LOOP MAX377x OUT± OUT± Figure 2. Disk Array Implemented with Port Bypass Circuits _______________________________________________________________________________________ 9 MAX3754/MAX3755 Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater PACKAGE PARASITICS DIE VCC ESD STRUCTURES 1.2kΩ 2.2nH 0.2pF 0.4pF 2.2nH 0.2pF 0.4pF 50Ω *(75Ω) 50Ω *(75Ω) VCC - 0.45V *MAX3754 LIN_ ± INPUTS Figure 3. MAX3754/MAX3755 Input Structure VCC quad-PBC to the IN± pins of the next quad-PBC. See Typical Operating Circuit. Layout Considerations 50Ω *(75Ω) 50Ω *(75Ω) DIE PACKAGE PARASITICS ESD STRUCTURES 2.2nH For best performance, carefully lay out the PC board using high-frequency techniques. Filter voltage supplies, keep ground connections short with multiple vias where possible. Use controlled impedance transmission lines to interface with the MAX3754/MAX3755 high-speed inputs and outputs. Power-supply decoupling capacitors should be placed very close to VCC pins. Isolate the input signals from the output signals as much as possible. OUT+ 0.4pF 2.2nH OUT0.4pF *MAX3754 LOUT_ ± OUTPUTS Figure 4. MAX3754/MAX3755 Output Structure 10 0.2pF ______________________________________________________________________________________ 0.2pF Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater IN OUT SEL IN OUT SEL LOUT2± LOUT1± LOUT2± CF+ CLKEN CF- RATESEL DOWNSTREAM L_PORT OUT- SEL4 CF 0.047µF IN- LIN4± SEL4 RATESEL LIN4± CF- LOUT4± CLKEN SEL3 CF+ Z0 = 50Ω OUT+ MAX3754 MAX3755 LOUT4± OUT- LOCK IN+ SEL3 MAX3754 MAX3755 VCC CDREN GND Z0 = 50Ω LIN3± OUT+ VCC LOUT3± LOCK IN+ LIN3± VCC CDREN GND INCF 0.047µF VCC SEL2 IN OUT SEL LIN2± IN OUT SEL SEL1 L_PORT n+5 LIN1± L_PORT n+4 SEL2 L_PORT n+1 LIN2± L_PORT n SEL1 DISK DRIVE LIN1± DISK DRIVE LOUT3± UPSTREAM L_PORT VCC DISK DRIVE LOUT1± VCC DISK DRIVE IN OUT SEL IN OUT SEL IN OUT SEL IN OUT SEL L_PORT n+2 L_PORT n+3 L_PORT n+6 L_PORT n+7 DISK DRIVE DISK DRIVE DISK DRIVE DISK DRIVE NOTE: ALL HIGH-SPEED INPUTS AND OUTPUTS (IN±, OUT±, LIN±, AND LOUT±) SHOULD BE CONNECTED USING CONTROLLEDIMPEDANCE TRANSMISSION LINES. AC-COUPLING MAY ALSO BE REQUIRED. ALL CAPACITORS ARE 0.1µF UNLESS OTHERWISE INDICATED. FIGURE SHOWS 1.0625Gbps OPERATION. FOR 2.125Gbps OPERATION, CONNECT RATESEL TO VCC. ______________________________________________________________________________________ 11 MAX3754/MAX3755 Typical Operating Circuit Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 48L,TQFP.EPS MAX3754/MAX3755 Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater 12 ______________________________________________________________________________________ Dual-Rate, 1Gbps/2Gbps Fibre Channel Quad-Port Bypass ICs with Repeater Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX3754/MAX3755 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)