19-1701; Rev 2; 2/01 2.125Gbps, 3.3V Quad-Port Bypass with Repeater ________________________Applications Features ♦ Four High-Speed Data Ports ♦ Meets Fibre Channel Jitter Tolerance Requirements ♦ Large Output Signal Swing (>1000mVp-p) ♦ +3.0V to +3.6V Single-Supply Voltage ♦ On-Chip Termination Resistors Compatible with 75Ω Transmission Lines at All Ports Ordering Information PART TEMP. RANGE MAX3752CCM 0°C to +70°C PIN-PACKAGE 48 TQFP-EP* *EP = Exposed pad 2.125Gbps Fibre Channel Fibre Channel Data Storage Systems Storage Area Networks Fibre Channel Hubs LIN3+ LIN337 38 39 LOUT3+ LOUT3GND 41 40 GND GND 42 43 44 GND LIN2+ LIN246 45 LOUT2+ LOUT247 48 1 36 2 35 3 34 4 33 5 32 6 31 MAX3752 7 30 23 24 VCC 22 CDREN LOCKEN 21 20 19 SEL3 SEL4 VCC VCC SEL1 SEL2 18 25 17 26 12 16 27 11 15 28 10 14 29 9 13 8 VCC GND LIN1LIN1+ GND LOUT1LOUT1+ GND GND ININ+ GND CLKEN CFP CFM Typical Operating Circuit appears at end of data sheet. Pin Configuration GND LOUT4+ LOUT4GND LIN4+ LIN4GND GND OUTOUT+ GND LOCK TQFP-EP* * Exposed pad is connected to ground. ________________________________________________________________ Maxim Integrated Products 1 For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX3752 General Description The MAX3752 quad-port bypass IC is designed for use in the Fibre Channel Arbitrated Loop topology. This device consists of four serially connected port bypass circuits (PBCs) and a repeater that provides clock and data recovery (CDR). The quad-port bypass circuit allows connection of up to four Fibre Channel L-Ports, which can each be enabled or bypassed by controlling the PBC select inputs. Additional quad PBCs can be cascaded for applications requiring more than four L-Ports. To reduce the external parts count, all signal inputs and outputs have internal termination resistors. The MAX3752 complies with Fibre Channel jitter tolerance requirements and can recover data signals with up to 0.7 unit intervals (UIs) of high-frequency jitter. When the repeater is not needed, it can be disabled to reduce power consumption. A fully integrated phase-locked loop (PLL) provides a frequency lock indication and does not need an external reference clock. MAX3752 2.125Gbps, 3.3V Quad-Port Bypass with Repeater ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC..............................................-0.5V to +5.0V Current into OUT+, OUT-, LOUT1+, LOUT1-, LOUT2+, LOUT2-, LOUT3+, LOUT3-, LOUT4+, LOUT4- ......................0 to 22mA Voltage at OUT+, OUT-, LOUT1+, LOUT1-, LOUT2+, LOUT2-, LOUT3+, LOUT3-, LOUT4+, LOUT4-....................................... .......................................................(VCC - 1.65V) to (VCC + 0.5V) Voltage at IN+, IN-, LIN1+, LIN1-, LIN2+, LIN2-,LIN3+, LIN3-, LIN4+, LIN4-. ..........................................-0.5V to (VCC + 0.5V) Voltage at CLKEN, CFP, CFM, SEL1, SEL2, SEL3, SEL4, CDREN, LOCKEN.......................................-0.5V to (VCC + 0.5V) Voltage at LOCK.........................................-0.5V to (VCC + 0.5V) Current at LOCK .................................................-10mA to +1mA Continuous Power Dissipation (TA = +70°C) TQFP-EP (derate 27.0mW/°C above +70°C) ......................2W Operating Junction Temperature Range ...........-55°C to +150°C Operating Temperature Range...............................0°C to +70°C Storage Temperature Range .............................-50°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = 0°C to +70°C. Typical values are at +3.3V, TA = +25°C, unless otherwise noted.) PARAMETER CONDITIONS MIN CDR disabled (CLKEN, CDREN, LOCKEN = GND) 193 269 225 CDR enabled (CLKEN, CDREN, LOCKEN = VCC) IN±, LINn± MAX UNITS 195 Supply Current (Note 1) Input Swing (Differential) TYP 255 200 353 2200 VCC 0.45 Input Common-Mode Voltage mA mVp-p V Output Voltage Swing (Differential) 150Ω load (OUT±, LOUTn±) 1000 1400 1600 mVp-p Input Resistance (Differential) (IN±, LINn±) 132 150 181 Ω Output Resistance (Differential) (OUT±, LOUTn±) 132 150 181 Ω TTL Input Voltage (Low) 0.8 TTL Input Voltage (High) 2 TTL Input Current 0 ≤ TTL input voltage ≤ VCC Lock Output Voltage (Low) IOL = +1mA, LOCKEN = HIGH Lock Output Voltage (High) IOH = -100µA, LOCKEN = HIGH Voltage at CFP, CFM 2 -50 0.4 2.4 V V 50 µA 0.7 V VCC 0.4 V VCC 1.03 V ______________________________________________________________________________________ 2.125Gbps, 3.3V Quad-Port Bypass with Repeater (VCC = +3.0V to +3.6V, TA = 0°C to +70°C. Typical values are at +3.3V, CF = 0.22µF, TA = +25°C, unless otherwise noted.) (Notes 2–7) PARAMETER CONDITIONS Output Edge Speed 20% to 80% Random Jitter at OUT± Deterministic Jitter at OUT± Total Jitter at OUT± Jitter Tolerance (BER = 10-12) TYP 75 115 Pattern = K28.7+, CDR disabled 1.5 Pattern = K28.7+, CDR enabled 2.3 Pattern = CRPAT, CDR enabled (Note 8) 3.6 MAX 39 82 27 47 Pattern = FC-RPAT, CDR enabled (Note 8, jitter applied) 52 80 72 Pattern = CRPAT, CDR enabled (Note 8, jitter applied) 100 f = 85kHz sine wave (Notes 8, 9) 1.5 >4.22 f = 1.27MHz sine wave (Notes 8, 9) 0.1 >0.85 f = 10MHz sine wave (Notes 8, 9) 0.1 >0.47 Total High-Frequency Jitter Tolerance BER = 10-12 (Note 10) CDR Lock Time Pattern = CJTPAT ps psRMS Pattern = K28.5, CDR enabled Pattern = CRPAT, CDR enabled UNITS Gbps 160 Pattern = K28.5, CDR disabled Deterministic Jitter Tolerance Propagation Delay MIN 2.125 ± 100ppm Data Rate psp-p psp-p UIp-p 0.38 UIp-p 0.7 UIp-p 4.4 ms IN± to OUT± (ports bypassed, CDR enabled) 10 LINn± to LOUT(n+1)± (port normal mode) 2 SEL(n) rising edge to data valid at LOUT(n+1)± or OUT± (port normal mode) 8 SEL(n) falling edge to data valid at LOUT(n+1)± or OUT± (port bypass mode) 8 ns _______________________________________________________________________________________ 3 MAX3752 AC ELECTRICAL CHARACTERISTICS—MAX3752 Operating at 2.125Gbps AC ELECTRICAL CHARACTERISTICS (continued) Note 1: Includes output currents. Note 2: AC characteristics are guaranteed by design and characterization. Note 3: K28.7+ Pattern: 0011 1110 00. Note 4: Fibre Channel Random Pattern in hex (FC-RPAT): 3EB0 5C67 85D3 172C A856 D84B B6A6 65. Note 5: Compliant Random Pattern in hex (CRPAT): Pattern Sequence Repetitions 3E AA 2A AA AA 6 3E AA A6 A5 A9 1 86 BA 6C64 75 D0 E8 DC A8 B4 79 49 EA A6 65 16 72 31 9A 95 AB 1 C1 6A AA 9A A6 1 Note 6: K28.5 Pattern: 0011 1110 1011 0000 0101. Note 7: Compliant Jitter Tolerance Pattern in Hex (CJTPAT): Pattern Sequence Repetitions 3E AA 2A AA AA 6 3E AA A6 A5 A9 1 87 1E 38 71 E3 41 87 1E 38 70 BC 78 F4 AA AA AA 1 AA AA AA AA AA 12 AA A1 55 55 E3 87 1E 38 71 E1 1 AB 9C 96 86 E6 1 C1 6A AA 9A A6 1 Note 8: Parameter measured with 0.38UI deterministic and 0.22UI random jitter (BER = 10-12) applied to the input. Note 9: Jitter tolerance measurement exceeds the capability of the test equipment used. Note 10: Parameter measured with 0.1UI sinusoidal jitter at 10MHz plus 0.38UI deterministic jitter applied to the input. Typical Operating Characteristics (TA = +25°C and VCC = +3.3V, unless otherwise noted.) REPEATER ENABLED MAX3752/3-03 MAX3752/3-02 MAX3752/3-01 300 275 DATA OUTPUT EYE DIAGRAM (2.125Gbps CJTPAT) DATA OUTPUT EYE DIAGRAM (1.0625Gbps CJTPAT) SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT (mA) MAX3752 2.125Gbps, 3.3V Quad-Port Bypass with Repeater 250 225 REPEATER DISABLED 200 100mV/div 100mV/div 175 150 125 100 0 10 20 30 40 50 60 70 200ps/div 100ps/div TEMPERATURE °(C) 4 _______________________________________________________________________________________ 2.125Gbps, 3.3V Quad-Port Bypass with Repeater MAX3752/3-04 1.00E+00 2Gbps CRPAT (NO JITTER ON INPUTS) 1.00E+02 2Gbps CRPAT (0.38UI DJ, 0.63UI TJ ON INPUTS) 1.00E+02 1.00E+04 BIT ERROR RATE 1.00E+04 1.00E+06 1.00E+08 1.00E+06 1.00E+08 1.00E+10 1.00E+10 1.00E+12 1.00E+12 1.00E+14 1.00E+14 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 DATA SAMPLING TIME RELATIVE TO FIRST ZERO CROSSING (UI) DATA SAMPLING TIME RELATIVE TO FIRST ZERO CROSSING (UI) INPUT VSWR vs. FREQUENCY (BY SIMULATION) OUTPUT VSWR vs. FREQUENCY (BY SIMULATION) MAX3752/3-07 4 MAX3752/3-06 4 3 VSWR 3 VSWR BIT ERROR RATE MAX3752/3-05 OUTPUT JITTER—BATHTUB PLOT OUTPUT JITTER—BATHTUB PLOT 1.00E+00 2 2 1 1 0.1 0.4 0.7 1.0 1.3 1.6 FREQUENCY (GHz) 1.9 2.2 2.5 0.1 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5 FREQUENCY (GHz) _______________________________________________________________________________________ 5 MAX3752 Typical Operating Characteristics (continued) (TA = +25°C and VCC = +3.3V, unless otherwise noted.) MAX3752 2.125Gbps, 3.3V Quad-Port Bypass with Repeater Pin Description PIN NAME 1, 4, 7, 8, 11, 26, 29, 30, 33, 36, 39, 42, 43, 46 GND 2 3 5 6 9 10 12 13,16, 21, 24 14 15 LIN1LIN1+ LOUT1LOUT1+ ININ+ CLKEN VCC CFP CFM 17 SEL1 Select 1. A TTL low on SEL1 selects data from IN±. TTL high on SEL1 selects data from LIN1±. 18 SEL2 Select 2. A TTL low on SEL2 selects data from the previous port bypass circuit. A TTL high on SEL2 selects data from LIN2±. 19 SEL3 Select 3. A TTL low on SEL3 selects data from the previous port bypass circuit. A TTL high on SEL3 selects data from LIN3±. 20 SEL4 Select 4. A TTL low on SEL4 selects data from the previous port bypass circuit. A TTL high on SEL4 selects data from LIN4±. 22 CDREN CDR Enable Input (TTL). A high input enables the CDR for data recovery. A low input disables the CDR (no data recovery). 23 LOCKEN 25 LOCK 27 28 31 32 34 35 37 38 40 41 44 45 47 48 EP OUT+ OUTLIN4LIN4+ LOUT4LOUT4+ LIN3LIN3+ LOUT3LOUT3+ LIN2LIN2+ LOUT2LOUT2+ Exposed Pad 6 FUNCTION Electrical Ground Inverted Data Input for L-Port 1 Noninverted Data Input for L-Port 1 Inverted Data Output for L-Port 1 Noninverted Data Output for L-Port 1 Inverted Data Input Noninverted Data Input Clock Enable. A TTL high level enables clock output at L-Port 1. Positive Supply Voltage CDR Filter Capacitor Positive Connection CDR Filter Capacitor Negative Connection Lock Enable Input (TTL). A high input enables the LOCK output. A low input disables the LOCK output. CDR Lock Output. Enabled by LOCKEN. A high output indicates the CDR PLL is locked. When LOCKEN is low, LOCK is high. Noninverted Data Output Inverted Data Output Inverted Data Input for L-Port 4 Noninverted Data Input for L-Port 4 Inverted Data Output for L-Port 4 Noninverted Data Output for L-Port 4 Inverted Data Input for L-Port 3 Noninverted Data Input for L-Port 3 Inverted Data Output for L-Port 3 Noninverted Data Output for L-Port 3 Inverted Data Input for L-Port 2 Noninverted Data Input for L-Port 2 Inverted Data Output for L-Port 2 Noninverted Data Output for L-Port 2 Ground. The exposed pad must be soldered to the circuit board for proper thermal performance. _______________________________________________________________________________________ LIN4- LIN4+ LOUT4- LOUT4+ LIN3- LIN3+ LOUT3- LOUT3+ LIN2- LIN2+ LOUT2- LOUT2+ LIN1- LIN1+ CLKEN LOUT1- CFM MAX3752 CF CFP LOUT1+ 2.125Gbps, 3.3V Quad-Port Bypass with Repeater TTLIN LOCK LOCKEN CDR CLK EN DIN DOUT IN+ IN- D1 D0 Q D0 Q D0 Q D0 Q D0 Q D0 Q D1 D1 D1 D1 D1 OUT+ OUTVCC MAX3752 TTLIN CDREN GND TTLIN TTLIN SEL1 TTLIN SEL2 TTLIN SEL3 SEL4 Figure 1. Functional Diagram Detailed Description The MAX3752 quad PBC consists of an input buffer, a clock/data recovery circuit (for optional data recovery), four serially connected port bypass circuits, and an output buffer (Figure 1). The circuit design is optimized for both high-speed (2Gbps) and low-voltage (+3.3V) operation. Input Buffer The input buffer provides line termination and level conversion. It accepts a differential input voltage of 200mV to 2200mV at the IN+ and IN- pins. Internal resistors terminate each input to 75Ω (150Ω total between the two inputs), eliminating the need for external termination resistors in most applications (see Applications Information for a suggested interface to 50Ω systems). Clock and Data Recovery The purpose of the clock and data recovery (CDR) is to improve jitter transfer performance by attenuating jitter that may be present in the input data. The CDR can recover data signals that are corrupted by up to 0.7UI of high-frequency jitter (BER = 10-12). When data recovery is not needed, the CDR may be disabled in order to save power. The input buffer drives the CDR circuit, as well as one input of a 2:1 multiplexer. A TTL high on the CDR enable pin (CDREN) enables the CDR and connects the CDR data output to the port bypass circuits. The recovered clock signal is available for test purposes at LOUT1 (the output of the first port bypass circuit) when the clock enable input (CLKEN) is set to a TTL high level. A TTL low on CDREN disables the CDR and connects the input buffer output directly to the port bypass circuits. Port Bypass Circuits The output of the 2:1 input multiplexer drives a cascaded series of four PBCs. Each PBC consists of a differential output buffer, a differential input buffer, and a 2:1 multiplexer. The multiplexer select input (SELn) controls which multiplexer input is connected to the multiplexer output. A TTL low on the multiplexer select pin causes the data signal from the previous stage to be connected to the multiplexer output (port bypass mode). A TTL high on the multiplexer select pin causes the data signal from the input buffer to be connected to the multiplexer output (port enable mode). The output of the last PBC drives the output buffer. Output Buffer The output signal of the last PBC drives the differential high-power output buffer. The output buffer drives the output port (OUT±). Internal resistors terminate each output to 75Ω (150Ω total between the two outputs), eliminating the need for external termination resistors in most applications (see Applications Information for a suggested interface to 50Ω systems). The output buffer produces a differential output voltage of 1000mV to 1600mV when driving a differential 150Ω load. _______________________________________________________________________________________ 7 MAX3752 2.125Gbps, 3.3V Quad-Port Bypass with Repeater PORT BYPASS SERIAL DATA IN IN OUT PORT BYPASS PORT BYPASS PORT BYPASS 0 0 0 0 MUX MUX MUX MUX 1 1 1 1 SEL IN OUT L-PORT L-PORT DISK DRIVE DISK DRIVE SEL IN BYPASSED OUT SERIAL DATA OUT SEL L-PORT DISK DRIVE Figure 2. Disk Array Implemented with Port Bypass Circuits Applications Information The MAX3752 quad-port bypass circuit is designed for hard disk array applications of the Fibre Channel Arbitrated Loop network protocol. A drive array is a collection of hard disk drives (called physical drives) that are connected together. The total storage capacity of the array of physical drives can be divided into one or more subsets (called logical drives) that may be spread over all of the physical drives in the array. For example, a computer accessing the drive array might “see” it as two logical drives (D: and E:, for example) that each have a storage capacity of 20GB, even though the actual array is made up of eight physical 5GB drives. In applications where data storage reliability is critical, it may be desirable to create a disk array where the data is stored redundantly on more than one physical drive. This type of system is generally called a redundant array of inexpensive disks (RAIDs). If a physical drive fails, it may be replaced and the lost data can be restored. Drive arrays are also useful in applications that require fast access to stored data. The data may be distributed over physical drives connected in a parallel arrangement, enabling access to data concurrently from multiple drives in the array. This makes it possible to achieve I/O 8 rates much greater than what is feasible with nonarrayed drives. The Fibre Channel Arbitrated Loop protocol enables multiple physical drives to be connected in a loop topology. Each physical drive is connected to the Fibre Channel loop through an L-Port that may be individually addressed and controlled to create the array of logical drives. Data is transmitted over the loop as an encoded serial bit stream. Using the Fibre Channel Arbitrated Loop protocol, the configuration of the disk array can be rearranged under software control to achieve desired objectives (such as data reliability or fast access). The port bypass circuit allows any L-Port to be enabled (connected to the network) or bypassed (disconnected from the network) while the network is operating. This enables hot swapping of physical drives (inserting or removing physical drives while the network is operating) so that drives may be replaced with minimal disruption to the disk array system. Figure 2 shows the disk array. Input/Output Structures Figures 3 and 4 show models for the MAX3752 inputs and outputs. _______________________________________________________________________________________ 2.125Gbps, 3.3V Quad-Port Bypass with Repeater DIE MAX3752 PACKAGE PARASITICS VCC ESD STRUCTURES 1k 2.2nH 0.2pF 0.4pF 2.2nH 0.2pF 0.4pF 75Ω 75Ω VCC - 0.45V Figure 3. MAX3752 Input Structure Cascading Port Bypass Circuits Two or more MAX3752 quad PBCs can be cascaded by directly connecting the OUT+ and OUT- pins of one quad PBC to the IN+ and IN- pins of the next quad PBC. See Typical Operating Circuit. Interfacing to 50Ω Systems Figure 5 shows examples of resistive impedance transforming networks that can be used to interface between the 75Ω input/output structure of the MAX3752 and 50Ω systems. The characteristics of the two examples shown can be derived by referring to Figures 3, 4, and 5. The top configuration in Figure 5 is useful in designs where the parallel 300Ω resistors can be placed very close to the input/output pins of the IC. In this case, the 50Ω transmission lines should connect directly to the IC. The bottom configuration in Figure 5 provides a better impedance match than the top configuration for designs where 75Ω transmission lines are connected between the input/output pins of the IC and the resistive impedance transforming networks. Neither of the two configurations in Figure 5 provides 100% efficient voltage coupling. In the top configuration, the input voltage (VIN) is the same as the source voltage (VSRC), but the output/load voltage (VOUT = VLOAD for this case) is reduced by a factor of 0.67 because the output is loaded with an equivalent of 75Ω. (The data sheet specification for output voltage swing is based on a 150Ω load.) In the bottom configuration, VIN is attenuated by a factor of 0.64 from VSRC, and VLOAD is attenuated by a factor of 0.43 from VOUT. For example, a source voltage of 625mV will result in an input voltage of 625mV for the top configuration, but only 400mV for the bottom configuration. Also, a typical output voltage swing of 1400mV into a differential 150Ω load will cause the corresponding load voltage to be _______________________________________________________________________________________ 9 MAX3752 2.125Gbps, 3.3V Quad-Port Bypass with Repeater DIE VCC 940mV for the top configuration and 600mV for the bottom configuration. PACKAGE PARASITICS Layout Considerations 75Ω ESD STRUCTURES 75Ω 2.2nH OUT+ 0.4pF 0.2pF 2.2nH OUT0.4pF For best performance, carefully lay out the PC board using high-frequency techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled impedance transmission lines to interface with the MAX3752 high-speed inputs and outputs. Power-supply decoupling capacitors should be placed very close to VCC pins. Isolate the input signals from the output signals as much as possible. 0.2pF 19mA Figure 4. MAX3752 Output Structure 50Ω Z0 = 50Ω IN+ Z0 = 50Ω OUT+ + ± VSRC 300Ω - RLOAD = 100Ω 300Ω MAX3752 + VLOAD - 50Ω IN- Z0 = 50Ω Z0 = 50Ω OUT- VLOAD = 0.67VOUT VIN = VSRC 50Ω 43Ω Z0 = 50Ω 43Ω Z0 = 75Ω IN+ OUT+ Z0 = 75Ω Z0 = 50Ω + ± VSRC 176Ω - 50Ω 43Ω Z0 = 50Ω RLOAD = 100Ω 176Ω MAX3752 43Ω Z0 = 75Ω VIN = 0.64VSRC IN- OUT- Z0 = 75Ω Z0 = 50Ω VLOAD = 0.43VOUT Figure 5. Interfaces to 50Ω Systems 10 ______________________________________________________________________________________ + VLOAD - 2.125Gbps, 3.3V Quad-Port Bypass with Repeater DISK DRIVE DISK DRIVE DISK DRIVE DISK DRIVE L_PORT n L_PORT n+1 L_PORT n+4 L_PORT n+5 IN OUT SEL IN OUT SEL IN OUT SEL IN OUT SEL 2 2 2 SEL4 LIN4 LOUT4 2 CF 0.47µF LIN2 SEL2 LOUT2 SEL1 LOUT1 LOCK IN+ OUT+ MAX3752 IN- OUT- CFP CLKEN CFM LOCKEN 2 2 2 N.C. DOWNSTREAM L_PORT LOCKEN SEL3 CLKEN CFM LIN3 CFP Z0 = 75Ω CDREN SEL4 OUT- VCC GND LIN4 IN- Z0 = 75Ω 2 VCC LOUT4 OUT+ MAX3752 N.C. 2 SEL3 LOCK VCC 2 LIN3 CDREN GND IN+ CF 0.47µF VC LOUT3 SEL2 2 LIN1 2 LIN2 LOUT2 SEL1 2 VCC LOUT3 UPSTREAM L_PORT VCC 2 LIN1 LOUT1 2 2 IN OUT SEL IN OUT SEL IN OUT SEL IN OUT SEL L_PORT n+2 L_PORT n+3 L_PORT n+6 L_PORT n+7 DISK DRIVE DISK DRIVE DISK DRIVE DISK DRIVE NOTE: ALL HIGH-SPEED INPUTS AND OUTPUTS (IN±, OUT±, LIN±, AND LOUT±) SHOULD BE CONNECTED USING CONTROLLED IMPEDANCE TRANSMISSION LINES. AC-COUPLING MAY ALSO BE REQUIRED. ALL CAPACITORS ARE 0.1µF UNLESS OTHERWISE INDICATED. ______________________________________________________________________________________ 11 MAX3752 Typical Operating Circuit 2.125Gbps, 3.3V Quad-Port Bypass with Repeater 48L, TQFP.EPS MAX3752 Package Information 12 ______________________________________________________________________________________ 2.125Gbps, 3.3V Quad-Port Bypass with Repeater Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 13 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX3752 Package Information (continued)