FAIRCHILD CCD595

PRELIMINARY DATA SHEET
CCD595
9216 x 9216 Pixel Image Area
Full Frame CCD Image Sensor
FEATURES
•
9216 x 9216 Full Frame CCD Array
•
8.75 µm x 8.75 µm Pixels
•
80.64mm x 80.64mm Image Area
•
100% Fill Factor
•
Non Multi-Pinned Phase (MPP) Operation
•
8 Outputs (4 on each side)
•
Readout Noise Less Than 30 e at 100MHz (25MHz x 4)
GENERAL DESCRIPTION
The CCD595 is a 9216 x 9216 active element solid state Charge
Coupled Device (CCD) Full Frame sensor. The CCD is intended for
advanced scientific, space, and aerial reconnaissance applications. The
CCD595 is organized as an array of 9216 horizontal by 9216 vertical
imaging elements. The pixel pitch is 8.75µm with a 100% fill factor.
Three-phase clocking is employed in the imaging area with two-phase
clocking in the serial readout registers. Image readout is performed via
4 serial registers containing 19 isolation rows between imaging and
readout sections. The imaging array can be clocked unidirectional (4output configuration) or bi-directional (8-output configuration). The
imaging area segments are split in mid-array for the latter configuration.
To maximize the exposure/readout cycle rate, concurrent array and
serial register clocking is utilized. Fast transfer clocking between the
array and serial registers is accomplished with strapped transfer gates
that load each line in less than five microseconds.
DEVICE ARCHITECTURE
The output circuit architecture features eight (four active, eight optional)
three-stage source follower readouts. The nominal read noise of the
output amplifiers is less than 25 electrons at 25MHz. The combined
data rates for 4 and 8 output configurations are 100MHz and 200MHz
respectively. Internal temperature and humidity sensors are also
located near the FPA for external monitoring.
PACKAGE INFORMATION
The top of the package has an optical window over the CCD active
area. The CCD595 is mounted in an environmentally sealed
enclosure containing the CCD array with thermoelectric coolers for
controlling the operating temperature of the array
Pinouts are provided on three sides for electrical connections (4output configuration). The package base serves as the heat sink
interface for thermal management. A mounting flange at the
package rim is used as a Z-axis reference datum for the
planarization of f the CCD focal plane with external optics.
ROBUST FLIGHT PACKAGE
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PRELIMINARY DATA SHEET
PIN NUMBER AND PIN NAME
P1-xx
P1-01
P1-02
P1-03
P1-04
P1-05
P1-06
P1-07
P1-08
P1-09
P1-10
P1-11
P1-12
P1-13
P1-14
P1-15
P1-16
P1-17
P1-18
P1-19
P1-20
P1-21
P1-22
P1-23
P1-24
P1-25
P1-26
P1-27
P1-28
P1-29
P1-30
P1-31
P1-32
P1-33
P1-34
P1-35
P1-36
P1-37
P1-38
P1-39
P1-40
P1-41
P1-42
P1-43
P1-44
P1-45
P1-46
P1-47
P1-48
P1-49
P1-50
P1-51
P1-52
P1-53
P1-54
P1-55
P1-56
PIN NAME
SUB
N.C.
H2_4B
H1_4B
SW4
RG4
SUB
OTG4
RD4
OD4
OS4
VSRC4
VGT4
SUB
N.C.
H2_3B
H1_3B
SW3
RG3
SUB
OTG3
RD3
OD3
OS3
VSRC3
VGT3
TEMP2P
TEMP2M
SUB
N.C.
H2_2B
H1_2B
SW2
RG2
SUB
OTG2
RD2
OD2
OS2
VSRC2
VGT2
HUM1
HUM2
SUB
N.C.
H2_1B
H1_1B
SW1
RG1
SUB
OTG1
RD1
OD1
OS1
VSRC1
VGT1
P2-xx
P2-01
P2-02
P2-03
P2-04
P2-05
P2-06
P2-07
P2-08
P2-09
P2-10
P2-11
P2-12
P2-13
P2-14
P2-15
P2-16
P2-17
P2-18
P2-19
P2-20
P2-21
P2-22
P2-23
P2-24
P2-25
P2-26
P2-27
P2-28
P2-29
P2-30
P2-31
P2-32
P2-33
P2-34
P2-35
P2-36
P2-37
P2-38
P2-39
P2-40
P2-41
P2-42
P2-43
P2-44
P2-45
P2-46
P2-47
P2-48
P2-49
P2-50
P2-51
P2-52
P2-53
P2-54
P2-55
P2-56
PIN NAME
TG3LB
TG2LB
TG1LB
A1L16
A2L16
A3L16
A1L15
A2L15
A3L15
A1L14
A2L14
A3L14
A1L13
A2L13
A3L13
A1L12
A2L12
A3L12
SUB
A1L11
A2L11
A3L11
A1L10
A2L10
A3L10
A1L9
A2L9
A3L9
A3L8
A2L8
A1L8
A3L7
A2L7
A1L7
A3L6
A2L6
A1L6
SUB
A3L5
A2L5
A1L5
A3L4
A2L4
A1L4
A3L3
A2L3
A1L3
A3L2
A2L2
A1L2
A3L1
A2L1
A1L1
BIAS2
BIAS1
TEMP1M
P3-xx
P3-01
P3-02
P3-03
P3-04
P3-05
P3-06
P3-07
P3-08
P3-09
P3-10
P3-11
P3-12
P3-13
P3-14
P3-15
P3-16
P3-17
P3-18
P3-19
P3-20
P3-21
P3-22
P3-23
P3-24
P3-25
P3-26
P3-27
P3-28
P3-29
P3-30
P3-31
P3-32
P3-33
P3-34
P3-35
P3-36
P3-37
P3-38
P3-39
P3-40
P3-41
P3-42
P3-43
P3-44
P3-45
P3-46
P3-47
P3-48
P3-49
P3-50
P3-51
P3-52
P3-53
P3-54
P3-55
P3-56
PIN NAME
TEMP1P
BIAS2
BIAS1
A1R1
A2R1
A3R1
A1R2
A2R2
A3R2
A1R3
A2R3
A3R3
A1R4
A2R4
A3R4
A1R5
A2R5
A3R5
SUB
A1R6
A2R6
A3R6
A1R7
A2R7
A3R7
A1R8
A2R8
A3R8
A3R9
A2R9
A1R9
A3R10
A2R10
A1R10
A3R11
A2R11
A1R11
SUB
A3R12
A2R12
A1R12
A3R13
A2R13
A1R13
A3R14
A2R14
A1R14
A3R15
A2R15
A1R15
A3R16
A2R16
A1R16
TG1RB
TG2RB
TG3RB
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PRELIMINARY DATA SHEET
Array Size
Pixel Size
Image Format
Number of Outputs
Pixel Output Rate
Number of Phases
Number of Prescan Pixels
Number of Overscan Lines
Total Number of Lines
Number of Phases
Pixel Rate per Output
SYMBOL
VDD
VRD
VOG
VSS
Vodc
Z
DEVICE ARCHITECTURE
9216 x 9216
Full Frame
8.75-um x 8.75-um
80.64 x 80.64
Mm
8 (4 Upper, 4 Lower)
Current Configuration Wired for 4 outputs
100MHz (25MHz per output)
3 + 3 (TG clocks)
3
Pixels/line
19
Top and Bottom
9216
2
Horizontal
25MHz
Typical
DC OPERATING CHARACTERISTICS
RANGE
MIN
NOM
MAX
DC Supply Voltage
18.0
20.0
23.0
Reset Drain Voltage
14.0
17.0
20.0
Output Gate Voltage
4.0
Substrate Ground
0.0
Output DC Level
VRD-5
VRD-4
Suggested Load Resistor
0.8
1.0
1.8
PARAMETER
TYPICAL CLOCK VOLTAGES
HIGH
LOW
SYMBOL
PARAMETER
VφH(1,2),
φSG
VφV (1,2,3)
VφR
VφVTG (2,3)
CφV(1,2,3)
Horizontal Transport Clock Voh Max-Min
Horizontal Transport Clock Voh Max-Min
Vertical Transport Clocks
Reset Gate Clock
Array Transfer Gate Clock
Vertical Array Gates
Cap. (per φV)
CφVTG2,3
Array Transfer Gate
Cap. (per pin)
A1
A2
A3
TG2
TG3
+7.5
+6
+8.0
+6.0
+8.0
47
86
109
200
200
-7.5
-2
-12.0
+1.0
-12.0
30
38
31
150
150
UNIT
V
V
V
V
K ohms
UNIT
REMARKS
V
V
V
V
V
nF
+4.5, -0.5 Typical
pF
65
PF
Horizontal Transfer Gate
S1
76
Cap. (per φ H)
S2
Note 1: φH = 400 pF, φV = 60,000 pF. All φH clock rise and fall times should be > 10 ns.
CφH (1,2)
REMARKS
+5, -11 V Typical
+2.0 +8.0 V Typical
+5, -11 Typical
Min @ +10V
Max @ -10V
Min @ +10V
Max @ -10V
Min @ +10V (per output)
Max @ -10V (per output)
PERFORMANCE SPECIFICATIONS
RANGE
UNIT
REMARKS
MIN
NOM
MAX
Vsat
Saturation Output Voltage
350
600
750
mV
Note 1
Qsat
Full Well Capacity (98% of Pixels)
70,000
eNote 1
SV
Output Amp Sensitivity
5
9
11
µV/eHsat
Horizontal Register Capacity
100,000
ePRNU
Photo Response Non-Uniformity, Peak-to-Peak
+10
%VSAT
Note 2
DSNU
Dark Signal Non-Uniformity (RMS)
5.0
mV
Note 3
2
DC
Average Dark Current
0.5
nA/cm
Note 3
QEA
0.35
%
Average Quantum Efficiency (550 – 800µm)
MTF
MTF at Nyquist
0.50
%
Note 4
Vcte
Vertical Transfer Efficiency
0.999995
Per Transfer (each phase) Note 2
Hcte
Horizontal Charge Transfer Efficiency
0.99995
Per Transfer (each phase) Note 2
NE
Total Read Noise Electrons
20
30
e-rms
Less Shot Noise Note 6
fMAXH
H Clock Frequency
25
MHz
PD
Power Dissipation On Chip
2.9
W
At 25MHz each register
Note 1: Minimum output voltage and/or well capacity is achieved operating in standard test condition mode and is the level above which saturation
non-linearity of 50% from best straight line fit occurs.
Note 2: Measured at approximately 50% Vsat.
Note 3: Value shown is for 15°C.
Note 4: Measured at the format center with 2854K tungsten source and Schott OG550 filter, 3mm thick.
Note 5: Standard test conditions are non-MPP clocks and DC operating voltages with 25MHz serial output rate/port.
Note 6: Measured in dark with correlated double sampling of amplifier output signal.
SYMBOL
PARAMETER
1801 McCarthy Blvd, Milpitas 95035 • 800-325-6975 • Fax 408-435-7352 • www.fairchildimaging.com • Rev A1 • 3 of 7
PRELIMINARY DATA SHEET
READOUT AMPLIFIER CONFIGURATION
The CCD595 readout structure is shown in the diagram below. Array to serial register transfer gates are not shown.
OUTPUT
8
7
1
2
6
3
5
4
OUTPUT
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PRELIMINARY DATA SHEET
SINGLE OUTPUT SECTION DIAGRAM
A single section of the CCD595 is shown below. The 20 taper rows include a single row of transfer gates nearest the serial readout register.
VGT
VSRC
TIMING
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PRELIMINARY DATA SHEET
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PRELIMINARY DATA SHEET
COSMETIC SPECIFICATIONS
Parameters
Grade 1
Grade 2
Grade 3
4
4
≥2
Output
Column Defects
≤ 10
≤ 50
≤ 250
Column
Maximum Defective Column Width
≤2
≤ 10
≤ 50
Column
Defective Column Separation
≥2
≥2
≥2
Column
100,000
200,000
400,000
Small
≤ 400
≤ 900
Medium
≤ 10
Number of Outputs
Single Pixels
Units
Notes
Pixel
Excluding defective columns & clusters
≥ 900
Cluster
Excluding defective columns & single pixels
≤ 50
≤ 250
Cluster
Excluding defective columns & single pixels
0
≤2
≤ 10
Cluster
Excluding defective columns & single pixels
≥2
≥2
≥2
Rows/Columns
Cluster Defects
Large
Cluster Defect Separation
Test Conditions:
Device temperature 25°C
Readout mode 1 x 1
Data Rate 25Mhz per output
Definitions:
Single Pixels
Column Defects
Defective Column Width
Cluster Defects
Small
Medium
Large
Excluded Regions
Pixels which photoresponse deviates more than + 10% of the minimum vertical pixel
well at 50% of Vsat
More than 25 contiguous blemished pixels in a column
Number of adjacent defective columns
A grouping of 2 to 11 adjacent point defects
A grouping of 12 to 25 adjacent point defects
A grouping of 26 to 1000 adjacent point defetcs
The outer 5 rows and columns are excluded
WARRANTY
Within twelve months of delivery to the end customer, Fairchild
Imaging will repair or replace, at our option, any Fairchild Imaging
camera product if any part is found to be defective in materials or
workmanship. Contact Customer Service for assignment of warranty
return number and shipping instructions to ensure prompt repair or
replacement.
This product is designed, manufactured and distributed utilizing the
ISO 9000:2000 Business Management System.
CERTIFICATION
Fairchild Imaging certifies that all products are carefully inspected and
tested at the factory prior to shipment and will meet all requirements of
the specifications under which it is furnished.
Fairchild Imaging, Inc., 1801 McCarthy Blvd.,
Milpitas, CA 95035 (800) 325-6975, (408) 433-2500

2001 Fairchild Imaging reserves the right to make changes to its
products and/or their specifications at any time without notice. Printed
in the U.S.A.
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