ETC CCD4156

CCD4156
512 x 512 Element
Interline High Frame Rate Sensor
FEATURES
512 x 512 Photosite Array
• 17µ
µm x 17µ
µm Pixel Size
• 8.70 mm x 8.70 mm Active Image Area
• 512 x 512 Optically Active Pixels
• 19 % Fill Factor
• Over 1000 FPS Capable
• Anti-blooming to 1000X
• Electronic Shuttering VOD Design
• Two Phase Buried Channel NMOS
• Optional Color Operation Configurable
•
GENERAL DESCRIPTION
The CCD4156 is a 512 x 512 element solid state
Charge Coupled Device (CCD) Interline image sensor
which is intended for use in high frame rate scientific,
industrial, and commercial electro-optical systems.
The CCD4156 is organized as a matrix of 32
separate segments of 32 horizontal by 256 vertical
CCD photosites. The pixel pitch and spacing is 17µm.
The imaging array is operated with vertically strapped
phases (one tri-level) which clock charge towards
upper and lower serial readout registers. Serial
register clocks operate from 0 to 5 volt clock levels to
simplify high speed readout schemes. Both vertical
and horizontal channels operate in Buried Channel
mode. A Summing Gate is provided in each of the 8
output sections for pixel binning if required. The
Buried Channel operation offers excellent charge
transfer efficiencies even at high readout speeds. An
additional implant under each vertical and horizontal
phase creates a barrier which allows electrons to be
stored under the other non-barrier phases. Dark
2
current is approximately 1 nA/cm @ 20°C. Excellent
antiblooming performance is achieved by use of a
vertical overflow drain (VOD) CCD structure. A three
stage low noise output amplifier with an output
conversion gain of 2.5µV/e is utilized in each of the 32
separate outputs. Device processing is done using
ccd4156_512x512.doc
1.0 micron design rules. The double metal, two-poly
process allows a photosite layout with small pixel
geometry and minimal array blemishes.
FUNCTIONAL DESCRIPTION
The CCD4156 consists of the following functional
elements illustrated in the block diagram.
Image Sensing Elements: Incident photons pass
through a transparent oxide layer over each
photodiode pixel gate structure creating electron hole
pairs. The resulting photo-electrons are collected in
the photosites during the integration period. The
amount of charge accumulated in each photosite is a
linear function of the localized incident illumination
intensity and integration period.
The photosite structure is made up of individual
photodiode elements coupled to adjacent vertical
interline storage areas. These shielded storage areas
are also used to shift image data vertically.
Consequently, the device does not need to be
shuttered during readout of each sequential frame.
1
Vertical Charge Shifting: The Interline architecture
of the CCD4156 provides video information as a
parallel sequential readout of 256 lines, each
containing 32 photosite elements. At the end of an
integration period the ΦV1 phase is tri-level clocked
followed by conventional ΦV1 and ΦV2 clocks to
transfer charge vertically through the CCD interline
array to the horizontal readout register. Vertical
columns are separated by channel stop regions to
prevent charge migration.
The imaging area is divided into 32 segments (16upper and 16-lower). Each segment is simultaneously
clocked to provide 32 output parallel pixel information.
The last clocked gate in the Horizontal registers
(ΦSW) is larger than the others and can be used to
horizontally bin charge. This gate can be clocked
independently or tied to ΦH1 for binned or normal full
resolution pixel information. The output video is
available following the high to low transition of ΦSW.
Output Amplifier: The CCD4156 has 32 separate
output amplifiers. They are three-stage FET
amplifiers with a reset MOSFET tied to the input gate.
Charge packets are clocked to a precharged (sense
node) capacitor whose potential changes linearly in
response to the number of electrons delivered. This
potential is applied to the input gate of an NMOS
amplifier producing a signal at the Output VOUT pin.
The capacitor is reset with ΦR to a precharge level
prior to the arrival of the next charge packet except
when horizontally binning. It is reset by use of the
reset MOSFET. The first two output amplifier drains
are tied to VDD and the output MOSFET drain (OD)
can be tied to VDD or a slightly less positive DC
potential. The output sources (OSn) are connected to
external load resistors to ground. The OS sources
constitute the 32 individual video outputs from the
device.
DEFINITION OF TERMS
Vertical Transport Clocks φV1, φV2 -The clock
signals applied to the vertical transport register. Trilevel V1 and two level V2 Vertical clocks are common
to all image area groups. This minimizes
requirements for external clocking electronics. Color
applications utilize the same readout structure with
individual R-G-B dye matrix structures over the
photosites.
Horizontal Transport Clocks φH1, φH2,-The clock
signals applied to the horizontal transport registers.
Reset Clock φR -The clock applied to the reset
switch of the output amplifiers.
Dynamic Range -The ratio of saturation output
voltage to RMS noise in the dark. The peak-to-peak
random noise is 4-6 times the RMS noise output.
Saturation Exposure -The minimum exposure level
that produces an output signal corresponding to the
maximum photosite charge capacity. Exposure is
equal to the product of light intensity and integration
time.
Responsivity -The output signal voltage per unit of
exposure.
Spectral Response Range -The spectral band over
which the response per unit of radiant power is more
than 10% of the peak response.
Photo-Response Non-Uniformity -The difference of
the response levels between the most and the least
sensitive regions under uniform illumination
(excluding blemished elements) expressed as a
percentage of the average response.
Dark Signal -The output signal in the dark caused by
thermally generated electrons. Dark signal is a linear
function of integration time and an exponential
function of chip temperature.
Pixel - Picture element or sensor element also called
photoelement , photodiode, or photosite.
Charge-Coupled Device-A charge-coupled device is
a monolithic silicon structure in which discrete
packets of electron charge are transported from
position to position by sequential clocking of an array
of gates.
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4156 Timing Diagram
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CCD4156 PACKAGE PIN ASSIGNMENTS
ccd4156_512x512.doc
Pin #
Name
(See Package Pin Diagram)
Pin #
Name
1
OD
31
OD
2
VDD1
32
N.C.
3
VSRC
33
N.C.
4
VLOAD
34
OS1
5
OTG
35
OS2
6
RD
36
PWELL
7
PWELL
37
OS3
8
RG
38
OS4
9
H2
39
PWELL
10
PWELL
40
OS5
11
H1
41
PWELL
12
SW
42
OS6
13
V1
43
OS7
14
LS
44
PWELL
15
N.C.
45
OS8
16
N.C.
46
OS9
17
LS
47
PWELL
18
V2
48
N.C.
19
SW
49
OS10
20
H1
50
OS11
21
PWELL
51
PWELL
22
H2
52
OS12
23
RG
53
PWELL
24
PWELL
54
OS13
25
RD
55
OS14
26
OTG
56
PWELL
27
VLOAD
57
N.C.
28
VSRC
58
OS15
29
VDD1
59
OS16
30
NSUB
60
NSUB
4
CCD4156 PACKAGE PIN ASSIGNMENTS
ccd4156_512x512.doc
Pin #
Name
(See Package Pin Diagram)
Pin #
Name
61
OD
91
OD
62
VDD1
92
N.C.
63
VSRC
93
PWELL
64
VLOAD
94
OS32
65
OTG
95
OS31
66
RD
96
PWELL
67
PWELL
97
OS30
68
RG
98
OS29
69
H2
99
PWELL
70
PWELL
100
OS28
71
H1
101
PWELL
72
SW
102
OS27
73
V2
103
OS26
74
LS
104
PWELL
75
N.C.
105
OS25
76
N.C.
106
OS24
77
LS
107
PWELL
78
V1
108
N.C.
79
SW
109
OS23
80
H1
110
OS22
81
PWELL
111
PWELL
82
H2
112
OS21
83
RG
113
PWELL
84
PWELL
114
OS20
85
RD
115
OS19
86
OTG
116
PWELL
87
VLOAD
117
N.C.
88
VSRC
118
OS18
89
VDD1
119
OS17
90
NSUB
120
NSUB
5
CCD 4156 IMAGE SEGMENT ARRANGNMENT
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CCD 4156 IMAGE SEGMENT ARRANGNMENT
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CCD 4156 WIRE BONDING DIAGRAM
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CCD 4156 PGA PIN NUMBERING DIAGRAM (BACKSIDE VIEW)
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CCD 4156 PGA PIN NAME MATRIX
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PERFORMANCE CHARACTERISTICS: TP = 20 º C (Notes 1 & 2)
SYMBOL
RANGE
PARAMETER
MIN
DSAVE
IDARK
DSNU
QSat
VSat
PRNU
CTE (V)
CTE (H)
R
SSF
Dark Signal, (Readout)
Dark Current Density (Integration)
Dark Signal Non-Uniformity
Full Well Capacity
Saturation Voltage
Photoresponse Nonuniformity
Charge Transfer Efficiency,
Vertical
Charge Transfer Efficiency,
Horizontal
Responsivity
Sensitivity (Scale Factor)
80
180
TYPICAL
TBD
1.0
TBD
110
250
UNIT
CONDITION
mV
nA/cm2
mV
KemV
% of Vsat
Note 3
Note 3
Note 4
MAX
2.0
TBD
400
10
.9999
.99995
Per Phase
Transfer
.9999
.99995
Per Phase
Transfer
V/µJ/cm2
2.0
TBD
2.5
RANGE
UNIT
Note 5
µV/e-
DC CHARACTERISTICS: TP = 20 º C (Note 1)
SYMBOL
VDD1
VDD2
VRD
VLOAD
VPW
VSRC
PARAMETER
DC Supply Voltage
Output Drain Supply Voltage
Reset Drain Voltage
Output Load Gate Voltage
P-Well Ground
Output Amplifier Return
MIN
14.7
12.5
13
0
0
0
TYPICAL
15
15
13.5
1.6
0
1.4
MAX
16
16
14
3.0
0
2.0
CONDITION
Volts
Volts
Volts
Volts
Volts
Volts
CLOCK CHARACTERISTICS: TP = 20 º C (Note 1)
SYMBOL
VφH (1, 2 ) HIGH
VφH (1, 2) LOW
VφSW HIGH
VφSW
LOW
VφV(1, 2 ) HIGH
VφV(1, 2) LOW
VφRG HIGH
VφRG LOW
VφV1-TRI HIGH
ccd4156_512x512.doc
RANGE
PARAMETER
Horizontal Transport Clock
Horizontal Transport Clock
Summing Gate Clock
Summing Gate Clock
Vertical Transport Clocks
Vertical Transport Clocks
Reset Gate Clock
Reset Gate Clock
Vertical Tri-Level Clock
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
MIN
+ 4.5
- 0.2
+ 4.5
- 0.2
- 1.0
- 10
+6
+ 0.5
+ 9.0
TYPICAL
+ 5.5
0.0
+ 5.5
0.0
+ 0.0
-9
+7
+2
+ 11.0
UNIT
MAX
+ 6.5
+ 0.5
+ 6.5
+ 0.5
+ 1.0
-8
+8
+ 2.5
+ 17.0
CONDITION
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
11
AC CHARACTERISTICS: TP = 20 º C (Note 1)
SYMBOL
VODC
Ro
f MAX HORIZ.
PD
RANGE
PARAMETER
Output DC Level
Output load Resistor
Horizontal Clock Frequency
On-Chip Power Dissipation
MIN
7.5
0.7
TYPICAL
9.0
1.0
20
2.50
MAX
10
1.5
50
UNIT
CONDITION
Volts
KΩ
MHz
W
Note 6
Note 7
NOTES
1.- TP is defined as the package temperature.
2.- Standard test conditions are nominal clocks and DC operation voltages. 5.0 MHz horizontal data
rate, integration time = 20.0 msec. Values shown are for 20 °C, unless otherwise indicated.
3.- Dark Current doubles every 5-7 ºC.
4.- Excluding spikes.
5.- Excluding spikes, and measured @ ½Vsat
6.- For the cases of VRD = MIN, TYPICAL, MAX and Ro = 1 kΩ
7.- At f MAX HORIZ = 40 MHz, 32 On-Chip amplifier outputs, vertical & horizontal registers.
8.- Device has 32 On-Chip amplifiers.
WARRANTY
Within twelve months of delivery to the end
customer, Fairchild Imaging will repair or replace,
at our option, any Fairchild Imaging product if any
part is found to be defective in materials or
workmanship. Contact Customer Service for
assignment of warranty return number and shipping
instructions to ensure prompt repair or replacement.
CERTIFICATION
Fairchild Imaging certifies that all products are
carefully inspected and tested at the factory prior to
shipment and will meet all requirements of the
specifications under which it is furnished.
Fairchild Imaging
1801 McCarthy Blvd., Milpitas, CA 95035
(800) 325-6975 or (408) 433-2500
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