Rev 0; 9/06 I2C Programmable-Gain Amplifier for Audio Applications Features The DS4420 is a fully differential, programmable-gain amplifier for audio applications. It features a -35dB to +25dB gain range controlled by an I2C interface and it is optimized to drive loads as low as 50Ω. The gain is adjustable in 3dB increments across the entire range. Three address inputs, used to select the I 2 C slave address, enable up to eight devices on a common bus. Differential Inputs and Outputs -35dB to +25dB Adjustable Gain Low Output Noise Low-Distortion Driving into a 50Ω Load 3dB Gain Steps Programmed through I2C Interface The product operates from a single 5V supply over a -20°C to +70°C temperature range. It is offered in a 3mm x 3mm TDFN package. 5V Single Supply 20kHz Bandwidth for All Gain Settings Small 3mm x 3mm x 0.8mm TDFN Package Applications Up to Eight DS4420s can be Placed on the Same I2C Bus Telephone Headsets Audio Volume Control Microphone Gain Control Ordering Information Pin Configuration TOP VIEW 1 + A2 14 AVCC A1 2 13 OUT+ A0 3 12 OUT- SCL 4 11 AGND N.C. DS4420 SDA 5 10 VCC 6 9 IN- GND 7 8 IN+ PART TEMP RANGE PIN-PACKAGE DS4420+ -20°C to +70°C 14 TDFN-EP* +Denotes lead-free package. *EP = Exposed paddle. TDFN (3mm x 3mm x 0.8mm) Typical Operating Circuit VCC MICROPR0CESSORCONTROLLED GAIN GND AGND AVCC SDA SCL A2 A1 I2C INTERFACE A0 OUT+ IN+ AUDIO SOURCE -35dB TO +25dB GAIN IN- AUDIO AMPLIFIER OUT- DS4420 ______________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS4420 General Description DS4420 I2C Programmable-Gain Amplifier for Audio Applications ABSOLUTE MAXIMUM RATINGS Voltage on VCC, SDA, and SCL Relative to GND.................................................-0.5V to +6.0V Voltage on A0, A1, and A2 Relative to GND ......................................-0.5V to (VCC + 0.5V; not to exceed 6.0V) Voltage on IN+, IN-, OUT-, and OUT+ Relative to AGND .................................-0.5V to (AVCC + 0.5V; not to exceed 6.0V) Voltage on AVCC Relative to VCC ..........................-0.3V to +0.3V Voltage on AGND Relative to GND .......................-0.3V to +0.3V Output Current ..................................................................150mA Operating Temperature Range ...........................-20°C to +70°C Storage Temperature .....................See J-STD-020 Specification Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (TA = -20°C to +70°C.) PARAMETER SYMBOL Digital Supply Voltage VCC Analog Supply Voltage AVCC Analog Ground AGND CONDITIONS (Note 1) MIN TYP +4.5 MAX UNITS +5.5 V VCC (See Figure 5) V GND V Input Logic 1 (SCL, SDA, A0, A1, A2) VIH 2.0 VCC + 0.3 Input Logic 0 (SCL, SDA, A0, A1, A2) VIL -0.3 +0.8 V TYP MAX UNITS 1.7 3 mA V ELECTRICAL CHARACTERISTICS (VCC = +4.5V to +5.5V, TA = -20°C to +70°C, unless otherwise noted.) PARAMETER Supply Current Standby Current SYMBOL CONDITIONS ICC VCC = 5.5V, RL = ∞, VIN = 0V differential (Note 9) ISTBY Input Leakage (SDA, SCL, A2, A1, A0) IIL Output Leakage (SDA) IL Output-Current Low (SDA) Input Voltage Range Max Peak-to-Peak Input Level Input Resistance Input Common-Mode Voltage Output Voltage IOL VOL = 0.4V 3 VOL = 0.6V 6 Differential Differential Differential, active mode (Note 3) VO Output Common-Mode Voltage VO:CM Output Offset Voltage VO:OS IOS1 -19 29 49 RL = 50Ω differential Differential 0.45 x VCC AV = +25dB -20 VOUT = GND 95 VOUT = VCC - 0.75V 64 _____________________________________________________________________ 140 µA 1 µA 1 µA mA 0.45 x VCC VIN:CM VOP-P 2 VCC = 5.5V VIN Output Peak-to-Peak Signal Swing Amplifier Output Current (Sourcing) VCC = 5.5V (Notes 2, 9) VINP-P RIN MIN 0.5 x VCC +1 dBV 3.2 V 60 kΩ 0.55 x VCC V 6 dBV 5.6 V 0.55 x VCC V +20 mV mA I2C Programmable-Gain Amplifier for Audio Applications (VCC = +4.5V to +5.5V, TA = -20°C to +70°C, unless otherwise noted.) PARAMETER Amplifier Output Current (Sinking) SYMBOL IOS2 CONDITIONS VOUT = VCC 89 VOUT = 0.75V 64 50 Resistive Load Range RL Differential Capacitive Load CL Cap to GND (Note 4) Closed-Loop Bandwidth Passband Flatness Output Noise (Note 5) Total Harmonic Distortion (Note 5) NO MIN All gain settings (Note 5) 20 20Hz to 20kHz (Notes 2, 5) -1 TYP MAX UNITS mA A = -35dB, 300Hz to 3.4kHz -123 A = +25dB, 300Hz to 3.4kHz -88 RL = 50Ω, VO ≤ +6dBV, f = 1kHz, A = ±16dB 0.03 RL = 1kΩ, VO ≤ +6dBV, f = 1kHz, A = ±16dB 0.01 50k Ω 100 pF 20k Hz +1 dB dBV 1.0 % THD Gain Range A -35 Gain Step Size AS 2.0 3.0 dB 4.0 dB Gain Accuracy AERR1 (Note 10) +2.5 dB Mute and Standby Mode Gain AMUTE (Note 5) -90 dB tPU (Note 6) 10 µs MAX UNITS 400 kHz Standby Mode Exit Time -2.5 +25 I2C AC ELECTRICAL CHARACTERISTICS (See Figure 3) (VCC = +4.5V to +5.5V, TA = -20°C to +70°C, timing referenced to VIL(MAX) and VIH(MIN), unless otherwise noted.) PARAMETER SYMBOL CONDITIONS Bus Free Time Between STOP and START Conditions tBUF 1.3 µs tHD:STA 0.6 µs tLOW 1.3 µs Low Period of SCL High Period of SCL 0 TYP fSCL Hold Time (Repeated) START Condition (Note 7) MIN SCL Clock Frequency tHIGH 0.6 Data Hold Time tHD:DAT 0 Data Setup Time tSU:DAT 100 ns Start Setup Time tSU:STA 0.6 µs SDA and SCL Rise Time tR (Note 8) 20 + 0.1CB 300 ns SDA and SCL Fall Time tF (Note 8) 20 + 0.1CB 300 ns STOP Setup Time SDA and SCL Capacitive Loading tSU:STO CB µs 0.9 0.6 (Note 8) µs µs 400 pF _____________________________________________________________________ 3 DS4420 ELECTRICAL CHARACTERISTICS (continued) Note 1: All voltages are referenced to ground. Currents entering the IC are specified positive, and currents exiting the IC are negative. Note 2: Standby supply current specified with SDA = SCL = VCC, the output disconnected, and A0, A1, and A2 driven to within 100mV of VCC or GND. Note 3: Input resistance during mute and power-down is approximately one-half of the active-mode resistance. Note 4: Each output is capable of driving a 100nF capacitive load to ground using an external 10Ω series resistor. However, output capacitance should be minimal for optimal distortion performance. Note 5: Guaranteed by design. Note 6: This is the time it takes for the output to become active after exiting standby mode. Note 7: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standardmode timing. Note 8: CB = total capacitance of one bus line in picofarads. Note 9: The current specified is the sum of VCC and AVCC supply currents. Note 10: Gain accuracy specified assuming the output impedance of signal source driving of the DS4420 is ≤ 2.5kΩ. Typical Operating Characteristics (TA = +25°C, VCC = AVCC = 5.0V, unless otherwise noted.) 78 76 74 -20°C 1.7 VCC = AVCC = SDA = SCL NO LOAD IN+ AND IN- SHORTED +25°C TOGETHER 1.5 +70°C 1.6 1.4 1.2 1.0 0.8 0.6 0.4 72 IN+ AND IN- SHORTED TOGETHER NO LOAD 0.2 70 0 1.4 4.50 4 1.8 -20°C 1.6 DS4420 toc03 +25°C SUPPLY CURRENT vs. GAIN SETTING 2.0 SUPPLY CURRENT (mA) 80 VCC = AVCC = SDA = SCL NO LOAD +70°C IN+ AND IN- SHORTED TOGETHER SUPPLY CURRENT (mA) 82 1.8 DS4420 toc01 84 SUPPLY CURRENT vs. SUPPLY VOLTAGE (SETTING AT -11dB) DS4420 toc02 SUPPLY CURRENT vs. SUPPLY VOLTAGE (STANDBY MODE ENABLED) SUPPLY CURRENT (μA) DS4420 I2C Programmable-Gain Amplifier for Audio Applications 4.75 5.00 5.25 SUPPLY VOLTAGE (V) 5.50 4.50 4.75 5.00 5.25 5.50 SUPPLY VOLTAGE (V) _____________________________________________________________________ 0 5 10 GAIN SETTING 15 20 I2C Programmable-Gain Amplifier for Audio Applications COMMON-MODE FREQUENCY RESPONSE SWEEP AT -11dB 20kHz 50Ω LOAD 10 -30 GAIN (dB) 60 -40 20 0 15 10,000 1000 100,000 100,000 FREQUENCY (Hz) GAIN vs. SETTING CCITT NOISE vs. GAIN SETTING TOTAL HARMONIC DISTORTION vs. FREQUENCY 0.018 DS4420 toc08 0 NO LOAD -20 WITH 50Ω LOAD AND 1kΩ LOAD 1VRMS INPUT -11dB SETTING 0.016 0.014 -10 -20 -40 0.012 THD+N (%) 0 1,000,000 DS4420 toc09 FREQUENCY (Hz) CCITT NOISE (dBV) 10 10,000 GAIN SETTING IN+ AND IN- SHORTED TOGETHER ACROSS -20°C TO +70°C WITH 50Ω LOAD, 1kΩ LOAD, AND NO LOAD 20 -35dB SETTING -40 1000 20 DS4420 toc07 30 -60 -80 0.010 0.008 0.006 -100 0.004 -120 -40 -140 10 GAIN SETTING 15 0.000 0 20 5 10 GAIN SETTING TOTAL HARMONIC DISTORTION vs. FREQUENCY 0.09 WITH 50Ω LOAD AND 1kΩ LOAD 1VRMS INPUT +10dB SETTING 0.08 0.07 15 10 20 100 5 0 0.06 0.05 0.04 0.03 0.02 DS4420 toc11 50Ω LOAD 1kHz 2VRMS INPUT VOUT 0.01 FREQUENCY (Hz) 10,000 100,000 0.018 0.014 -10 0.012 -15 0.010 -20 0.008 -25 0.006 0.004 THD+N -40 0.00 1000 100,000 0.016 -35 100 10,000 0.020 -5 -30 10 1000 FREQUENCY (Hz) TOTAL HARMONIC DISTORTION vs. VOUT 10 VOUT (dB) 5 DS4420 toc10 0 0.002 THD+N (%) -30 THD+N (%) GAIN (dB) -30 -80 10 -2dB SETTING -10 -20 -70 5 0 -50 -60 0 50Ω LOAD +25dB SETTING 20 -20 CMRR (dB) PSRR (dB) NO LOAD -10 80 40 GAIN vs. FREQUENCY RESPONSE 30 DS4420 toc05 1kHz 50Ω LOAD 100 0 DS4420 toc04 120 DS4420 toc06 POWER-SUPPLY REJECTION RATIO vs. GAIN SETTING 0.002 0.000 2 4 6 8 10 12 14 16 18 20 GAIN SETTING _____________________________________________________________________ 5 DS4420 Typical Operating Characteristics (continued) (TA = +25°C, VCC = AVCC = 5.0V, unless otherwise noted.) I2C Programmable-Gain Amplifier for Audio Applications DS4420 Pin Description PIN NAME 1 A2 2 A1 FUNCTION Address Select Inputs—Determine I2C Slave Address. Device address is 1010A2A1A0. 3 A0 4 SCL I2C Serial Clock—Input for I2C Clock 5 SDA I2C Serial Data—Input/Output for I2C Data 6 VCC Digital Power-Supply Terminal 7 GND Ground 8 IN+ 9 IN- 10 N.C. 11 AGND 12 OUT- 13 OUT+ 14 AVCC EP EP Differential Audio Input Signal No Connection Analog Ground (Must be Connected to GND) Differential Audio Output Signal Analog Power Supply (Must be Connected to VCC) Exposed Paddle. Connect to GND and AGND. Detailed Description Block Diagram The key features of the DS4420 are illustrated in the Block Diagram. A0 A1 A2 VCC AVCC Controlling the DS4420 The DS4420 is controlled through the I2C serial interface. Gain, mute, and standby settings all reside in one control register located at memory address F8h (see Figure 1). Writes to other memory addresses are invalid. Programmable Gain The gain is adjustable from -35dB to +25dB in 3dB increments. The gain is determined by the five LSBs of the control register as shown in Figure 1. Gain settings greater than 14h are invalid. Mute Mode The DS4420 is placed in mute mode by setting the mute bit located in the control register (see Figure 1). When in this mode, the output of the amplifier is muted and is independent of the gain setting. The input-to-output attenuation is specified in the Electrical Characteristics table as AMUTE. Standby Mode Standby mode is entered by setting the standby control bit (see Figure 1). Setting the standby control bit mutes the output of the amplifier and places the DS4420 into a 6 SDA I2C INTERFACE SCL IN+ DS4420 3dB GAIN STEPS -35dB TO +25dB GAIN IN- GND OUT+ OUT- AGND low-current (I STBY ) consumption state. Unlike mute mode, however, standby mode is intended for use when no input signal is present. While in standby mode, the DS4420 maintains input and output common-mode bias voltages. The device produces no audible clicks or pops when entering or exiting the standby state. The time required for the output to become active when exiting standby mode is specified as tPU. _____________________________________________________________________ I2C Programmable-Gain Amplifier for Audio Applications DS4420 Control Register (F8h) Power-Up Default: F8h 1000 0000 b Standby x Mute Gain Setting[4:0] bit 7 bit 4 bit 3 bit 2 bit 7 Standby: Places the DS4420 in standby mode. 0 = Normal operation. 1 = Places the DS4420 in standby mode. (Power-up default.) bit 6 Don’t care. bit 5 bit 4:0 bit 1 bit 0 Mute: Mutes the amplifier output, regardless of the current gain setting. 0 = Normal operation. (Power-up default.) 1 = Mutes the amplifier output. Gain Setting: Five-bit gain setting. The power-up default is setting 00h. GAIN SETTING (hex) GAIN (dB) GAIN SETTING (hex) 00h -35 0Bh -2 01h -32 0Ch +1 02h -29 0Dh +4 03h -26 0Eh +7 04h -23 0Fh +10 05h -20 10h +13 06h -17 11h +16 07h -14 12h +19 08h -11 13h +22 09h -8 14h +25 0Ah -5 15h to 1Fh Illegal GAIN (dB) Figure 1. Control Register Description Slave Address Byte and Address Pins The slave address byte consists of a 7-bit slave address plus a R/W bit (see Figure 2). The DS4420’s slave address is determined by the state of the A0, A1, and A2 address pins. These pins allow up to eight DS4420s to reside on the same I2C bus. Address pins connected to GND result in a ‘0’ in the corresponding bit position in the slave address. Conversely, address pins connected to VCC result in a ‘1’ in the corresponding bit positions. For example, the DS4420’s slave address byte is A0h when A0, A1, and A2 pins are grounded. I2C communication is described in detail in the I2C Serial Interface Description section. MSB 1 LSB 0 1 0 A2 SLAVE ADDRESS* A1 A0 R/W READ/WRITE BIT *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1, AND A2. Figure 2. DS4420 Slave Address Byte _____________________________________________________________________ 7 DS4420 I2C Programmable-Gain Amplifier for Audio Applications SDA tBUF tHD:STA tLOW tR tSP tF SCL tHD:STA STOP tSU:STA tHIGH tSU:DAT START REPEATED START tSU:STO tHD:DAT NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN). Figure 3. I2C Timing Diagram I2C Serial Interface Description I2C Definitions The following terminology is commonly used to describe I2C data transfers. See the timing diagram (Figure 3) and the I2C AC Electrical Characteristics table for additional information. Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses, start and stop conditions. Slave Devices: Slave devices send and receive data at the master’s request. Bus Idle or Not Busy: Time between stop and start conditions when both SDA and SCL are inactive and in their logic-high states. Start Condition: A start condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a start condition. Stop Condition: A stop condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a stop condition. Repeated Start Condition: The master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated start condition is issued identically to a normal start condition. 8 Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements. Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one (done by releasing SDA) during the 9th bit. Timing (Figure 3) for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition. _____________________________________________________________________ I2C Programmable-Gain Amplifier for Audio Applications I2C Communication Writing a Single Byte to a Slave: The master must generate a start condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a stop condition. The master must read the slave’s acknowledgement during all byte write operations. Reading a Single Byte from a Slave: Unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. A dummy write cycle can be used to force the address pointer to a desired location. To do this, the master generates a start condition, writes the slave address byte (R/W =0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (R/W = 1), reads the data byte with a NACK to indicate the end of the transfer, and generates a stop condition. See Figure 4 for I2C communication examples. The DS4420’s slave address is determined by the state of the A0, A1, and A2 address pins as shown in Figure 2. Address pins connected to GND result in a ‘0’ in the corresponding bit position in the slave address. Conversely, address pins connected to VCC result in a ‘1’ in the corresponding bit positions. When the R/W bit is 0 (such as in A0h), the master is indicating it will write data to the slave. If R/W is set to a 1, (A1h in this case), the master is indicating it wants to read from the slave. Applications Information Power-Supply Decoupling If an incorrect (nonmatching) slave address is written, the DS4420 will assume the master is communicating with another I2C device and ignore the communication until the next start condition is sent. Memory Address: During an I2C write operation to the DS4420, the master must transmit a memory address to identify the memory location where the slave is to store The DS4420 has separate supply voltages for its analog and digital circuitry. For best noise and distortion performance, place a 0.1µF or 0.01µF capacitor from VCC to GND and from AVCC to AGND. These capacitors should be placed as close as possible to the supply and ground pins of the device. COMMUNICATIONS KEY S START A ACK WHITE BOXES INDICATE THE MASTER IS CONTROLLING SDA P STOP N NOT ACK SHADED BOXES INDICATE THE SLAVE IS CONTROLLING SDA Sr REPEATED START NOTE 1: ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST. X X X X X X X X WRITE THE GAIN SETTING S 1 0 1 0 A2 A1 A0 0 1 0 1 0 A2 A1 A0 0 8-BITS ADDRESS OR DATA F8h A 1 1 1 1 1 A 1 1 1 1 1 READ THE GAIN SETTING S NOTE 2: THE FIRST BYTE SENT AFTER A START CONDITION IS ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE READ/WRITE BIT. 0 0 0 A 0 0 0 A REGISTER SETTING A P F8h Sr 1 0 1 0 A 2 A1 A0 1 A REGISTER SETTING N P Figure 4. I2C Communication Examples _____________________________________________________________________ 9 DS4420 the data. The memory address is always the second byte transmitted during a write operation following the slave address byte. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave will return control of SDA to the master. Slave Address Byte: Each slave on the I 2 C bus responds to a slave address byte sent immediately following a start condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. DS4420 I2C Programmable-Gain Amplifier for Audio Applications Exposed Paddle Internal Ground Connections The DS4420 exposed paddle is not electrically isolated. It must be soldered to ground for proper operation. The DS4420’s ground pins, GND and AGND, must be connected together externally. Internally, they are connected as shown in Figure 5. Input-Coupling Capacitors The DS4420 is designed to be operated with an ACcoupled input signal. The input resistance, RIN, is sufficiently large to allow the use of small and inexpensive external capacitors. The input resistance combined with the AC-coupling capacitor will create a highpass filter. The -3dB cutoff frequency of the highpass, fC, is given by: fC = 13Ω TYPICAL 1 2π × CIN × RIN where CIN is the external coupling capacitor and RIN is the internal input resistance. At the cutoff frequency, the input signal will be attenuated 3dB, with less attenuation as the signal’s frequency increases beyond the cutoff frequency. To guarantee passband flatness, the cutoff frequency of the filter should be designed using the specified minimum input resistance, and placed well below the desired flat band of the circuit. The typical input resistance should only be used to estimate typical performance. GND AGND Figure 5. Internal Ground Connections Chip Topology TRANSISTOR COUNT: 5347 SUBSTRATE CONNECTED TO: Ground Package Information For the latest package outline information, go to www.maximic.com/DallasPackInfo. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Dallas Semiconductor Corporation. Springer