RENESAS M6MGD13TW66CWG-P

Renesas LSIs
Preliminary
Notice: This is not a final specification.
Some parametric limits are subject to change.
M6MGD13TW66CWG-P
134,217,728-BIT (8,388,608-WORD BY 16-BIT) CMOS FLASH MEMORY &
67,108,864-BIT (4,194,304-WORD BY 16-BIT) CMOS MOBILE RAM
Stacked-CSP ( Chip Scale Package)
Description
The M6MGD13TW66CWG-P is a Stacked Chip Scale
Package (S-CSP) that contents 128M-bit Flash memory and
64M-bit Mobile RAM in a 72-pin Stacked CSP with leaded
solder ball.
128M-bit Flash memory is a 8,388,608 words, single power
supply and high performance non-volatile memory fabricated
by CMOS technology for the peripheral circuit and DINOR IV
(Divided bit-line NOR IV) architecture for the memory cell. All
memory blocks are locked and can not be programmed or
erased, when F-WP# is Low. Using Software Lock Release
function, program or erase operation can be executed.
The M6MGD13TW66CWG-P is suitable for a high
performance cellular phone and a mobile PC that are
required to be small mounting area, weight and small power
dissipation.
Features
Access Time
Random Access/ Page Access
Flash
70ns /25ns (Max.)
Mobile RAM
85ns /25ns (Max.)
Supply Voltage
FM-VCC=2.7 ~ 3.0V
Ambient Temperature
64M-bit Mobile RAM is a 4,194,304 words high density RAM
Package
fabricated by CMOS technology for the peripheral circuit and
DRAM cell for the memory array. The interface is compatible to
an asynchronous SRAM.
Ta= -40 ~ 85 degree
72pin S-CSP,
Ball pitch 0.80mm
Outer-ball:Sn-Pb
The cells are automatically refreshed and the refresh control is Application
not required for system. The device also has the partial block
Mobile communication products
refresh scheme and the power down mode by writing the
command.
PIN CONFIGURATION (TOP VIEW)
INDEX(Laser Marking)
1
3
4
5
6
7
8
DU
DU
A
DU
DU
B
GND
A16
A20
C
FRY/BY#
A8
A11
D
A18
A5
A17
MUB#
NC
FRP#
A4
A7
MOE#
A19
DU
A21
A10
A15
E
A0
A6
DU
DQ11
DU
NC
A9
A14
F
A3
DQ9
DU
DQ12
DQ13
DQ15
A13
G
A12
H
FCE1#
FWP#
FWE#
MLB#
NC
10.8 mm
2
GND
A2
DQ8
DQ10
NC
DQ6
MWE#
FOE#
A1
DQ0
DQ2
NC
DQ4
DQ14
GND
J
FCE2#
MCE#
DQ3
FMVCC
DQ5
DQ7
DU
K
DU
L
DU
M
DQ1
DU
DU
(Top View)
8.5 mm
FM-VCC
GND
A0-A21
DQ0-DQ15
F-CE1#
F-CE2#
F-OE#
F-WE#
1
: VCC for Flash / Mobile RAM
: GND for Flash / Mobile RAM
: Common address for Flash/Mobile RAM
: Data I/O
: Flash chip enable 1
: Flash chip enable 2
: Output enable for Flash Memory
: Write enable for Flash Memory
F-RP#
F-WP#
F-RY/BY#
M-CE#
M-OE#
M-WE#
M-LB#
M-UB#
NC
DU
: Reset power down for Flash
: Write protect for Flash
: Flash Memory Ready /Busy
: Mobile RAM chip enable
: Output enable for Mobile RAM
: Write enable for Mobile RAM
: Lower byte control for Mobile RAM
: Upper byte control for Mobile RAM
: Non Connection
: Don’t Use
Rev.1.0.48a_bezb
Renesas LSIs
Preliminary
Notice: This is not a final specification.
Some parametric limits are subject to change.
M6MGD13TW66CWG-P
134,217,728-BIT (8,388,608-WORD BY 16-BIT) CMOS FLASH MEMORY &
67,108,864-BIT (4,194,304-WORD BY 16-BIT) CMOS MOBILE RAM
Stacked-CSP ( Chip Scale Package)
MCP Block Diagram
FM-Vcc GND
A0 to A21
F-RY/BY#
A0 to A21
128Mbit DINOR IV
Flash Memory
F-CE1#
F-CE2#
F-WP#
F-RP#
F-WE#
F-OE#
DQ0 to DQ15
A0 to A21
M-WE#
M-OE#
M-UB#
M-LB#
M-CE#
64Mbit
Mobile RAM
Note: In the 128M-bit DINOR(IV) Flash Memory lower 64Mbit is selected by F-CE1#=“L” and upper 64Mbit is done
by F-CE2#=“L”. Never select each chip at the same time.
In the data sheet there are “VCC”s which mean “FM-VCC” (Common Vcc for Flash / Mobile RAM).
In the Flash Memory part they mean OE# and WE# are F-OE# and F-WE#.
In the Mobile RAM part UB# , LB#, OE# and WE# are M-UB# , M-LB#, M-OE# and M-WE#, respectively.
Capacitance
Symbol
2
Parameter
CIN
Input
capacitance
A21-A0, F-OE#, F-WE#, F-CE1#,
F-CE2#, F-WP#, F-RP#, M-OE#,
M-WE#, M-CE#, M-LB#, M-UB#
COUT
Output
Capacitance
DQ15-DQ0, F-RY/BY#
Conditions
Ta=25°C, f=1MHz,
Vin=Vout=0V
Min.
Limits
Typ.
Max.
Unit
26
pF
34
pF
Rev.1.0.48a_bezb
Renesas LSIs
Preliminary
Notice: This is not a final specification.
Some parametric limits are subject to change.
M6MGD13TW66CWG-P
134,217,728-BIT (8,388,608-WORD BY 16-BIT) CMOS FLASH MEMORY &
67,108,864-BIT (4,194,304-WORD BY 16-BIT) CMOS MOBILE RAM
Stacked-CSP ( Chip Scale Package)
Nippon Bldg.,6-2,Otemachi 2-chome,Chiyoda-ku,Tokyo,100-0004 Japan
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REJ03C0167
© 2003 Renesas Technology Corp.
New publication, effective April 2003.
Specifications subject to change without notice