ETC T64BM34CWG

Renesas LSIs
M6MGB/T64BM34CWG
67,108,864-BIT (4,194,304-WORD BY 16-BIT) CMOS FLASH MEMORY
33,554,432-BIT (2,097,152-WORD BY 16-BIT) CMOS MOBILE RAM
&
Stacked-CSP ( Chip Scale Package)
Description
The M6MGB/T64BM34CWG is a Stacked Chip Scale
The M6MGB/T64BM34CWG is suitable for a high
Package (S-CSP) that contents 64M-bit Flash memory and
performance cellular phone and a mobile PC that are
32M-bit Mobile RAM in a 67-pin Stacked CSP for lead free use. required to be small mounting area, weight and small power
dissipation.
64M-bit Flash memory is a 4,194,304 words, single power
supply and high performance non-volatile memory fabricated
by CMOS technology for the peripheral circuit and DINOR IV
(Divided bit-line NOR IV) architecture for the memory cell. All
memory blocks are locked and can not be programmed or
erased, when F-WP# is Low. Using Software Lock Release
function, program or erase operation can be executed.
Features
Supply Voltage
F-VCC=M-VCC=2.7 ~ 3.0V
32M-bit Mobile RAM is a 2,097,152 words high density RAM
fabricated by CMOS technology for the peripheral circuit and
DRAM cell for the memory array. The interface is compatible
to an asynchronous SRAM.
Ambient Temperature
Ta=-40 ~ 85 degree
Package
67pin S-CSP
Access Time
Flash
70ns (Max.)
Mobile RAM
80ns (Max.)
Ball pitch 0.80mm
The cells are automatically refreshed and the refresh control is
not required for system. The device also has the partial block
refresh scheme and the power down mode by writing the
command.
Outer-ball:Su-Ag-Cu
Application
Mobile communication products
PIN CONFIGURATION (TOP VIEW)
INDEX(Laser Marking)
1
3
4
5
6
7
8
NC
NC
A
NC
NC
B
FWP#
MGND
FWE#
A16
A20
C
FRP#
FRY/BY#
A8
A11
D
A10
A15
E
A9
A14
F
DQ13
DQ15
A13
G
DQ6
MWE#
A12
H
DQ4
DQ14
FGND
J
DQ5
DQ7
NC
K
NC
L
NC
M
A18
MLB#
A5
A17
MUB#
NC
A4
A7
MOE#
A19
A0
A6
NC
10.8 mm
2
FCE#
FGND
FOE#
NC
A3
A21
DQ11
DQ9
DQ12
A2
DQ8
DQ10
NC
A1
DQ0
DQ2
MVCC
MCE#
DQ1
DQ3
FVCC
NC
NC
(Top View)
8.5 mm
F-VCC
:VCC for Flash Memory
M-VCC
:VCC for Mobile RAM
F-GND
:GND for Flash Memory
M-GND
:GND for Mobile RAM
A0-A20
:Common address for Flash/Mobile RAM
A21
:address for Flash
DQ0-DQ15 :Data I/O
F-CE#
:Flash chip enable
M-CE#
:Mobile RAM chip enable
1
F-RY/BY#
F-OE#
M-OE#
F-WE#
M-WE#
F-WP#
F-RP#
M-LB#
M-UB#
: Flash Memory Ready /Busy
:Output enable for Flash Memory
:Output enable for Mobile RAM
:Write enable for Flash Memory
:Write enable for Mobile RAM
:Write protect for Flash
:Reset power down for Flash
:Lower byte control for Mobile RAM
:Upper byte control for Mobile RAM
NC
: Non Connection
Rev.1.1.48a_bezc
Renesas LSIs
M6MGB/T64BM34CWG
67,108,864-BIT (4,194,304-WORD BY 16-BIT) CMOS FLASH MEMORY
33,554,432-BIT (2,097,152-WORD BY 16-BIT) CMOS MOBILE RAM
&
Stacked-CSP ( Chip Scale Package)
MCP Block Diagram
F-Vcc
F-GND
A0 to A21
F-RY/BY#
A0 to A21
F-CE#
F-WP#
F-RP#
F-WE#
F-OE#
64Mbit DINOR IV
Flash Memory
M-Vcc
M-GND
DQ0 to DQ15
A0 to A20
M-WE#
M-OE#
M-UB#
M-LB#
M-CE#
32Mbit
Mobile RAM
Note: In the data sheet there are “VCC”s , “GND”s , “OE”s and “WE”s.
In the Flash Memory part they mean F-Vcc, F-GND, F-OE# and F-WE#.
In the Mobile RAM part they mean M-Vcc, M-GND, M-OE# and M-WE#.
In the Mobile RAM part UB# and LB# are M-UB# and M-LB#, respectively.
Capacitance
Symbol
Parameter
Conditions
Input
A21-A0, F-OE#, F-WE#, F-CE#, F-WP#, Fcapacitance RP#, M-CE#, M-OE#, M-WE#, M-LB#, M-UB# Ta=25°C, f=1MHz,
Vin=Vout=0V
Output
COUT
DQ15-DQ0, F-RY/BY#
Capacitance
CIN
2
Min.
Limits
Typ.
Max.
Unit
18
pF
22
pF
Rev.1.1.48a_bezc
Renesas LSIs
M6MGB/T64BM34CWG
67,108,864-BIT (4,194,304-WORD BY 16-BIT) CMOS FLASH MEMORY
33,554,432-BIT (2,097,152-WORD BY 16-BIT) CMOS MOBILE RAM
&
Stacked-CSP ( Chip Scale Package)
Nippon Bldg.,6-2,Otemachi 2-chome,Chiyoda-ku,Tokyo,100-0004 Japan
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47
REJ03C0035
© 2003 Renesas Technology Corp.
New publication, effective April 2003.
Specifications subject to change without notice
Rev.1.1.48a_bezc
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.