Preliminary Renesas LSIs M6MGB/T331S8AKT Notice: This is not a final specification. Some parametric limits are subject to change. 33,554,432-BIT (2,097,152 - WORD BY 16-BIT /4,194,304-WORD BY 8-BIT) CMOS FLASH MEMORY & 8,388,608-BIT (524,288-WORD BY 16-BIT /1,048,576-WORD BY 8-BIT) CMOS SRAM Stacked - µ MCP (micro Multi Chip Package) Description The M6MGB/T331S8AKT is a Stacked micro Multi Chip Package (S- µMCP) that contents 32M-bit Flash memory and 8M-bit Static RAM in a 52-pin TSOP for lead free use. 32M-bit Flash memory is a 4,194,304 bytes / 2,097,152 words, , single power supply and high performance nonvolatile memory fabricated by CMOS technology for the peripheral circuit and DINOR (Divided bit-line NOR IV) architecture for the memory cell. All memory blocks are locked and can not be programmed or erased, when F-WP# is low. Using Software Lock Release function, program or erase operation can be executed. 8M-bit SRAM is a 1,048,576 bytes / 524,288 words asynchronous SRAM fabricated by CMOS technology for the peripheral circuit . The M6MGB/T331S8AKT is suitable for a high performance cellular phone and a mobile PC that are required to be small mounting area, weight and small power dissipation Features Access Time Flash 70ns (Max.) SRAM 85ns (Max.) Supply Voltage VCC=2.7 ~ 3.0V Ambient Temperature Ta=-40 ~ 85 °C Package 52pin TSOP(Type-II), Lead pitch 0.4mm Outer-lead finishing:Sn-Cu Application Mobile communication products 10.79 mm PIN CONFIGURATION (TOP VIEW) A15 A14 A13 A12 A11 A10 A9 A8 A19 S-CE1# WE# F-RP# F-WP# S-VCC S-CE2 DU A20 A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 M6MGB/T331S8AKT 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 A16 BYTE# S-UB# GND S-LB# DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 F-VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# GND F-CE# A0 52PTJ-A 10.49 mm F-VCC S-VCC GND A-1 - A18 A19 - A20 DQ0 - DQ15 F-CE# S-CE1# S-CE2 OE# WE# 1 :Vcc for Flash :Vcc for SRAM :GND for Flash/SRAM :Flash/SRAM common Address :Address for Flash :Data I/O :Flash Chip Enable :SRAM Chip Enable1 :SRAM Chip Enable2 :Flash/SRAM Output Enable :Flash/SRAM Write Enable Outline F-WP# F-RP# BYTE# S-LB# S-UB# DU :Flash Write protect :Flash Reset Power Down :Flash/SRAM Byte Enable :SRAM Lower Byte :SRAM Upper Byte :Do not use Rev.0.2.48a_bebz Preliminary Renesas LSIs M6MGB/T331S8AKT Notice: This is not a final specification. Some parametric limits are subject to change. 33,554,432-BIT (2,097,152 - WORD BY 16-BIT /4,194,304-WORD BY 8-BIT) CMOS FLASH MEMORY & 8,388,608-BIT (524,288-WORD BY 16-BIT /1,048,576-WORD BY 8-BIT) CMOS SRAM Stacked - µ MCP (micro Multi Chip Package) MCP Block Diagram F-Vcc GND 1) 2) 1) 2) A0 to A20 A0 to A20 F-CE# F-WP# F-RP# BYTE# 32Mbit DINOR(IV) Flash Memory 1) S-Vcc DQ0 to DQ15 1) A0 to A18 WE# OE# S-UB# S-LB# S-CE1# S-CE2 8Mbit SRAM Note 1): In case of x8 organization, A-1 is added, and only Lower Byte data(DQ0 to DQ7) are assigned to I/O and Upper Byte data(DQ8 to DQ15) are High-Z. Note 2): In the data sheet there are “VCC”s which mean “F-VCC” or "S-VCC". In the SRAM part there are “UB#” and “LB#” which mean “S-UB#” and “S-LB#”, respectively. Note 3): “DU(Don’t Use)” pin must be OPEN ,otherwise be inputted within 0V ~ Vcc. Capacitance Symbol Parameter Input A20-A0, OE#, WE#, F-CE#, F-WP#, F-RP#, capacitance S-CE1#, S-CE2, BYTE#, S-LB#, S-UB# Output COUT DQ15-DQ0 Capacitance CIN 2 Conditions Ta=25 °C, f=1MHz, Vin=Vout=0V Min. Limits Typ. Max. Unit 18 pF 22 pF Rev.0.2.48a_bebz Renesa LSIs M6MGB/T331S8AKT 33,554,432-BIT (2,097,152 - WORD BY 16-BIT/4,194,304-WORD BY 8-BIT) CMOS 3.0V-ONLY FLASH MEMORY & 8,388,608-BIT (524,288-WORD BY 16-BIT/1,048,576-WORD BY 8-BIT) CMOS SRAM Stacked - µ MCP (micro Multi Chip Package) Nippon Bldg.,6-2,Otemachi 2-chome,Chiyoda-ku,Tokyo,100-0004 Japan Keep safety first in your circuit designs! • Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. 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New publication, effective April 2003. Specifications subject to change without notice