TOSHIBA TB62202AFG

TB62202AFG
TOSHIBA Bi−CMOS Processor IC Silicon Monolithic
TB62202AFG
Dual-Stepping Motor Driver IC for OA Equipment Using PWM Chopper Type
The TB62202AFG is a dual-stepping motor driver driven by
chopper micro-step pseudo sine wave.
To drive two-phase stepping motors, Two pairs of 16-bit latch and
shift registers are built in the IC. The IC is optimal for driving
stepping motors at high efficiency and with low-torque ripple.
The IC supports Mixed Decay mode for switching the attenuation
ratio at chopping. The switching time for the attenuation ratio
can be switched in four stages according to the load.
Features
z Two stepping motors driven by micro−step pseudo sine wave
are controlled by a single driver IC
Weight: 0.79 g (typ.)
z Monolithic Bi-CMOS IC
z Low ON-resistance of Ron = 1.2 Ω (Tj = 25°C @1.0 A: Typ.)
z Two pairs of built-in 16-bit shift and latch registers
z Two pairs of built-in 4-bit DA converters for micro steps
z Built-in ISD, TSD, VDD and VM power monitor (reset) circuit for protection
z Built-in charge pump circuit (two external capacitors)
z 36-pin power flat package (HSOP36-P-450-0.65)
z Output voltage: 40 V max
z Output current: 1.0 A/phase max
z Built-in Mixed Decay mode enables specification of four-stage attenuation ratio.
(The attenuation ratio table can be overwritten externally.)
z Chopping frequency can be set by external resistors and capacitors. High-speed chopping possible at 100 kHz or
higher.
Note:
When using the IC, pay attention to thermal conditions.
These devices are easy damage by high static voltage.
In regards to this, please handle with care.
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TB62202AFG
Block Diagram
1. Overview (Power lines: A/B unit (C/D unit is the same as A/B unit))
RESET
Logic circuit
Current control data logic circuit
DATA
Chopping
reference circuit
16-bit shift register
16-bit latch
CLK
Chopping
waveform
generator
circuit
STROBE
CR
Current setting
Vref
Torque control
Waveform
chapping
circuit
4-bit DA
(analog control)
Current feedback circuit
RS
VRS
RS COMP
circuit
circuit
Output control circuit
VM
ISD
circuit
Ccp 2
Charge pump
circuit
Output circuit
(H-bridge)
Ccp 1
VM
TSD
circuit
VDDR/VMR
circuit
VDD
Protected circuit
Out X
Stepping
motor
High voltage wiring (VM)
Logic DATA
Analog DATA
IC terminal
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TB62202AFG
2. Logic unit A/B (C/D unit is the same as A/B unit)
Function
This circuit is used to input from the DATA pins micro−step current setting data and to transfer them to the
subsequent stage. By switching the SETUP pin, the data in the mixed decay timing table can be overwritten.
SETUP
Micro-step current setting data logic circuit
MIXED
DECAY
TIMING
16-bit shift register
Output control
circuit
DATA
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
STROBE
A unit side
16-bit latch
Data input
selector
TORQUE
× 2 bits
DECAY
× 2 bits
B unit side
CURRENT
× 4 bits
B unit side
PHASE
× 1 bit
B
D/A circuit
Output control circuit
RESET
Current feedback circuit
Note: The RESET and SETUP pins are pulled down in the IC by 10-kΩ resistor.
When not using these pins, connect them to GND. Otherwise, malfunction may occur.
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TB62202AFG
3. Current feedback circuit and current setting circuit
(A/B unit (C/D unit is the same as A/B unit)
Function
The current setting circuit is used to set the reference voltage of the output current using the micro−step
current setting data input from the DATA pins.
The current feedback circuit is used to output to the output control circuit the relation between the set
current value and output current. This is done by comparing the reference voltage output to the current
setting circuit with the potential difference generated when current flows through the current sense resistor
connected between RS and VM.
The chopping waveform generator circuit to which CR is connected is used to generate clock used as
reference for the chopping frequency.
Vref
100%
85%
70%
50%
Torque
Control
circuit
Current setting circuit
CURRENT
0~3
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Micro-step current setting
selector circuit
LOGIC
UNIT
TORQUE
0, 1
Chopping waveform
generator circuit
Waveform shaping circuit
4-bit
D/A
circuit
CR
Mixed decay
timing circuit
Chopping reference circuit
Output stop signal (ALL OFF)
Use in Charge mode
RS
VM
VRS circuit 1
(detects
potential
difference
between
RS and VM)
RS COMP
circuit 1
(Note 1)
VRS circuit 2
(detects
potential
difference
between
VM and RS)
RS COMP
circuit 2
(Note 2)
NF
(set current reached signal)
Output
control circuit
RNF
(set current monitor signal)
Use in Fast mode
Current feedback circuit
Note 1: RS COMP 1: Compares the set current with the output current and outputs a signal when the output current
reaches the set current.
Note 2: RS COMP 2: Compares the set current with the output current at the end of Fast mode during chopping.
Outputs a signal when the set current is below the output current.
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TB62202AFG
4. Output control circuit, current feedback circuit and current setting circuit (A/B unit
(C/D unit is the same as A/B unit)
Micro-step current setting
data logic circuit
Output control circuit
Chopping
reference circuit
DECAY
MODE
PHASE
MIXED
DECAY
TIMING
circuit
NF
set current
reached signal
Current
feedback
circuit
CR
COUNTER
RNF
set current
monitor signal
MIXED
DECAY
TIMING
CR COUNTER
Charge start
Current
setting
circuit
Output stop
signal
U1
U2
Output control circuit
Output circuit
L1
L2
Output RESET signal
VDD
VM
Power supply
for upper
output MOS
transistors
RESET
Output pin
ISD (current
shutdown)
circuit
VM
VMR
circuit
VDD
VDDR
circuit
Charge
pump
halt
signal
Reset signal
selector
circuit
VH
Charge pump
circuit
Ccp C
Charge pump
circuit
Protection circuit
MIXED DECAY
TIMING TABLE
CLEAR signal
MICRO-STEP
CURRENT SETUP
LATCH CLEAR signal
Note:
Ccp A
Ccp B
Thermal
shut down
(TSD)
circuit
VDDR: VDD power on Reset
VMR: VM power on Reset
ISD:
Current shutdown circuit
TSD: Thermal shutdown circuit
Output
circuit
LOGIC
The RESET pins is pulled down in the IC by 10-kΩ resistor.
When not using the pin, connect it to GND. Otherwise, malfunction may occur.
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5. Output equivalent circuit (A/B unit (C/D unit is the same as A/B unit)
RS A
Output driver
circuit
From output
control circuit
U1
U2
L1
L2
To VM
RRS A
U2
U1
Output A
Power supply
for upper
output MOS
transistors
(VH)
L2
L1
Output A
Phase A
VM B
RS B
Output driver
circuit
From output
control circuit
U1
U2
L1
L2
Power supply
for upper
output MOS
transistors
(VH)
U1
RRS B
U2
Output B
L1
L2
M
Output B
Phase B
PGND
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TB62202AFG
6. Input equivalent circuit
(1) Logic input circuit (CLK, DATA, STROBE)
VDD 27
IN
To Logic IC
150 Ω
30/29/31
25/26/24
GND
FIN
(2) Input circuit ( RESET )
VDD 27
IN
GND
To Logic IC
10 kΩ
28
150 Ω
FIN
(3) Vref input circuit
VDD 27
IN
4
9/10
To D/A circuit
GND
FIN
Note: RESET pin is pulled down. Do not use them open.
When not using these pins, connect them to GND.
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TB62202AFG
Pin Assignment
(top view)
VM B
1
36
VM A
OUT B
2
35
OUT A
RS B
3
34
RS A
PGND
4
33
PGND
OUT B
5
32
OUT A
NC
6
31
STROBE AB
Ccp A
7
30
CLK AB
CR
8
29
DATA AB
VREF AB
9
28
RESET
TB62202AFG
VSS (FIN)
VSS (FIN)
VREF CD
10
27
VDD
NC
11
26
DATA CD
Ccp B
12
25
CLK CD
Ccp C
13
24
STROBE CD
OUT D
14
23
OUT C
PGND
15
22
PGND
RS D
16
21
RS C
OUT D
17
20
OUT C
VM D
18
19
VM C
Note: [Important] If this IC is inserted reverse, voltages exceeding the voltages of standard may be applied to some
pins, causing damage.
Please confirm the pin assignment before mounting and using the IC.
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TB62202AFG
Pin Description
Pin No.
Pin Symbol
Description
1
VM B
2
OUT B
3
RS B
4
PGND
Power GND pin
5
OUT B
Output B pin
6
NC
Non connection
7
Ccp A
8
CR
9
VREF AB
Voltage major for output B block
Output B pin
Channel B current pin
Capacitor pin for charge pump (Ccp1)
External C/R (osc) pin (sets chopping frequency)
Vref input pin AB
FIN
VSS
10
VREF CD
FIN (VSS) : Logic GND pin
11
NC
12
Ccp B
Capacitor pin for charge pump (Ccp2)
13
Ccp C
Capacitor pin for charge pump (Ccp2)
14
OUT D
Output D pin
15
PGND
Power GND pin
16
RS D
17
OUT D
18
VM D
Voltage major for output D block
19
VM C
Voltage major for output C block
20
OUT C
21
RS C
22
PGND
Power GND pin
23
OUT C
Output C pin
24
STROBE CD
Vref input pin CD
Non connection
Channel D current pin
Output D pin
Output C pin
Channel C current pin
CD STROBE (latch) signal input pin (
25
CLK CD
26
DATA CD
27
VDD
Power pin for logic block
FIN
VSS
FIN (VSS) : Logic GND pin
28
RESET
29
DATA AB
30
CLK AB
31
STROBE AB
32
OUT A
Output A pin
33
PGND
Power GND pin
34
RS A
35
OUT A
36
VM A
: LATCH)
CD clock input pin
CD serial data signal input pin
Output reset signal input pin (L : RESET)
AB serial data signal input pin
AB clock input pin
AB STROBE (latch) signal input pin (
: LATCH)
Channel A current pin
Output A pin
Voltage major for output A block
Note: How to handle GND pins
All power GND pins and FIN (VSS: signal GND) pins must be grounded.
Since FIN also functions as a heat sink, take the heat dissipation into consideration when designing the board.
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TB62202AFG
Signal Functions
1. Serial input signals (for A/B. C/D is the same as A/B)
Data No.
0
LSB
Name
Functions
DATA No.0, 1 = HH: 100%, LH: 85%
TORQUE 0
HL: 70%, LL: 50%
1
TORQUE 1
2
DECAY MODE B0
3
DECAY MODE B1
4
Current B0
5
Current B1
6
Current B2
7
Current B3
8
PHASE B
Phase information (H: OUT A: H, OUT A : L)
9
DECAY MODE A0
10
DECAY MODE A1
00: DECAY MODE 0, 01: DECAY MODE 1
10: DECAY MODE 2, 11: DECAY MODE 3
11
Current A0
12
Current A1
13
Current A2
14
Current A3
15
MSB
00: DECAY MODE 0, 01: DECAY MODE 1
10: DECAY MODE 2, 11: DECAY MODE 3
Used for setting current.
(LLLL = Output ALL OFF MODE)
4−bit current B data
(Steps can be divided into 16 by 4−bit data)
(Note 1)
Used for setting current.
(LLLL = Output ALL OFF MODE)
4−bit current A data
(Steps can be divided into 16 by 4−bit data)
Phase information (H : OUT A : H, OUT A : L)
PHASE A
Note 1: Serial data input order
Serial data are input in the order LSB (DATA 0)
→ MSB (DATA 15)
Role of Data
Data Name
TORQUE
Number of Bits
2
Functions
Roughly regulates the current (four stages).
Common to A and B units.
DECAY MODE
2 × 2 phases
Selects Decay mode.
A and B units are set separately.
CURRENT
4 × 2 phases
Sets a 4−bit micro−step electrical angle.
A and B units are set separately.
PHASE
1 × 2 phases
Determines polarity (+ or −).
A and B units are set separately.
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2. Serial input signal functions
Input
CLK
Action
STROBE
DATA
RESET
VDDR
(Note 1) or
VMR
×
×
H
H
L
No change in shift register.
×
H
H
H
L
H level is input to shift register.
×
Operation of
TSD/ISD
(Note 2)
L
H
H
L
L level is input to shift register.
×
×
H
H
L
Shift register data are latched.
×
×
H
H
L
×
×
×
L
×
L
×
×
×
×
L
L
Qn
Output off, charge pump halted
(S/R DATA CLR)
Output off (S/R DATA CLR)
Charge pump halted
Mixed decay timing table cleared (only VDDR)
Output off (S/R DATA HOLD)
×
×
×
H
H
H
Charge pump halted
Restored when RESET goes from Low to High
×:
Don’t Care
Qn:
Latched output level when STROBE is
.
Note 1: VDDR and VMR
H when the operable range (3 V typical) or higher and L when lower.
When one of VDDR or VMR is operating, the system resets (OR relationship).
Note 2: High when TSD is in operation.
When one of TSD or ISD is operating, the system resets (OR relationship).
Note: Function of overcurrent protection circuit
Until the RESET signal is input after ISD is triggered, the overcurrent protection circuit remains in operation.
During ISD, the charge pump stays halted.
When TSD and ISD are operating, the charge pump halts.
3. PHASE functions
Input
Function
H
Positive polarity (A: H, Α : L)
L
Negative polarity (A: L, Α : H)
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4. DECAY mode X0, X1 functions
DECAY Mode X1
DECAY Mode X0
Function
L
L
Decay Mode 0
(Initial value: SLOW DECAY MODE)
L
H
Decay Mode 1
(Initial value: MIXED DECAY MODE: 37.5%)
H
L
Decay Mode 2
(Initial value: MIXED DECAY MODE: 75%)
H
H
Decay Mode 3
(Initial value: FAST DECAY MODE)
5. TORQUE functions
TORQUE 0
TORQUE 1
Comparator Reference Voltage Ratio
H
H
100%
L
H
85%
H
L
70%
L
L
50%
6. Current AX (BX) functions
Step
Set Angle
A3
A2
A1
A0
B3
B2
B1
B0
16
90.0
H
H
H
H
L
L
L
L
15
84.4
H
H
H
H
L
L
L
H
14
78.8
H
H
H
L
L
L
H
L
13
73.1
H
H
L
H
L
L
H
H
12
67.5
H
H
L
L
L
H
L
L
11
61.2
H
L
H
H
L
H
L
H
10
56.3
H
L
H
L
L
H
H
L
9
50.6
H
L
L
H
L
H
H
H
8
45.0
H
L
L
L
H
L
L
L
7
39.4
L
H
H
H
H
L
L
H
6
33.8
L
H
H
L
H
L
H
L
5
28.1
L
H
L
H
H
L
H
H
4
22.5
L
H
L
L
H
H
L
L
3
16.9
L
L
H
H
H
H
L
H
2
11.3
L
L
H
L
H
H
H
L
1
5.6
L
L
L
H
H
H
H
H
0
0.0
L
L
L
L
H
H
H
H
By inputting the above current data (A: 4-bit, B: 4-bit), 17-microstep drive is possible. For 1 step fixed to 90
degrees, see the section on output current vector line (85 page).
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TB62202AFG
7. Serial data input setting
DATA
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
STROBE
Note: Data input to the DATA pin are 16-bit serial data.
Data are transferred from DATA 0 (Torque 0) to DATA 15 (Phase A). Data are input and transferred at the
following timings.
At CLK falling edge: data input
At CLK rising edge: data transfer
After data are transferred, all data are latched on the rising edge of the STROBE signal.
As long as STROBE is not rising, the signal can be either Low or High during data transfer.
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TB62202AFG
Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Rating
Unit
Logic supply voltage
VDD
7
V
Output voltage
VM
40
V
Output current
IOUT
1.5
A/phase
Current detect pin voltage
VRS
VM ± 4.5
V
Charge pump pin maximum voltage
(CCP1 pin)
VH
VM + 7.0
V
Logic input voltage
VIN
to VDD + 0.4
V
Power dissipation
PD
1.4
W
(Note 2)
3.2
W
(Note 3)
Operating temperature
Topr
−40 to 85
°C
Storage temperature
Tstg
−50 to 150
°C
Junction temperature
Tj
150
°C
(Note 1)
Note 1: Perform thermal calculations for the maximum current value under normal conditions. Use the IC at 1.2 A or
less per phase.
Note 2: Input 7 V or less as VIN.
Note 3: Measured for the IC only. (Ta = 25°C)
Note 4: Measured when mounted on the board. (Ta = 25°C)
Ta: IC ambient temperature
Topr: IC ambient temperature when starting operation
Tj: IC chip temperature during operation Tj (max) is controlled by TSD (thermal shut down circuit)
Recommended Operating Conditions (Ta = 0 to 85°C)
Characteristics
Symbol
Test Condition
Min
Typ.
Max
Unit
Power supply voltage
VDD
⎯
4.5
5.0
5.5
V
Output voltage
VM
VDD = 5.0 V
20
24
34
V
IOUT (1)
Ta = 25°C, per phase
(when one motor is driven)
⎯
0.6
0.9
A
IOUT (2)
Ta = 25°C, per phase
(when two motors are driven)
⎯
0.6
0.9
A
GND
⎯
VDD
V
Output current
⎯
Logic input voltage
VIN
Clock frequency
fCLK
VDD = 5.0 V
1.0
6.25
25
MHz
Chopping frequency
fchop
VDD = 5.0 V
40
100
150
KHz
Reference voltage
Vref
VM = 24 V, Torque = 100%
2.0
3.0
VDD
V
Current detect pin voltage
VRS
VDD = 5.0 V
0
±1.0
±1.5
V
Note: Use the maximum junction temperature (Tj) at 120°C or less
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TB62202AFG
Electrical Characteristics 1
(Unless otherwise specified, Ta = 25°C, VDD = 5 V, VM = 24 V)
Characteristics
Test
Circuit
Min
Typ.
Max
2.0
VDD
VDD
+ 0.4
GND
− 0.4
GND
0.8
―
―
1.0
―
―
1.0
―
―
700
―
―
700
VDD = 5 V (STROBE, RESET ,
DATA = L), RESET = L,
Logic, output all off
―
3.0
6.0
IDD2
Output OPEN, fCLK = 6.25 MHz
LOGIC ACTIVE, VDD = 5 V,
Charge pump = charged
―
4.0
8.0
IM1
Output OPEN (STROBE, RESET ,
DATA = L), RESET = L,
Logic, output all off
Charge Pump = no operation
―
5.0
6.0
IM2
Output OPEN, fCLK = 6.25 MHz
LOGIC ACTIVE, VDD = 5 V,
VM = 24 V, Output off
Charge Pump = charged
―
12
20
IM3
Output OPEN, fCLK = 6.25 MHz
LOGIC ACTIVE, 100 kHz
chopping (emulation), Output OPEN,
Charge Pump = charged Ccp1 =
0.22 µF, Ccp2 = 0.01µf
―
30
40
VRS = VM = 24 V, Vout = 0 V,
RESET = H, DATA = ALL L
−400
―
―
VRS = VM = 24 V, Vout = 24 V,
RESET = H, DATA = ALL L
−200
―
―
VRS = VM = CcpA = Vout = 24 V,
RESET = L
―
―
1.0
Vref = 3.0 V,
Vref (Gain) = 1/5.0
TORQUE = (H.H) = 100% set
―
100
―
Vref = 3.0 V, Vref (Gain) = 1/5.0
TORQUE = (H.L) = 85% set
83
85
87
68
70
72
Symbol
High
VIN (H)
Low
VIN (L)
1
Input voltage
IIN1 (H)
Input current 1
IIN1 (L)
IIN2 (H)
Input current 2
2
RESET , SETUP pins
IDD1
2
3
Power dissipation (VM pin)
Output standby
current
Upper
IOH
Output bias current
Upper
IOB
Output leakage
current
Lower
IOL
High
(Reference)
VRS (H)
Mid High
VRS (MH)
Comparator
reference voltage
ratio
CLK, RESET , STROBE, DATA pins
CLK, STROBE, DATA pins
IIN2 (L)
Power dissipation (VDD pin)
Test Condition
4
5
6
Unit
V
µA
µA
mA
Mid Low
VRS (ML)
Vref = 3.0 V, Vref (Gain) = 1/5.0
TORQUE = (L.H) = 70% set
LOw
VRS (L)
Vref = 3.0 V, Vref (Gain) = 1/5.0
TORQUE = (L.L) = 50% set
48
50
52
mA
µA
%
Output current differential
∆Iout1
7
Differences between output current
channels
Iout = 1000 mA
−5
―
5
%
Output current setting differential
∆Iout2
7
Iout = 1000 mA
−5
―
5
%
IRS
8
VRS = 24 V, VM = 24 V,
RESET = L (RESET status)
―
―
10
µA
RS pin current
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TB62202AFG
Characteristics
Output transistor drain-source
on-resistance
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
RON (D-S) 1
Iout = 1.0 A, VDD = 5.0 V
Tj = 25°C, Drain-source
―
1.1
1.3
RON (D-S) 1
Iout = 1.0 A, VDD = 5.0 V
Tj = 25°C, Source-drain
―
1.1
1.3
RON (D-S) 2
Iout = 1.0 A, VDD = 5 V,
Tj = 105°C, Drain-source
―
1.4
1.6
RON (D-S) 2
Iout = 1.0 A, VDD = 5 V,
Tj = 105°C, Source-drain
―
1.4
1.6
9
16
Unit
Ω
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TB62202AFG
Electrical Characteristics 2
(Unless otherwise specified, Ta = 25°C, VDD = 5 V, VM = 24 V)
Symbol
Test
Circuit
Vref input voltage
Vref
10
Vref input current
Iref
Vref attenuation ratio
TSD temperature
Min
Typ.
Max
Unit
VM = 24 V, VDD = 5 V,
RESET = H, Output on
2.0
⎯
VDD
V
10
RESET = H, Output off
VM = 24 V, VDD = 5 V,
Vref = 3.0 V
0
⎯
100
µA
Vref (GAIN)
6
VM = 24 V, VDD = 5 V,
RESET = H, Output on,
Vref = 2.0 to VDD − 1.0 V
1/4.8
1/5.0
1/5.2
⎯
TjTSD (Note
1)
11
VDD = 5 V, VM = 24 V
130
⎯
170
°C
∆TjTSD
11
TjTSD = 130 to 170°C
⎯
TjTSD
− 35
⎯
°C
VDD return voltage
VDDR
12
VM = 24 V, RESET = H,
STROBE = H
2.0
⎯
4.0
V
VM return voltage
VMR
13
VDD = 5 V, RESET = H,
STROBE = H
2.0
⎯
4.0
V
ISD
(Note 2)
14
VDD = 5V, VM = 24V,
fchop = 100 kHz set
⎯
2.6
⎯
A
Characteristics
TSD return temperature difference
Over current protected circuit
operation current
Test Condition
Note 1: Thermal shut down (TSD) circuit
When the IC junction temperature reaches the specified value and the TSD circuit is activated, the internal
reset circuit is activated switching the outputs of both motors to off.
When the temperature is set between 130 (min) to 170°C (max), the TSD circuit operates. When the TSD
circuit is activated, the function data latched at that time are cleared. Output is halted until the reset is
released. While the TSD circuit is in operation, the charge pump is halted.
Even if the TSD circuit is activated and RESET goes H → L → H instantaneously, the IC is not reset until
the IC junction temperature drops 35°C (typ.) below the TSD operating temperature (hysteresis function).
Note 2: Overcurrent protection circuit
When current exceeding the specified value flows to the output, the internal reset circuit is activated
switching the outputs of both shafts to off.
When the ISD circuit is activated, the function data latched at that time are cleared.
Until the RESET signal is input, the overcurrent protection circuit remains activated.
During ISD, the charge pump halts.
For failsafe operation, be sure to add a fuse to the power supply.
17
2005-04-04
TB62202AFG
Electrical Characteristics 3
(Ta = 25°C, VDD = 5 V, VM = 24 V, Iout = 1.0 A)
Characteristics
Chopper current
SymboL
Vector
Test
Circuit
15
Test Condition
Min
Typ.
Max
θA = 90 (θ16)
⎯
100
⎯
θA = 84 (θ15)
⎯
100
⎯
θA = 79 (θ14)
93
98
⎯
θA = 73 (θ13
91
96
―
θA = 68 (θ12)
87
92
97
θA = 62 (θ11)
83
88
93
θA = 56 (θ10)
78
83
88
θA = 51 (θ9)
72
77
82
66
71
76
θA = 40 (θ7)
58
63
68
θA = 34 (θ6)
51
56
61
θA = 28 (θ5)
42
47
52
θA = 23 (θ4)
33
38
43
θA = 17 (θ3)
24
29
34
θA = 11 (θ2)
15
20
25
θA = 6 (θ1)
5
10
15
θA = 0 (θ0)
⎯
0
⎯
θA = 45 (θ8)
18
⎯
Unit
%
2005-04-04
TB62202AFG
AC Characteristics (Ta = 25°C, VM = 24 V, VDD = 5 V, 6.8 mH/5.7 Ω)
Characteristics
Clock frequency
SymboL
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
fCLK
16
⎯
1.0
⎯
25
MHz
40
⎯
⎯
20
⎯
⎯
twn (CLK)
20
⎯
⎯
tSTROBE
40
⎯
⎯
20
⎯
⎯
20
⎯
⎯
20
⎯
⎯
20
⎯
⎯
20
⎯
⎯
20
⎯
⎯
⎯
0.1
⎯
⎯
0.1
⎯
STROBE (↑) to VOUT
Output Load; 6.8 mH/5.7 Ω
⎯
15
⎯
⎯
10
⎯
CR to VOUT
Output Load; 6.8 mH/5.7 Ω
⎯
1.2
⎯
⎯
2.5
⎯
200
300
400
ns
tw (CLK)
Minimum clock pulse width
Minimum STROBE pulse width
twp (CLK)
tSTROBE (H)
⎯
16
⎯
16
tSTROBE (L)
Data setup time
Data hold time
tsuSIN-CLK
tsuST-CLK
thSIN-CLK
thCLK-ST
16
⎯
16
⎯
tr
Output Load ; 6.8 mH/5.7 Ω
tf
Output transistor switching
characteristic
tpLH (ST)
tpHL (ST)
18
tpLH (CR)
tpHL (CR)
ns
ns
ns
ns
µs
Noise rejection dead band time
tBLNK
19
Iout = 1.0 A
CR reference signal oscillation
frequency
fCR
20
Cosc = 560 pF, Rosc = 3.6 kΩ
⎯
800
⎯
kHz
40
100
150
kHz
20
Output active (Iout = 1.0 A)
Step fixed, Ccp1 = 0.22 µF,
Ccp2 = 0.01µF
Output active (Iout = 1.0 A)
CR CLK = 800 kHz
⎯
100
⎯
kHz
Ccp2 = 0.22µF, Ccp = 0.01 µF
VM = 24 V, VDD = 5 V,
RESET = L → H
⎯
2
4
ms
Chopping frequency range
fchop (min)
fchop (typ.)
fchop (max)
Chopping frequency
fchop
Charge pump rise time
tONG
21
19
2005-04-04
TB62202AFG
Test Waveforms (Timing waveforms and names)
tw (CLK)
50%
CLK
tsuST-CLK
thCLK-ST
twn
twp
50%
STROBE
tSTROBE (H)
tSTROBE (L)
tsuSIN-CLK
DATA
50%
DATA15
thSIN-CLK
tSTROBE
DATA0
50%
CR waveform
(reference)
tpHL (CR)
tpHL (ST)
90%
OUTPUT
voltage A
50%
10%
tpLH (CR)
tpLH (ST)
90%
OUTPUT
voltage A
90%
50%
50%
10%
10%
tr
20
tf
2005-04-04
TB62202AFG
Test Waveforms (Timing waveforms and names)
OSC-Charge Delay
OSC-Fast Delay
H
OSC (CR)
L
T chop
H
OUTPUT
voltage A
50%
L
H
OUTPUT
voltage A
50%
50%
L
Set current
OUTPUT
current
L
Charge
Slow
21
Fast
2005-04-04
TB62202AFG
Calculation of Set Current
Determining RRS and Vref determines the set current value.
Iout (Max) =
Torque (Torque = 100, 85, 70, 50% : input serial data )
1
× Vref (V) ×
R RS (Ω)
Vref (GAIN)
1/5.0 is Vref (gain) : Vref attenuation ratio (typ.).
For example,
to input Vref = 3 V and Torque = 100% and to output Iout = 0.8 A,
RRS = 0.75 Ω (0.5 W or more) is required.
Formulas for Calculating CR Oscillation Frequency (Chopping reference frequency)
The CR oscillation frequency and fchop can be calculated by the following formulas:
fCR =
1
[Hz]
KA × (C× R× KB × C)
KA (constant): 0.523
KB (constant): 600
f
fchop = CR [Hz]
8
Example : When Cosc = 1,000 pF and Rosc = 2.0 kΩ are connected, fCR = 735 kHz.
At this time, the chopping frequency fchop is : fchop = fCR/8 = 92 kHz.
1
Note: fCR =
tCR
tCR = t (Charge) + t (Dis - Charge)
CR oscillation CR charge
cycle
time
CR distance
time
At this time, t (CR-discharge) is subject to the following condition:
600 ns > t (CR-discharge) > 400 ns.
Be sure to set the CR value in accordance with this condition.
22
2005-04-04
TB62202AFG
CR Circuit Constants
OSC circuit oscillation waveform
t (CR-charge)
t (CR-dis-charge)
E1
E2
t=0
t=1
t=2
The OSC circuit generates the chopping reference signal by charging and discharging the external capacitor Cosc
through current supplied from the external resistor Rosc in the OSC block.
Voltages E1 and E2 in the diagram are set by dividing the VDD by approximately 3/5 (E1) and 2/5 (E2).
The actual current chopping time is 1/8 the CR frequency.
[Important: Setting the CR Circuit Constants]
The CR oscillation waveform is converted in the IC to the CLK waveform (CR-CLK signal) and used for control.
If the CR waveform discharge time is set outside the range shown below, the operation of the IC is not guaranteed.
Be sure to set the CR waveform discharge time within the following range.
600 ns > t (CR discharge) > 400 ns
23
2005-04-04
TB62202AFG
IC Power Dissipation
IC power dissipation is classified into two: power consumed by transistors in the output block and power consumed
by the logic block and the charge pump circuit.
(1) Power consumed by the Power Transistor (calculated with Ron = 1.3 Ω)
In Charge mode, Fast Decay mode, or Slow Decay mode, power is consumed by the upper and lower
transistors of the H bridges. The following expression expresses the power consumed by the transistors of a
H bridge.
P (out) = 2 (Tr) × Iout (A) × VDS (V) = 2 × Iout^2 × Ron ·························(1)
The average power dissipation for output under 4-bit micro step operation (phase difference between
phases A and B is 90°) is determined by expression (1).
Thus, power dissipation for output per unit is determined as follows (2) under the conditions below.
Ron = 1.3 Ω (@1.0 A)
Iout (Peak : Max) = 0.6 A
VM = 24 V
VDD = 5 V
P (out) = 2 (Tr) × 0.6 (A)^2 × 1.3 (Ω) ·················································(2)
= 0.936 (W)
(2) Power consumed by the logic block and IM
The following standard values are used as power dissipation of the logic block and IM at operation.
I (LOGIC) = 2 mA (Typ.): /unit
I (IM3) = 12.5 mA (Typ.): operation/unit
I (IM1) = 6.0 mA (Typ.): stop/unit
The logic block is connected to VDD (5 V). IM (total of current consumed by the circuits connected to VM
and current consumed by output switching) is connected to VM (24 V). Power dissipation is calculated as
follows:
P (Logic and IM) = 5 (V) × 0.002 (A) + 24 (V) × 0.0125 (A) ....................... (3)
= 0.31 (W)
(3) Thus, power dissipation for 1 unit (P) is determined as follows by (2) and (3) above.
P = P (out) + P (Logic and IM) = 1.246 (W)
Power dissipation for 1 unit at standby is determined as follows:
P (standby) = 24 (V) × 0.006 (A) + 5 (V) × 0.002 (A)
= 0.154 (W)
When one motor driving = 100 %, power dissipation is determined as follows:
P (all) = 1.246 (W) + 0.154 (W) = 1.4 (W)
For thermal design on the board, evaluate by mounting the IC.
24
2005-04-04
TB62202AFG
MIXED DECAY Mode Waveforms (concept of mixed decay mode)
fchop
CR pin
input
waveform
Set current value
DECAY MODE 0
SLOW
DECAY
MODE
Slow
NF
Charge
DECAY MODE 1
37.5%
MIXED
DECAY
MODE
Set current value
Slow
NF
Charge
Monitoring
set current
value
Fast
MDT
RNF
DECAY MODE 2
75%
MIXED
DECAY
MODE
Set current value
NF
Charge
Fast
MDT
Monitoring
set current
value
RNF
DECAY MODE 3
NF
FAST
DECAY
MODE
Set current value
Charge
Fast
Monitoring
set current
value
RNF
100%
87.5%
75%
62.5%
50%
37.5%
25%
12.5%
0
NF is the point where the output current reaches the set current value. RNF is the timing for monitoring the set
current.
In Mixed Decay and Fast Decay modes, where the condition RNF (set current monitor signal) < (output current)
applies, Charge mode is cancelled at the next chopping cycle (charge cancel circuit). Therefore, at the next chopping
cycle, the IC enters Slow + Fast modes (Slow → Fast at MDT).
25
2005-04-04
TB62202AFG
Test Circuit (A/B unit only. C/D unit conforms to A/B unit.)
Rosc AB
= 3.6 kΩ
1. VIN (H), VIN (L)
Cosc AB
= 560 pF
3V
Vref AB 9
8 CR
SGND
VM A 36
SGND
RRS A 34
A
5V
0V
5V
0V
5V
0V
27 VDD
IDD1, IDD2
RRS A
A 32
A 35
31 STROBE AB
B 2
30 CLK AB
B
29 DATA AB
Vary VIN
5
RRS B 3
RRS B
VM B 1
VSS
(FIN)
SGND
Ccp C 13
SGND
6 SETUP
5V
VDD
Ccp B 12
A
Ccp A 7
P-GND
0.01 µF
0 V to 5 V
No reset at testing
RESET = 5 [V]
Ccp 2
0.22 µF
28 RESET
Ccp 1
24 V
IIN (H), IIN (L) A
: PGND
: SGND (VSS)
Test method
VIN (H): Set RESET to High and vary the logic input voltage from 0 to 7 V.
Monitor IDD and measure the change point (VM = 24 V).
VIN (L): Set RESET to High and vary the logic input voltage from 5 to 0 V.
Monitor IDD and measure the change point.
Setup data
DATA
CLK
STROBE
H
L
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
H
L
H
L
26
2005-04-04
TB62202AFG
Rosc AB
= 3.6 kΩ
2. IIN (H), IIN (L), IDD1, IDD2 (A/B unit only. C/D unit conforms to A/B unit.)
Cosc AB
= 560 pF
3V
Vref AB 9
8 CR
SGND
VM A 36
SGND
RRS A 34
A
5V
0V
5V
0V
5V
0V
27 VDD
IDD1, IDD2
RRS A
A 32
A 35
31 STROBE AB
B 2
30 CLK AB
B
29 DATA AB
Vary VIN
5
RRS B 3
RRS B
VM B 1
VSS
(FIN)
SGND
Ccp C 13
SGND
6 SETUP
5V
VDD
Ccp B 12
A
Ccp A 7
P-GND
0.01 µF
0 V to 5 V
No reset at testing
RESET = 5 [V]
Ccp 2
0.22 µF
28 RESET
Ccp 1
24 V
IIN (H), IIN (L) A
: PGND
: SGND (VSS)
Test method
IIN (H):
IIN (H):
IDD1:
IDD2:
Set RESET to High, set the the logic input voltage to 5 V, and measure the input current.
Set RESET to High, set the the logic input voltage to 0 V, and measure the input current.
Apply VDD, input RESET, and measure IDD.
Input 6.25 MHz clock and measure the current when the logic is operating. Set output to OPEN.
Setup data
DATA
CLK
STROBE
H
L
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
H
L
H
L
27
2005-04-04
TB62202AFG
Rosc
= 3.6 kΩ
3. IM1, IM2 (A/B unit only. C/D unit conforms to A/B unit.)
Cosc
= 560 pF
3V
Vref AB 9
8 CR AB
SGND
VM A 36
SGND
RRS A 34
27 VDD
5V
0V
5V
0V
5V
0V
A 32
A 35
31 STROBE AB
B 2
30 CLK AB
B
29 DATA AB
5
RRS B 3
VM B 1
VSS
(FIN)
SGND
At IM1 testing: RESET = L (0 V)
At IM2 testing: RESET = H (5 V)
5V
VDD
Ccp A 7
P-GND SETUP
6
SGND
Ccp 2
Ccp 1
IM A
24 V
Ccp B 12
0.01 µF
5V
Ccp C 13
0.22 µF
28 RESET
: PGND
: SGND (VSS)
Test method
IM1: Set the logic block to non-active (DATA = all 0), VDD = 5 V, VM = 24 V, and output to open. Measure the
current input from VM supply. RESET = L
IM2: Set the logic block only to active (CLK = 6.25 MHz), VM = 24 V, and output to open. Measure the
current input from VM supply. RESET = H
Setup data
DATA
CLK
STROBE
H
L
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
H
L
H
L
28
2005-04-04
TB62202AFG
Rosc
= 3.6 kΩ
4. IM3 (A/B unit only. C/D unit conforms to A/B unit.)
Cosc
= 560 pF
3V
Vref AB 9
8 CR AB
SGND
VM A 36
SGND
RRS A 34
27 VDD
5V
0V
5V
0V
5V
0V
A 32
A 35
31 STROBE AB
B 2
30 CLK AB
B
29 DATA AB
5
RRS B 3
VM B 1
VSS
(FIN)
SGND
SGND
No reset at testing
RESET = 5 [V]
Ccp A 7
P-GND SETUP
6
Ccp 2
Ccp 1
A IM
24 V
VDD
5V
Ccp B 12
0.01 µF
5V
Ccp C 13
0.22 µF
28 RESET
: PGND
: SGND (VSS)
This is the IM current when all of the circuits, including the output transistors, in the IC are operating.
The IM current includes the current dissipation in the charge pump circuit, output gate loss, and output
predriver.
Because the IM current (IM3) is input from the RS pin, which is also used for the output current, IM3 cannot be
measured by the normal testing methods.
Use the method shown below.
Setup data
The serial data PHASE signal (both A and B) switch over to high or low.
DATA
CLK
STROBE
H
L
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
H
L
H
L
Test method
Set output to open, change phase data from 1 → 0 → 1 → 0 and perform switching. When testing, input
phase data at double the chopping frequency (if fchop = 100 kHz, fDATA = 200 kHz) and measure the current
value of VM supply.
fDATA = 200 kHz means that the phase switches at 200 kHz.
29
2005-04-04
TB62202AFG
Number of switchings at phase switching
Number of switchings at actual operation
Mode changes three times
in one chopping cycle.
One phase switching
(16-bit data input)
Four transistors switching
To VM
RRS
RRS
To VM
Chopping cycle
U1
U2
U1
U2
ON
OFF
OFF
ON
Load
Switches by phase data
OFF
ON
Load
L2
L1
L2
OFF
ON
ON
OFF
OFF
ON
ON
Charge
ON
Slow
Two transistors
switching
OFF
Four transistors switching
One phase switching
(16-bit data input)
OFF
Two transistors
switching
L1
PGND
OFF
ON
Four transistors switching
PGND
Eight transistors switching
in one chopping cycle
Four transistors are switched at one phase switching
OFF
ON
Fast
Number of switchings at actual operation = 2 × number of switchings at phase switching.
Therefore, switching the phase at 2 × chopping cycle matches the number of switchings at actual operation
with the number of switchings at phase switching, and allows the actual current dissipation, IM3, to be
measured.
30
2005-04-04
TB62202AFG
Rosc
= 3.6 kΩ
5. IOB, IOH, IOL (A/B unit only. C/D unit conforms to A/B unit.)
Cosc AB
= 560 pF
3V
Vref AB 9
8 CR AB
SGND
VM A 36
SGND
RRS A 34
27 VDD
5V
0V
5V
0V
5V
0V
A 32
A
IOB
A 35
31 STROBE AB
B 2
30 CLK AB
B
29 DATA AB
IOH, IOL
A
5
RRS B 3
VM B 1
VSS
(FIN)
SGND
5V
Ccp B 12
VDD
SGND
No reset at testing
RESET = 5 [V]
Ccp A 7
P-GND
Ccp 2
Ccp 1
24 V
Ccp C 13
0.01 µF
5V
IOL
0.22 µF
28 RESET
: PGND
: SGND (VSS)
Test method
IOH:
IOB:
IOL:
With VM = 24 V, VDD = 5 V, and logic input all = 0 applied, set RESET = H, connect the output pins
to GND, and measure the supply current.
With VM = 24 V, VDD = 5 V, and logic input all = 0 applied, set RESET = H, connect the output pins
to VM, and measure the supply current.
With VM = 24 V, VDD = 5 V, and logic input all = 0 applied, set RESET = L, connect the output pins
to GND, and measure the supply current.
Setup data
DATA
CLK
STROBE
H
L
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
H
L
H
L
31
2005-04-04
TB62202AFG
6. VRS (H to L), Vref (GAIN) (when measuring phase A) after measurement
Rosc AB
= 3.6 kΩ
(A/B unit only. C/D unit conforms to A/B unit.)
Cosc AB
= 560 pF
3V
Vref AB 9
8 CR AB
SGND
VM A 36
SGND
RRS A 34
27 VDD
5V
0V
5V
0V
5V
0V
A 32
A 35
31 STROBE AB
B 2
30 CLK AB
B
29 DATA AB
V
Oscilloscope
5
RRS B 3
Vary between
0 and 1 V.
VM B 1
VSS
(FIN)
SGND
SGND
No reset at testing
RESET = 5 [V]
Ccp A 7
P-GND
Ccp 2
Ccp 1
24 V
VDD
5V
Ccp B 12
0.01 µF
5V
Ccp C 13
0.22 µF
28 RESET
: PGND
: SGND (VSS)
VRS (H to L): Input torque data = 100% (HH) and vary the voltage between VM and RS pins.
Measure the voltage (VRS) when output changes from fixed Charge mode to another mode.
Also measure VRS when torque data = 85% (HL), 70% (LH), or 50% (LL) as above and calculate the
ratio using VRS value at 100% as reference.
Vref (GAIN): Vref (GAIN) =
VRS (*)
((*) VRS: when torque data = 100%)
Vref
Setup data
DATA
CLK
STROBE
H
L
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
H
L
H
L
32
2005-04-04
TB62202AFG
7. ∆Iout1, ∆Iout2 (A/B unit only. C/D unit conforms to A/B unit.)
3V
Vref AB 9
8 CR
SGND
VM A 36
SGND
RRS A 34
27 VDD
5V
0V
5V
0V
5V
0V
RRS A
A 32
Monitors
current
waveform.
A 35
31 STROBE AB
B 2
30 CLK AB
B
29 DATA AB
5
RRS B 3
RRS B
VM B 1
VSS
(FIN)
SGND
No reset at testing
RESET = 5 [V]
5V
VDD
SGND
Ccp A 7
P-GND
Ccp 2
Ccp 1
24 V
Ccp B 12
0.01 µF
5V
Ccp C 13
0.22 µF
28 RESET
: PGND
: SGND (VSS)
With L load, perform chopping in Mixed Decay mode. Monitor the output current waveform and measure the
various output currents at constant current operation.
Setup data
Set to100%
H
DATA
L
0
1
2
3
4
5
6
7
8
9
10
11
13
14
15
H
CLK
L
STROBE
H
L
MDT
Current
waveform
12
Output current
value (set
current value)
100% 0%
0%
Charge
MDT
Slow
Slow
Fast
Fast
Measurement of
peak current
Charge
33
2005-04-04
TB62202AFG
Rosc
= 3.6 kΩ
8. IRS (when measuring phase A) (A/B unit only. C/D unit conforms to A/B unit)
Cosc
= 560 pF
3V
Vref AB 9
8 CR AB
SGND
VM A 36
SGND
RRS A 34
27 VDD
A
A 32
A 35
31 STROBE AB
B 2
30 CLK AB
B
29 DATA AB
5
RRS B 3
VM B 1
VSS
(FIN)
SGND
Ccp A 7
P-GND
SGND
Ccp 2
Ccp 1
24 V
VDD
5V
Ccp B 12
0.01 µF
Ccp C 13
RESET = L
0.22 µF
28 RESET
: PGND
: SGND (VSS)
With L input to RESET , connect VM and RRS to the power supply, and measure the current input to the RS
pin. (Either drop all the input pins to GND level or input all Low data to the DATA pin, then perform
measurement. At that time, leave all other output pins open.)
Setup data
DATA
CLK
STROBE
H
L
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
H
L
H
L
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2005-04-04
TB62202AFG
9. RON (D-S), RON (S-D) when measuring output A (A/B unit only. C/D unit conforms to A/B
Rosc
= 3.6 kΩ
unit.)
Cosc
= 560 pF
3V
Vref AB 9
8 CR AB
SGND
VM A 36
SGND
RRS A 34
27 VDD
5V
0V
5V
0V
5V
0V
A 32
A 35
31 STROBE AB
Curve tracer
B 2
30 CLK AB
B
29 DATA AB
5
RRS B 3
VM B 1
Curve tracer
VSS
(FIN)
SGND
SGND
No reset at testing
RESET = 5 [V]
Ccp A 7
P-GND
Ccp 2
Ccp 1
24 V
5V
Ccp B 12
0.01 µF
5V
Ccp C 13
0.22 µF
28 RESET
: PGND
: SGND (VSS)
Input the current setting data (HHHH signal) to the DATA pin and measure the voltage between VM and OUT
when Iout = 1000 mA or the voltage between OUT and GND. Then, change the phase and repeat measurement.
At that time, leave the output pins which are not measured open.
Setup data (Vary the phase data during testing.)
DATA
CLK
STROBE
H
L
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
H
L
H
L
35
2005-04-04
TB62202AFG
10. Vref, Iref (A/B unit only. C/D unit conforms to A/B unit.)
Rosc AB
= 3.6 kΩ
Oscilloscope
Vref AB 9
Cosc AB
= 560 pF
8 CR AB
VM A 36
SGND
*: When measuring Iref,
fix Vref = 3 V and
measure.
Monitor
A
Iref (*) Vary Vref
= 2 to VDD − 1.0 V
SGND
RRS A 34
27 VDD
A 32
31 STROBE AB
A 35
B 2
30 CLK AB
B
29 DATA AB
5
RRS B 3
VM B 1
VSS
(FIN)
SGND
SGND
No reset at testing
RESET = 5 [V]
Ccp A 7
P-GND
Ccp 2
Ccp 1
24 V
VDD
5V
Ccp B 12
0.01 µF
5V
Ccp C 13
0.22 µF
28 RESET
: PGND
: SGND (VSS)
Vref: Vary Vref = 2 to VDD − 1 V and confirm that output is on.
Iref: When VM = 24 V and VDD = 5 V, apply the specified voltage of 3 V to the Vref and monitor the current
flow value.
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2005-04-04
TB62202AFG
11. TjTSD, ∆TjTSD (Measure in an environment such as an constant temperature chamber where
Rosc
= 3.6 kΩ
the temperature for the IC can be freely changed) (A/B unit only. C/D unit conforms to A/B
unit.)
Cosc
= 560 pF
3V
Vref AB 9
8 CR AB
SGND
VM A 36
SGND
RRS A 34
27 VDD
5V
0V
5V
0V
5V
0V
A 32
A 35
31 STROBE AB
Curve tracer
B 2
30 CLK AB
B
29 DATA AB
5
RRS B 3
VM B 1
Curve tracer
VSS
(FIN)
SGND
SGND
No reset at testing
RESET = 5 [V]
Ccp A 7
P-GND
Ccp 2
Ccp 1
24 V
5V
Ccp B 12
0.01 µF
5V
Ccp C 13
0.22 µF
28 RESET
: PGND
: SGND (VSS)
TjTSD:
Increase the ambient temperature. Measure the temperature when output stops.
∆TjTSD: Gradually lower the temperature from the level when the TSD circuit was operating (output off). At
that time, control the RESET input thus : H → L → H → L. Output will begin at a certain
temperature level.
∆TjTSD is the difference between the temperature at which output begins and the temperature at
which TSD is triggered.
Setup data
DATA
CLK
STROBE
H
L
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
H
L
H
L
37
2005-04-04
TB62202AFG
12. VDDR (A/B unit only. C/D unit conforms to A/B unit.)
SGND
3V
Vref AB 9
8 CR AB
Cosc
= 560 pF
VDD
5V
Rosc
= 3.6 kΩ
Oscilloscope
SGND
VM A 36
SGND
RRS A 34
27 VDD
5V
0V
5V
0V
5V
0V
RRS A
A 32
A 35
31 STROBE AB
B 2
30 CLK AB
B
29 DATA AB
5
RRS B 3
RRS B
VM B 1
VSS
(FIN)
No reset at testing
RESET = 5 [V]
VDD
SGND
Ccp A 7
P-GND
Vary from 0 V
0.01 µF
Ccp B 12
Ccp 2
0.22 µF
5V
Ccp C 13
Ccp 1
VM
24 V
SGND
28 RESET
: PGND
: SGND (VSS)
Monitor the output pins. Increase the VDD voltage from 0. Measure the VDD value when output starts.
Next, decrease the VDD voltage and measure the VDD value when output stops.
Setup data
DATA
CLK
STROBE
H
L
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
H
L
H
L
38
2005-04-04
TB62202AFG
13. VMR (A/B unit only. C/D unit conforms to A/B unit.)
Rosc
= 3.6 kΩ
Oscilloscope
Cosc
= 560 pF
3V
Vref AB 9
8 CR AB
SGND
VM A 36
SGND
RRS A 34
27 VDD
5V
0V
5V
0V
5V
0V
RRS A
A 32
A 35
31 STROBE AB
B 2
30 CLK AB
B
29 DATA AB
5
RRS B 3
RRS B
VM B 1
VSS
(FIN)
SGND
Ccp B 12
No reset at testing
RESET = 5 [V]
SGND
5V
VDD
Ccp A 7
P-GND
0.01 µF
5V
Ccp C 13
Ccp 2
0.22 µF
28 RESET
Ccp 1
Vary from 0 V
: PGND
: SGND (VSS)
With the CLK signal and DATA (all High) input, increase the VM voltage from 0.
Measure the VM value when output starts.
Next, decrease the VM voltage and measure the VM value when output stops.
Setup data
DATA
CLK
STROBE
H
L
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
H
L
H
L
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2005-04-04
TB62202AFG
14. Overcurrent protector circuit (ISD) (To measure output A : )
Rosc AB
= 3.6 kΩ
(A/B unit only. C/D unit conforms to A/B unit.)
Cosc AB
= 560 pF
3V
Vref AB 9
8 CR AB
SGND
VM A 36
SGND
RRS A 34
27 VDD
5V
0V
5V
0V
5V
0V
A 32
A 35
31 STROBE AB
Curve tracer
B 2
30 CLK AB
B
29 DATA AB
5
RRS B 3
VM B 1
Curve tracer
VSS
(FIN)
SGND
SGND
At measuring, non-reset
RESET = 5 [V]
Ccp A 7
P-GND
Ccp 2
Ccp 1
24 V
5V
Ccp B 12
0.01 µF
5V
Ccp C 13
0.22 µF
28 RESET
: PGND
: SGND (VSS)
Test method: To monitor operating current of the overcurrent protector circuit when output A is short-circuited
to the power supply
Input the current setting data (HHHH signal) to the DATA pin. If short-circuited to the supply, measure the
lower output transistors. If short-circuited to ground, measure the upper output transistors (see how to measure
RON).
When measuring RON, increase the current flow. There is a current value at which output is switched off and
RON cannot be measured. This value is the set current value for the overcurrent protector circuit.
Make sure to leave open the output pins not being measured.
Note that if the temperature changes, the value may fluctuate. Try to avoid applying power to the IC by
one-shot measuring.
Setup data (Example : The phase signal must be changed depending on the pin.)
DATA
CLK
STROBE
H
L
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
H
L
H
L
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2005-04-04
TB62202AFG
Rosc
= 3.6 kΩ
15. Current vector (A/B unit only. C/D unit conforms to A/B unit.)
Cosc
= 560 pF
3V
Vref AB 9
8 CR
SGND
VM A 36
SGND
RRS A 34
27 VDD
5V
0V
5V
0V
5V
0V
RRS A
A 32
Monitor
current
waveform
A 35
31 STROBE AB
B 2
30 CLK AB
B
29 DATA AB
5
RRS B 3
RRS B
VM B 1
VDD
5V
Ccp B 12
SGND
At measuring, non-reset
RESET = 5 [V]
Ccp A 7
P-GND
Ccp 2
Ccp 1
24 V
5V
Ccp C 13
SGND
0.01 µF
28 RESET
0.22 µF
VSS
(FIN)
: PGND
: SGND (VSS)
Perform chopping in Mixed Decay mode with load L. Monitor the output current waveform and measure the output
current at constant current operation. At this time, vary the 4-bit data for current setting and measure the
current values. Using the set output current as 100%, calculate the output current ratio.
100%
Output current
(example)
71%
100%
0%
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2005-04-04
TB62202AFG
Rosc
= 3.6 kΩ
16. fCLK, tw (CLK), twp (CLK), twn (CLK), tSTROBE, tSTROBE (H), tSTOBE (L),
tsuSIN-CLK, tsuST-CLK, thSIN-CLK, thCLK-ST (A/B unit only. C/D unit conforms to A/B unit.)
Cosc
= 560 pF
3V
Vref AB 9
8 CR AB
SGND
VM A 36
SGND
RRS A 34
27 VDD
5V
0V
5V
0V
5V
0V
RRS A
A 32
A 35
31 STROBE AB
B 2
30 CLK AB
B
29 DATA AB
5
RRS B 3
RRS B
VM B 1
VSS
(FIN)
SGND
No reset at testing
RESET = 5 [V]
Ccp A 7
5V
P-GND
VDD
SGND
Ccp 2
Ccp 1
24 V
Ccp B 12
0.01 µF
5V
Ccp C 13
0.22 µF
28 RESET
: PGND
: SGND (VSS)
Input any data at fCLK (max), perform chopping, and monitor the output waveform.
For the measuring points, see the timing chart below.
Setup data
DATA
H
0
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
H
CLK
L
STROBE
H
L
Measuring points
tw (CLK)
CLK
50%
thCLK-ST
tsuST-CLK
STROBE
tsuSIN-CLK
DATA
twn (CLK) twp (CLK)
50%
50%
DATA15
tSTROBE (H)
tSTROBE (L)
tSTROBE
thSIN-CLK
50%
DATA0
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2005-04-04
TB62202AFG
Rosc
= 3.6 kΩ
17. OSC-fast delay, OSC-charge delay (A/B unit only. C/D unit conforms to A/B unit.)
Cosc
= 560 pF
3V
Vref AB 9
8 CR AB
SGND
VM A 36
SGND
RRS A 34
27 VDD
5V
0V
5V
0V
5V
0V
RRS A
A 32
A 35
31 STROBE AB
B 2
30 CLK AB
B
29 DATA AB
5
RRS B 3
RRS B
VM B 1
VSS
(FIN)
No reset at testing
RESET = 5 [V]
5V
VDD
SGND
Ccp A 7
P-GND
Ccp 2
Ccp 1
24 V
Ccp B 12
0.01 µF
5V
Ccp C 13
0.22 µF
SGND
28 RESET
: PGND
: SGND (VSS)
Fix the output current value in Mixed Decay mode and turn the output on. Measure the time until the output
switches from the CR pin waveform and the output voltage waveform.
Setup data
DATA
CLK
STROBE
H
L
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
H
L
H
L
Top
CR
Bottom
Osc-fast delay
Vout A
Osc-charge delay
50%
50%
50%
50%
Vout A
50%
50%
(Mode)
Charge
Slow
Fast
43
Charge
2005-04-04
TB62202AFG
Rosc
= 3.6 kΩ
18. tpHL (ST), tpLH (ST), tr, tf (A/B unit only. C/D unit conforms to A/B unit.)
Monitor
Cosc
= 560 pF
3V
Vref AB 9
8 CR AB
SGND
VM A 36
SGND
RRS A 34
27 VDD
RL = 5.7 Ω
A 35
31 STROBE AB
L = 6.8 mH
5V
0V
5V
0V
5V
0V
RRS A
A 32
B 2
30 CLK AB
B
29 DATA AB
5
RRS B 3
RRS B
VM B 1
VSS
(FIN)
SGND
VDD
SGND
No reset at testing
RESET = 5 [V]
Ccp A 7
P-GND
Ccp 2
Ccp 1
24 V
5V
Ccp B 12
0.01 µF
5V
Ccp C 13
0.22 µF
28 RESET
: PGND
: SGND (VSS)
Setup data
DATA
H
L
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
H
CLK
L
STROBE
H
L
Switch PHASE every 130 µs and measure the output pin voltage and the STROBE signal.
[Oscilloscope waveform (example)]
130 µs
STROBE
50%
50%
tpHL (ST)
OUTPUT
50%
Voltage A
tpLH (ST)
OUTPUT
Voltage A
90%
90%
50%
10%
tr
44
10%
tf
2005-04-04
TB62202AFG
Rosc AB
= 3.6 kΩ
19. tBRANK (A/B unit only. C/D unit conforms to A/B unit.)
Cosc AB
= 560 pF
3V
Vref AB 9
8 CR AB
SGND
VM A 36
SGND
RRS A 34
27 VDD
5V
0V
5V
0V
5V
0V
RRS A
A 32
A 35
31 STROBE AB
B 2
30 CLK AB
B
29 DATA AB
5
RRS B 3
RRS B
VM B 1
VSS
(FIN)
SGND
SGND
No reset at testing
RESET = 5 [V]
Ccp A 7
P-GND
Ccp 2
Ccp 1
24 V
5V
Ccp B 12
0.01 µF
5V
Ccp C 13
0.22 µF
28 RESET
: PGND
: SGND (VSS)
tBRANK is the dead time band for avoiding malfunction caused by noise. Apply sufficient differential voltage
(when Vref = 3 V, 0.6 V or higher) to VM-RS and apply duty. When the pulse width reaches a certain value,
triggering feedback and changing the output. Check the value.
Measure the pulse width
where output changes.
VM
RS pin voltage
Apply pulse to the RS pin so that the
RS pin = VM voltage − 1.0 V.
H
Output operation
L
Setup data
DATA
CLK
STROBE
H
L
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
H
L
H
L
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2005-04-04
TB62202AFG
20. fchop (fchop (min), fchop (max)) (A/B unit only. C/D unit conforms to A/B unit.)
Vref AB 9
8 CR AB
3V
Cosc AB
= 560 pF
Rosc AB
= 3.6 kΩ
Oscilloscope
SGND
VM A 36
SGND
RRS A 34
27 VDD
RRS A
A 32
31 STROBE AB
A 35
B 2
30 CLK AB
B
29 DATA AB
5
RRS B 3
RRS B
VM B 1
VDD
5V
Ccp B 12
Ccp A 7
P-GND
SGND
Ccp 2
Ccp 1
24 V
Ccp C 13
SGND
0.01 µF
28 RESET
0.22 µF
VSS
(FIN)
: PGND
: SGND (VSS)
Change the Rosc and Cosc values and measure the frequency on the CR pin using the oscilloscope.
At this time, 1/8 of the frequency of the measured CR waveform is fchop.
Oscilloscope waveform (example)
1/8 fchop (SYNC) = fCR
t=0
t=1
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2005-04-04
TB62202AFG
Rosc
= 3.6 kΩ
21. tONG (A/B unit only. C/D unit conforms to A/B unit.)
Cosc
= 560 pF
3V
Vref AB 9
8 CR AB
SGND
VM A 36
SGND
RRS A 34
27 VDD
5V
0V
5V
0V
5V
0V
RRS A
A 32
A 35
31 STROBE AB
B 2
30 CLK AB
B
29 DATA AB
5
RRS B 3
RRS B
VM B 1
VDD
5V
Ccp B 12
SGND
At measuring, change
from reset to non-reset.
Ccp A 7
P-GND
Ccp 2
Ccp 1
24 V
5V
Ccp C 13
SGND
0.01 µF
28 RESET
0.22 µF
VSS
(FIN)
: PGND
: SGND (VSS)
Apply VM and VDD and change RESET from L to H.
Measure the time until the CcpA pin becomes VM + VDD × 90%.
VDD + VM
VM + (VDD × 90%)
VM
5V
RESET
50%
0V
tONG
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2005-04-04
TB62202AFG
Rosc
= 3.6 kΩ
22. Mixed decay timing (A/B unit only. C/D unit conforms to A/B unit.)
Cosc
= 560 pF
3V
Vref AB 9
8 CR
SGND
VM A 36
SGND
RRS A 34
27 VDD
5V
0V
5V
0V
5V
0V
RRS A
A 32
A 35
31 STROBE AB
B 2
30 CLK AB
B
29 DATA AB
5
RRS B 3
RRS B
VM B 1
VSS
(FIN)
SGND
Ccp B 12
6 SETUP
P-GND
Ccp A 7
5V
SGND
Ccp 2
Ccp 1
24 V
At measuring, non-reset
RESET = 5 [V]
0.01 µF
Ccp C 13
0.22 µF
5V
VDD
5V
28 RESET
: PGND
: SGND (VSS)
With VM = 24 V, VDD = 5 V, RESET = H, change the SETUP pin from L to H and overwrite the MIXED DECAY
TIMING TABLE.
Then change the SETUP pin from H to L. With load L, perform chopping and monitor the output current
waveform at that time. Confirm that the switching timing from Slow Decay Mode to Fast Decay Mode within an
fchop cycle is the specified MIXED DECAY TIMING.
(Depending on the load L value and the test environment, chopping may be performed every two cycles or there
may be no Slow Decay Mode. If so, conditions, for example, load condition, may need to be changed.
Output current value
(set current value)
MDT
0%
MDT
Slow
Charge
MDT
100% 0%
MDT
Fast
Slow
Fast
Charge
Current waveform
48
2005-04-04
TB62202AFG
Waveforms in Various Current Modes (Ideal Waveform)
Normal MIXED DECAY MODE Waveform
NF is the point at which the output current
reaches the set current value.
fchop
fchop
CR CLK
signal
Iout
NF
Set current value
Set current
value
NF
12.5% MIXED
DECAY MODE
RNF
MDT (MIXED DECAY TIMING) point
When NF is after MIXED DECAY Timing
Fast Decay mode after Charge mode.
Iout
Set current value
MDT (MIXED DECAY TIMING) point
Set current
value
NF
NF
RNF
37.5% MIXED
DECAY MODE
RNF
STROBE signal input
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2005-04-04
TB62202AFG
In MIXED DECAY MODE, when the output current > the set current value
fchop
Set
current
value
fchop
NF
RNF
Iout
fchop
CHARGE MODE for one fchop
cycle after STROBE signal input
fchop
Because the set current value > the
output current, no CHARGE MODE in
the next cycle.
NF
12.5%
MIXED
DECAY
MODE
RNF
NF
Set current value
MDT (MIXED DECAY TIMING) point
RNF
STROBE signal input
FAST DECAY MODE Waveform
NF is the point at which the output
current reaches the set current value.
fchop
Set current
value
Iout
FAST DECAY
MODE
(0% MIXED
DECAY MODE)
Because the set current value > the output current,
FAST DECAY MODE in the next cycle, too
RNF
Set current value
NF
RNF
Because the set current value > the output current, CHARGE
MODE → NF → FAST DECAY MODE in the next cycle, too
RNF
STROBE signal input
Response delay time
50
2005-04-04
TB62202AFG
STROBE Signal, Internal CR CLK, and output Current Waveform
(When STROBE Signal is input in SLOW DECAY MODE)
fchop
fchop
fchop
37.5% MIXED DECAY MODE
Set current
value
MDT
Iout
NF
Set current
value
MDT
RNF
RNF
Momentarily enters
CHARGE MODE
STROBE signal input
Reset CR-CLK
counter here
When STROBE signal is input, the chopping counter (CR-CLK counter) is forced to reset at the next CR-CLK
timing.
Because of this, compared with a method in which the counter is not reset, response to the input data is faster.
(The delay time, the theoretical value in the logic portion, is expected to be a one-cycle CR waveform: 1.25 µS
@100 kHz CHOPPING.)
When the CR-CLK counter is reset due to STROBE signal input, CHARGE MODE is entered momentarily due to
current comparison.
Note: In FAST DECAY MODE, too, CHARGE MODE is entered momentarily due to current comparison.
51
2005-04-04
TB62202AFG
STROBE Signal, Internal CR CLK, and output Current Waveform
(When STROBE signal is input in CHARGE MODE)
fchop
fchop
Set current
value
fchop
MDT
37.5% MIXED DECAY MODE
Iout
NF
Set current
value
RNF
MDT
RNF
Momentarily enters
CHARGE MODE
STROBE signal input
52
2005-04-04
TB62202AFG
(When STROBE Signal is input in FAST DECAY MODE)
fchop
fchop
fchop
37.5% MIXED DECAY MODE
Set
current
value
NF
MDT
MDT
Iout
NF
Set current value
MDT
RNF
RNF
Momentarily enters
CHARGE MODE
STROBE signal input
53
2005-04-04
TB62202AFG
(When PHASE Signal is input)
37.5% MIXED DECAY MODE
fchop
fchop
fchop
Set current
value
Iout
0
RNF
RNF
Set current
value
NF
MDT
NF
STROBE signal input
54
2005-04-04
TB62202AFG
(When current point 0 control is included)
37.5% MIXED DECAY MODE
fchop
fchop
fchop
Set current
value
Iout
(1)
(2)
0
(1)
(2)
(1)
(1)
Set current
value
STROBE signal input
Reset CR-CLK
counter here
Reset CR-CLK
counter here
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2005-04-04
TB62202AFG
(When FAST DECAY MODE is included during the sequence)
fchop
fchop
fchop
fchop
fchop
Set current
value
37.5% MIXED DECAY MODE
FAST DECAY MODE
Set current
value
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2005-04-04
TB62202AFG
(When SLOW DECAY MODE is included during the sequence)
fchop
fchop
fchop
fchop
fchop
fchop
Set current
value
SLOW DECAY MODE
37.5% MIXED DECAY MODE
fchop
Set current
value
In SLOW DECAY MODE, depending on the load,
the set current cannot be accurately traced.
Therefore, do not use SLOW DECAY MODE.
37.5% MIXED DECAY MODE
STROBE
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2005-04-04
TB62202AFG
Current Modes
(MIXED (= SLOW + FAST) Decay Mode Effect)
z Sine wave in increasing (Slow Decay Mode (Charge + Slow + Fast) normally used)
Slow
Set current
value
Set current
value
Fast
Charge
Fast
Charge
Slow
Slow
Slow
Charge
Fast
Fast
Charge
z Sine wave in decreasing (When using MIXED DECAY Mode with large attenuation ratio (MDT%) at attenuation)
Slow
Slow
Set current
value
Charge
Because current attenuates so quickly, the current
immediately follows the set current value.
Fast
Charge
Fast
Slow
Slow
Set current
value
Fast
Fast
Charge
z Sine wave in decreasing (When using MIXED DECAY Mode with small attenuation ratio (MDT%) at attenuation)
Slow
Set current
value
Because current attenuates slowly, it takes a
long time for the current to follow the set current
value (or the current does not follow).
Slow
Fast
Charge
Fast
Charge
Charge
Fast
Charge
Set current
value
Fast
Note: The above charts are schematics. The actual current transient responses are curves.
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TB62202AFG
Output Transistor Operating Mode
To VM
To VM
To VM
RRS
RRS
RS pin
RRS
RS pin
U2
U1
RS pin
U2
U1
(Note)
(Note)
Load
(Note)
Load
L1
L2
Load
L2
L1
PGND
PGND
Charge mode
(Charges coil power)
U2
U1
L1
L2
PGND
Slow mode
(Slightly attenuates coil power)
Fast mode
(Drastically attenuates coil power)
Output Transistor Operation Functions
CLK
U1
U2
L1
L2
CHARGE
ON
OFF
OFF
ON
SLOW
OFF
OFF
ON
ON
FAST
OFF
ON
ON
OFF
Note: The above table is an example where current flows in the direction of the arrows in the above figures.
When the current flows in the opposite direction of the arrows, see the table below.
CLK
U1
U2
L1
L2
CHARGE
OFF
ON
ON
OFF
SLOW
OFF
OFF
ON
ON
FAST
ON
OFF
OFF
ON
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2005-04-04
TB62202AFG
Output Transistor Operating Mode 2
(Sequence of MIXED DECAY MODE)
To VM
To VM
To VM
RRS
RRS
U2
U1
OUT A
OUT A
L1
L2
RRS
U1
U2
U1
U2
OUT A
OUT A
OUT A
OUT A
L2
L1
L2
L1
PGND
PGND
PGND
H
OUTPUT
voltage A
50%
L
H
OUTPUT
voltage A
50%
50%
L
Set current
OUPUT
current
L
Charge Mode
Slow Mode
Fast Mode
The constant current is controlled by changing mode from Charge → Slow → Fast.
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2005-04-04
TB62202AFG
Current Discharge Path when Current Data = 0000 are input during operation
In Slow Decay Mode, when all output transistors are forced to switch off, coil energy is discharged in the following
MODES :
Note: Parasitic diodes are located on dotted lines. In normal MIXED DECAY MODE, the current does not flow to the
parasitic diodes. However, when signal 0000 is input during operation, the current flows to them.
To VM
To VM
RRS
RRS
RS pin
U1
ON
To VM power supply
(Note)
RRS
U2
U1
OFF
OFF
Load
(Note)
L2
L1
OFF
ON
ON
Charge mode
U2
U1
OFF
OFF
Input Current DATA
= 0000
Load
L1
PGND
RS pin
RS pin
L2
ON
U2
(Note)
OFF
Load
L1
L2
OFF
OFF
PGND
PGND
Slow Decay mode
Forced OFF mode
As shown in the figure at right, an output transistor has parasitic diodes.
To discharge energy from the coil, each transistor is switched on allowing current to flow in the reverse direction to
that in normal operation. As a result, the parasitic diodes are not used. If all the output transistors are forced to
switch off, the energy of the coil is discharged via the parasitic diodes.
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TB62202AFG
PD-Ta (Package Power Dissipation)
PD – Ta
3.5
(2)
(1) Rth (j-a) IC only (96°C/W)
(2) When mounted on the board
Power dissipation PD
(W)
3.0
(38°C/W)
Board size(100 × 200 × 1.6 mm)
* Rth (j-c): 8.5°C/W
2.5
2.0
1.5
(1)
1.0
0.5
0
0
25
50
75
Ambient temperature
62
100
125
150
Ta (°C)
2005-04-04
TB62202AFG
Power Supply Sequence (Recommended)
VDD (max)
VDD (min)
VDD
VDDR
GND
VM
VM
VM (min)
VMR
GND
NON-RESET
Internal reset
RESET
RESET
input
････*
H
RESET
L
Takes up to tONG until operable.
t
Non-operable area
Note 1: If the VDD drops to the level of the VDDR or below while the specified voltage is input to the VM pin, the IC is
internally reset. This is a protective measure against malfunction. Likewise, if the VM drops to the level of the
VMR or below while regulation voltage is input to the VDD, the IC is internally reset as a protective measure
against malfunction. To avoid malfunction, when turning on VM or VDD, we recommend you input the
RESET signal at the above timing.
It takes time for the output control charge pump circuit to stabilize. Wait up to tONG time after power on
before driving the motors.
Note 2: When the VM value is between 3.3 to 5.5 V, the internal reset is released, thus output may be on. In such a
case, the charge pump cannot drive stably because of insufficient voltage. We recommend the RESET state
be maintained until VM reaches 20 V or more.
Note 3: Since VDD = 0 V and VM = voltage within the rating are applied, output is turned off by internal reset. At that
time, a current of several mA flows due to the Pass between VM and VDD.
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TB62202AFG
Relationship between VM and VH
VH is the voltage of the CcpA pin. It is the highest voltage in this IC (power supply for driving the upper gate of the
H bridge).
VM – VH (& Vcharge up)
50
VH voltage
(V)
VM voltage
VDD = 5 V
Ccp1 = 0.22 µF
Ccp2 = 0.02 µF
VH = VDD + VM (CcpA)
Charge up voltage
VH voltage, charge up voltage, VM voltage
40
Input RESET.
( RESET = 0 V)
30
Maximum
VMR
20
Usable area
10
0
0
Recommended operation area
5
10
15
20
Supply voltage
25
VM
30
35
40
(V)
z V charge Up is the voltage to boost VM to VH. Usually equivalent to VDD.
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2005-04-04
TB62202AFG
Operation of Charge Pump Circuit
VM = 24 V
RRS
RS
1/18/19/36
VH
Ccp A
7
i2
Di2
Di1
i1
(2)
Tr2
Comparator
&
Controller
(1)
Output
VZ
Output
H switch
Di3
Ccp B
12
(2)
13
R1
Ccp 1 = 0.22 µF
3/16/21/34
VM
Ccp 2 = 0.01 µF
27
VDD = 5 V
Ccp C
Tr1
VH = VM + VDD = charge pump voltage
i1 = charge pump current
i2 = gate block power dissipation
z Initial charging
(1) When RESET is released, Tr1 is turned ON and Tr2 turned OFF. Ccp2 is charged from Ccp2 via Di1
(This is the same as when TSD and ISD are operating and the IC is restored from Reset state.)
(2) Tr1 is turned OFF, Tr2 is turned ON, and Ccp1 is charged from Ccp2 via Di2.
(3) When the voltage difference between VM and VH (CcpA pin voltage = charge pump voltage) reaches VDD or
higher, operation halts (Steady state : Because the capacitor is naturally discharged, the IC is continually
charging to the capacitor).
z Actual operation
(4) Ccp1 charge is used at fchop switching and the VH potential drops.
(5) Charges up by (1) and (2) above.
Output switching
Charge pump voltage
Initial charging
Normal state
VH
VM
(1)
(2)
(4)
(3)
(5)
(4)
(5)
t
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2005-04-04
TB62202AFG
External Capacitors for Charge Pumps
When VDD = 5V, fchop = 100 kHz, and L = 10 mH is driven with VM = 24 V, Iout = 1100 mA, the theoretical values
for Ccp1 and Ccp2 are as shown below:
Ccp 1 – Ccp 2
0.05
Usable area
0.045
‹ Ccp 1 = (NG)
„ Ccp 2 = (OK)
Ccp 2 capacitance
(µF)
0.04
0.035
0.03
Recommended area
0.025
0.02
Recommended value
0.015
0.01
0.005
0
0
„
„
‹
‹
„
‹
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Ccp 1 capacitance
(µF)
Combine Ccp1 and Ccp2 as shown in the shaded area in the above graph.
Select values 10: 1 or more for Ccp1: Ccp2.
When making a setting, evaluate properly and set values with a margin.
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2005-04-04
TB62202AFG
Charge Pump Rise Time
VDD + VM
VM + (VDD × 90%)
VM
5V
50%
RESET
0V
tONG
tONG: Time taken for capacitor Ccp2 (charging capacitor) to fill up Ccp1 (capacitor used to save charge) to VM +
VDD after a reset is released.
The internal IC cannot drive the gates correctly until the voltage of Ccp1 reaches VM + VDD. Be sure to
wait for tONG or longer before driving the motors.
Basically, the larger the Ccp1 capacitance, the longer the initial charge-up time but the smaller the
voltage fluctuation.
The smaller the Ccp1 capacitance, the shorter the initial charge-up time but the larger the voltage
fluctuation.
Depending on the combination of capacitors (especially with small capacitance), voltage may not be
sufficiently boosted. Thus, use the capacitors under the capacitor combination conditions (Ccp1 = 0.22 µF,
Ccp2 = 0.01 µF) recommended by Toshiba.
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2005-04-04
TB62202AFG
Operating Time for Overcurrent Protector Circuit
(ISD non-sensitivity time and ISD operating time)
Output halts (Reset status)
CR oscillation
(basic chopping waveform)
MIN
(Non-sensitivity time)
MIN
MAX
MAX
ISD operating time
ISD BLANK time
Point where overcurrent flows to output transistors (overcurrent status start)
A non-sensitivity time is set for the overcurrent protector circuit to avoid misdetection of overcurrent due to spike
current at irr or switching.
The non-sensitivity time synchronizes with the frequency of the CR for setting the chopping frequency. The
non-sensitivity time is set as follows :
Non-sensitivity time = 4 × CR cycle
The time required for the ISD to actually operate after the non-sensitivity time is as follows :
Minimum: 5 × CR cycle
Maximum: 8 × CR cycle
Therefore, from the time overcurrent flows to the output transistors to the time output halts is as follows.
Note that ideally, the operating time is the operating time when overcurrent flows. Depending on the output control
mode timing, the overcurrent protector circuit may not be triggered.
Therefore, to ensure safe operation, add a fuse to the VM power supply for protection.
The fuse capacity would vary according to the use conditions. However, select a fuse whose capacity avoids any
operating problems and does not exceed the power dissipation for the IC.
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2005-04-04
TB62202AFG
Application Operation Input Data (Example: 2-Phase Excitation Mode)
TORQUE TORQUE DECAY
0
1
B0
DECAY
B1
B0
B1
B2
B3 PHASE B DECAY A
DECAY
A0
A0
A1
A2
A3 PHASE A
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
2
1
1
1
0
1
1
1
1
0
1
0
1
1
1
1
1
3
1
1
1
0
1
1
1
1
0
1
0
1
1
1
1
0
4
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
0
Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.
For the input conditions, see page 9, Functions.
We recommend Mixed Decay mode (37.5%) as Decay mode. Set torque to 100%.
Output current waveform of 2-phase excitation sine wave
(%)
100
Phase B
0
Phase A
−100
Note: We recommended 2-phase excitation drive in 37.5% Mixed Decay mode.
Please refer to the caution of 2-phase excitation mode on next page.
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TB62202AFG
Application Operation Input Data (Example: 1-2 Phase Excitation Mode Typ.A)
TORQUE TORQUE DECAY
0
1
B0
DECAY
B1
B0
B1
B2
B3 PHASE B
DECAY
A0
DECAY
A1
A0
A1
A2
A3 PHASE A
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
2
1
1
1
0
1
0
0
0
1
1
0
1
1
1
1
1
3
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
4
1
1
1
0
1
1
1
1
0
1
0
1
0
0
0
0
5
1
1
1
0
1
1
1
1
0
1
0
1
1
1
1
0
6
1
1
1
0
1
0
0
0
0
1
0
1
1
1
1
0
7
1
1
1
0
1
1
1
1
0
1
0
1
1
1
1
0
8
1
1
1
0
1
1
1
1
1
1
0
1
0
0
0
1
Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.
For the input conditions, see page 10, Functions.
We recommend Mixed Decay Mode (37.5%) as Decay Mode.
Set torque to 100%.
When using this excitation mode, high efficiency can be achieved by setting the phase data to 10% (−10%). Set
current values in the order +100% → −10% → −100% → +10%.
Output Current Waveform of 1-2 Phase Excitation Sine Wave (Typ. A)
(%)
100
Phase A
10
0
−10
−100
(%)
100
Phase B
10
0
−10
−100
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2005-04-04
TB62202AFG
Points for Control that Includes Current of 0%
In modes other than 2-Phase Excitation mode (from 1-2 Phase Excitation mode to 4W1-2 Phase Excitation mode),
when the current is controlled to 0%, the TB62201F’s output transistors are all turned off.
At the time, the coil's energy returns to the power supply through the parasitic diodes. If the same current is
applied several times and is within the rated current, then : the power consumed by the on-resistance when current
flows to the output MOS will be less than the power consumed when current is applied to the parasitic diodes.
Therefore, when controlling the current, rather than setting 0%, set the current to the next step beyond 0% (the
minimum step in the reverse direction) for better power dissipation results.
However, if the 0% (actually 10%) current cycle is long, the power dissipation may be greater than in Off mode
because of the need for constant-current control.
Therefore, Toshiba recommend setting the current according to the actual operating pattern. (1-2 Phase Excitation
mode is the most effective.)
Flyback diode mode
Charge
[%]
100
Constantcurrent
control
RS pin
U2
OFF
U1
Output off
period
10
0
−10
To VM power supply
RRS
OFF
Load
L1
Constantcurrent
control
−100
The coil’s energy returns through
the parasitic diodes.
Because VDS < VF, the power
dissipation is large.
L2
OFF
OFF
Forced Off mode
Diode parasite
PGND
Non-flyback diode mode
Charge
[%]
100
To VM
RRS
Constantcurrent
control
RS pin
U2
OFF
U1
ON
10
0
−10
Constantcurrent
control
−100
Specifies a level of 10%,
either side of 0.
Constantcurrent
control
Load
OFF
L1
ON
The coil’s energy returns through
the MOS, which is turned on.
Then the coil is charged to a level
of 10%.
The power dissipation is smaller
than when the energy is returned
via the parasitic diode.
(However, the longer the ±10%
rated current control time, the
longer the period of current
dissipation.)
L2
Charge mode
Charge
PGND
71
2005-04-04
TB62202AFG
Application Operation Input Data (Example: 1-2 Phase Excitation mode Typ.B)
TORQUE TORQUE
MDMB
0
1
DECAY
B
B0
B1
B2
B3
PHASE
B
MDM A
DECAY
A
A0
A1
A2
A3
PHASE
A
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
1
1
1
0
1
1
1
1
1
1
0
0
0
0
0
1
2
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
3
1
1
1
0
0
0
0
0
1
1
0
1
1
1
1
1
4
1
1
1
0
0
0
0
1
0
1
0
0
0
0
1
1
5
1
1
1
0
1
1
1
1
0
1
0
0
0
0
0
0
6
1
1
1
0
0
0
0
1
0
1
0
0
0
0
1
0
7
1
1
1
0
0
0
0
0
0
1
0
1
1
1
1
0
Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.
For the input conditions, see page 10, Functions.
We recommend Mixed Decay Mode (37.5%) as Decay Mode.
Set torque to 100%. Same as 1-2 phase excitation (typ. A) in the previous section, power dissipation can be reduced
by changing 0% level to 10% or −10%.
Output Current Waveform of 1-2 Phase Excitation Sine Wave (Typ. B)
(%)
100
71
Phase A
0
Phase B
−71
−100
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2005-04-04
TB62202AFG
Application Operation Input Data (Example: 4-bit micro steps)
(4-bit micro steps = W1-2 phase excitation drive)
TORQUE TORQUE DECAY DECAY
0
1
B0
B1
B0
B1
B2
B3
PHASE DECAY DECAY
B
A0
A1
A0
A1
A2
A3
PHASE
A
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
1
1
1
0
1
1
1
1
1
1
0
0
0
0
0
1
2
1
1
1
0
0
0
1
1
1
1
0
0
0
1
0
1
3
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
4
1
1
1
0
0
0
1
0
1
1
0
0
0
1
1
1
5
1
1
1
0
0
0
0
0
1
1
0
1
1
1
1
1
6
1
1
1
0
0
0
0
0
0
1
0
1
1
1
1
1
7
1
1
1
0
0
0
1
0
0
1
0
0
0
1
1
1
8
1
1
1
0
0
0
0
1
0
1
0
0
0
0
1
1
9
1
1
1
0
0
0
1
1
0
1
0
0
0
1
0
1
10
1
1
1
0
1
1
1
1
0
1
0
0
0
0
0
1
11
1
1
1
0
1
1
1
1
0
1
1
0
0
0
0
0
12
1
1
1
0
0
0
1
1
0
1
1
0
0
1
0
0
13
1
1
1
0
0
0
0
1
0
1
1
0
0
0
1
0
14
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
15
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
16
1
1
1
0
0
0
0
0
1
1
0
1
1
1
1
0
17
1
1
1
0
0
0
1
0
1
1
0
0
0
1
1
0
18
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
0
19
1
1
1
0
0
0
1
1
1
1
0
0
0
1
0
0
20
1
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.
For the input conditions, see page 9, Functions.
We recommend Slow Decay Mode in the ascending direction of the sine wave ; Mixed Decay Mode (37.5%) in the
descending direction. Set torque to 100%.
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2005-04-04
TB62202AFG
Output Current Waveform of Pseudo Sine Wave (4-bit micro steps)
(%)
100
92
71
Phase A
38
0
Phase B
−38
−71
−92
−100
STEP
5 micro-step from 0 to 90° drive is possible by combining Current DATA (AB & CD) and phase data.
For input Current DATA at that time, see section on Current X in the list of the Functions.
Depending on the load, the optimum condition changes for selecting MIXED DECAY MODE when the sine wave
rises and falls. Select the appropriate MIXED DECAY TIMING according to the load.
74
2005-04-04
TB62202AFG
Application Operation Input Data (Example: 3-bit micro steps)
(3-bit micro steps = 2W1-2 phase excitation drive)
TORQUE TORQUE DECAY DECAY
0
1
B0
B1
B0
B1
B2
B3
PHASE
B
DECAY DECAY
A0
A1
A0
A1
A2
A3
PHASE
A
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
1
1
1
0
1
1
1
1
1
1
0
0
0
0
0
1
2
1
1
1
0
0
1
1
1
1
1
0
0
1
0
0
1
3
1
1
1
0
0
0
1
1
1
1
0
0
0
1
0
1
4
1
1
1
0
0
1
0
1
1
1
0
0
1
1
0
1
5
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
6
1
1
1
0
0
1
1
0
1
1
0
0
1
0
1
1
7
1
1
1
0
0
0
1
0
1
1
0
0
0
1
1
1
8
1
1
1
0
0
1
0
0
1
1
0
0
1
1
1
1
9
1
1
1
0
0
0
0
0
1
1
0
1
1
1
1
1
10
1
1
1
0
0
0
0
0
0
1
0
1
1
1
1
1
11
1
1
1
0
0
1
0
0
0
1
0
0
1
1
1
1
12
1
1
1
0
0
0
1
0
0
1
0
0
0
1
1
1
13
1
1
1
0
0
1
1
0
0
1
0
0
1
0
1
1
14
1
1
1
0
0
0
0
1
0
1
0
0
0
0
1
1
15
1
1
1
0
0
1
0
1
0
1
0
0
1
1
0
1
16
1
1
1
0
0
0
1
1
0
1
0
0
0
1
0
1
17
1
1
1
0
0
1
1
1
0
1
0
0
1
0
0
1
18
1
1
1
0
1
1
1
1
0
1
0
0
0
0
0
1
19
1
1
1
0
1
1
1
1
0
1
1
0
0
0
0
0
20
1
1
1
0
0
1
1
1
0
1
1
0
1
0
0
0
21
1
1
1
0
0
0
1
1
0
1
1
0
0
1
0
0
22
1
1
1
0
0
1
0
1
0
1
1
0
1
1
0
0
23
1
1
1
0
0
0
0
1
0
1
1
0
0
0
1
0
24
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
25
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
26
1
1
1
0
0
1
0
0
0
1
1
0
1
1
1
0
27
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
28
1
1
1
0
0
0
0
0
1
1
0
1
1
1
1
0
29
1
1
1
0
0
1
0
0
1
1
0
0
1
1
1
0
30
1
1
1
0
0
0
1
0
1
1
0
0
0
1
1
0
31
1
1
1
0
0
1
1
0
1
1
0
0
1
0
1
0
32
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
0
33
1
1
1
0
0
1
0
1
1
1
0
0
1
1
0
0
34
1
1
1
0
0
0
1
1
1
1
0
0
0
1
0
0
35
1
1
1
0
0
1
1
1
1
1
0
0
1
0
0
0
36
1
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.
For the input conditions, see page 10, Functions.
We recommend Slow Decay Mode in the ascending direction of the sine wave; Mixed Decay Mode (37.5%) in the
descending direction. Set torque to 100%.
75
2005-04-04
TB62202AFG
Output Current Waveform of Pseudo Sine Wave (3-bit micro steps)
[%]
100
98
92
83
71
Phase A
56
38
20
0
−20
Phase B
−38
−56
−71
−83
−92
−98
−100
STEP
9 micro-step from 0 to 90° drive is possible by combining Current DATA (AB & CD) and phase data.
For input Current DATA at that time, see section on Current X in the list of the Functions.
Depending on the load, the optimum condition changes for selecting MIXED DECAY MODE when the sine wave
rises and falls. Select the appropriate MIXED DECAY TIMING according to the load.
76
2005-04-04
TB62202AFG
Application Operation Input Data (Example: 4-bit micro steps)
TORQUE TORQUE DECAY DECAY
0
1
B0
B1
B0
B1
B2
B3
PHASE
B
DECAY DECAY
A0
A1
A0
A1
A2
A3
PHASE
A
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
1
1
1
0
1
1
1
1
1
1
0
0
0
0
0
1
2
1
1
1
0
1
1
1
1
1
1
0
1
0
0
0
1
3
1
1
1
0
0
1
1
1
1
1
0
0
1
0
0
1
4
1
1
1
0
1
0
1
1
1
1
0
1
1
0
0
1
5
1
1
1
0
0
0
1
1
1
1
0
0
0
1
0
1
6
1
1
1
0
1
1
0
1
1
1
0
1
0
1
0
1
7
1
1
1
0
0
1
0
1
1
1
0
0
1
1
0
1
8
1
1
1
0
1
0
0
1
1
1
0
1
1
1
0
1
9
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
10
1
1
1
0
1
1
1
0
1
1
0
1
0
0
1
1
11
1
1
1
0
0
1
1
0
1
1
0
0
1
0
1
1
12
1
1
1
0
1
0
1
0
1
1
0
1
1
0
1
1
13
1
1
1
0
0
0
1
0
1
1
0
0
0
1
1
1
14
1
1
1
0
1
1
0
0
1
1
0
1
0
1
1
1
15
1
1
1
0
0
1
0
0
1
1
0
0
1
1
1
1
16
1
1
1
0
1
0
0
0
1
1
0
1
1
1
1
1
17
1
1
1
0
0
0
0
0
1
1
0
1
1
1
1
1
18
1
1
1
0
0
0
0
0
0
1
0
1
1
1
1
1
19
1
1
1
0
1
0
0
0
0
1
0
1
1
1
1
1
20
1
1
1
0
0
1
0
0
0
1
0
0
1
1
1
1
21
1
1
1
0
1
1
0
0
0
1
0
1
0
1
1
1
22
1
1
1
0
0
0
1
0
0
1
0
0
0
1
1
1
23
1
1
1
0
1
0
1
0
0
1
0
1
1
0
1
1
24
1
1
1
0
0
1
1
0
0
1
0
0
1
0
1
1
25
1
1
1
0
1
1
1
0
0
1
0
1
0
0
1
1
26
1
1
1
0
0
0
0
1
0
1
0
0
0
0
1
1
27
1
1
1
0
1
0
0
1
0
1
0
1
1
1
0
1
28
1
1
1
0
0
1
0
1
0
1
0
0
1
1
0
1
29
1
1
1
0
1
1
0
1
0
1
0
1
0
1
0
1
30
1
1
1
0
0
0
1
1
0
1
0
0
0
1
0
1
31
1
1
1
0
1
0
1
1
0
1
0
1
1
0
0
1
32
1
1
1
0
0
1
1
1
0
1
0
0
1
0
0
1
33
1
1
1
0
1
1
1
1
0
1
0
1
0
0
0
1
34
1
1
1
0
1
1
1
1
0
1
0
0
0
0
0
1
77
2005-04-04
TB62202AFG
TORQUE TORQUE DECAY DECAY
0
1
B0
B1
B0
B1
B2
B3
PHASE
B
DECAY DECAY
A0
A1
A0
A1
A2
A3
PHASE
A
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
35
1
1
1
0
1
1
1
1
0
1
1
0
0
0
0
0
36
1
1
1
0
1
1
1
1
0
1
1
1
0
0
0
0
37
1
1
1
0
0
1
1
1
0
1
1
0
1
0
0
0
38
1
1
1
0
1
0
1
1
0
1
1
1
1
0
0
0
39
1
1
1
0
0
0
1
1
0
1
1
0
0
1
0
0
40
1
1
1
0
1
1
0
1
0
1
1
1
0
1
0
0
41
1
1
1
0
0
1
0
1
0
1
1
0
1
1
0
0
42
1
1
1
0
1
0
0
1
0
1
1
1
1
1
0
0
43
1
1
1
0
0
0
0
1
0
1
1
0
0
0
1
0
44
1
1
1
0
1
1
1
0
0
1
1
1
0
0
1
0
45
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
46
1
1
1
0
1
0
1
0
0
1
1
1
1
0
1
0
47
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
48
1
1
1
0
1
1
0
0
0
1
1
1
0
1
1
0
49
1
1
1
0
0
1
0
0
0
1
1
0
1
1
1
0
50
1
1
1
0
1
0
0
0
0
1
1
1
1
1
1
0
51
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
52
1
1
1
0
0
0
0
0
1
1
0
1
1
1
1
0
53
1
1
1
0
1
0
0
0
1
1
0
1
1
1
1
0
54
1
1
1
0
0
1
0
0
1
1
0
0
1
1
1
0
55
1
1
1
0
1
1
0
0
1
1
0
1
0
1
1
0
56
1
1
1
0
0
0
1
0
1
1
0
0
0
1
1
0
57
1
1
1
0
1
0
1
0
1
1
0
1
1
0
1
0
58
1
1
1
0
0
1
1
0
1
1
0
0
1
0
1
0
59
1
1
1
0
1
1
1
0
1
1
0
1
0
0
1
0
60
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
0
61
1
1
1
0
1
0
0
1
1
1
0
1
1
1
0
0
62
1
1
1
0
0
1
0
1
1
1
0
0
1
1
0
0
63
1
1
1
0
1
1
0
1
1
1
0
1
0
1
0
0
64
1
1
1
0
0
0
1
1
1
1
0
0
0
1
0
0
65
1
1
1
0
1
0
1
1
1
1
0
1
1
0
0
0
66
1
1
1
0
0
1
1
1
1
1
0
0
1
0
0
0
67
1
1
1
0
1
1
1
1
1
1
0
1
0
0
0
0
68
1
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.
For the input conditions, see page 10, Functions. In the above input data example, Decay mode has a Mixed Decay
mode (37.5%) setting for both the rising and falling directions of the sine wave, and a torque setting of 100%.
78
2005-04-04
TB62202AFG
4W1-2 Output Current Waveform of Pseudo Sine Wave (4-bit micro steps)
[%]
100
98
96
92
88
83
77
71
63
Phase A
56
47
38
29
20
10
0
−10
Phase B
−20
−29
−38
−47
−56
−63
−71
−77
−83
−88
−92
−96
−98
−100
STEP
17 micro-step from 0 to 90° drive is possible by combining Current DATA (AB & CD) and phase data.
For input Current DATA at that time, see section on Current X in the list of the Functions.
Depending on the load, the optimum condition changes for selecting MIXED DECAY MODE when the sine wave
rises and falls. Select the appropriate MIXED DECAY TIMING according to the load.
79
2005-04-04
TB62202AFG
Output Current Vector Line
4W-1-2 phase excitation (4-bit micro steps)
100
98
96
X = 16
X = 15
X = 14
X = 13
X = 12
92
X = 11
88
X = 10
83
X=9
77
X=8
71
X=7
63
X=6
(%)
56
X=5
IA
47
X=4
38
X=3
29
X=2
20
θX
X=1
10
θX
X=0
0
10
20
29
38
47
IB
56
63
71
77
83
88
92 96 98 100
(%)
For data to be input, see the function of Current AX (BX) in the list of Functions (10 page).
80
2005-04-04
TB62202AFG
Output Current Vector Line 2 (Each mode: except 4W1-2 phase)
1-2 phase excitation (Typ. A)
1-2 phase excitation (Typ. B)
IA (%)
100
IA (%)
100
0
100
0
71
IB (%)
100
IB (%)
W 1-2 phase excitation
2W 1-2 phase excitation
100
100
98
92
92
83
71
IA (%)
IA (%)
71
38
56
38
20
0
38
71
92 100
0
IB (%)
20
38
56
71
83
92 100
98
IB (%)
81
2005-04-04
TB62202AFG
Recommended Application Circuit
The values for the devices are all recommended values. For values under each input condition, see the
above-mentioned recommended operating conditions.
(Example : fchop = 96 kHz, CR : Iout = 0.6 (A), LF : Iout = 0.6 (A) )
Rosc = 2.0 kΩ
Vref AB
CR
Vref AB
Cosc = 1000 pF
SGND
2.63 V
1 µF
SGND
VM A
VDD
RRS A
5V
0V
STEPUP
5V
0V
CLK AB
5V
0V
DATA AB
5V
0V
STROBE AB
RRS A 0.75 Ω
A
A
B
STEPPING
M MOTOR 1
B
(CR: 6.8 mH/5.7 Ω)
RRS B
RRS B 0.75 Ω
VM B
P-GND
VSS
(FIN)
5V
0V
CLK CD
5V
0V
DATA CD
5V
0V
STROBE CD
C
5V
0V
RESET
C
SGND
VM C
RRS C
RRS C 0.75 Ω
D
STEPPING
M MOTOR 2
D
(LF: 6.8 mH/5.7 Ω)
RRS D
RRS D 0.75 Ω
VM D
Ccp A Ccp B
5V
SGND
Vref CD
Ccp C
100 µF
1 µF
4.13 V
Ccp 2
0.015 µF
Cop 1
0.22 µF
SGND
100 µF
24 V
SGND
Note: We recommend the user add bypass capacitors as required.
Make sure as much as possible that GND wiring has only one contact point.
Also, make sure that the VM pins are connected.
For the data to be input, see the section on the recommended input data.
Because there may be shorts between outputs, shorts to supply, or shorts to ground, be careful when designing
output lines, VDD (VM) lines, and GND lines.
82
2005-04-04
TB62202AFG
Package Dimensions
HSOP36-P-450-0.65
Unit: mm
Weight: 0.79 g (typ.)
83
2005-04-04
TB62202AFG
About solderability, following conditions were confirmed
• Solderability
(1) Use of Sn-63Pb solder Bath
· solder bath temperature = 230°C
· dipping time = 5 seconds
· the number of times = once
· use of R-type flux
(2) Use of Sn-3.0Ag-0.5Cu solder Bath
· solder bath temperature = 245°C
· dipping time = 5 seconds
· the number of times = once
· use of R-type flux
RESTRICTIONS ON PRODUCT USE
030619EBA
• The information contained herein is subject to change without notice.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
TOSHIBA or others.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced
and sold, under any law and regulations.
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2005-04-04