POWERINT DI-101

Design Idea DI-101
®
DPA-Switch Under-Voltage with
Wide Hysteresis
Application
Device
Power Output
Input Voltage
Output Voltage
Topology
PoE/VoIP
DPA423G
-
34-57 VDC
-
-
Design Highlights
• High hysteresis under-voltage lockout for Power over
Ethernet (PoE) Powered Devices (PDs)
• Turn-on threshold of 42 VDC and turn-off threshold of
34 VDC
• Compliance to PoE standard (IEEE 802.3af) over complete
voltage window ensures compatibility with PSE equipment.
Tested by University of New Hampshire Interoperability
Consortium (UNH-IOC)*
Wide Hysteresis Under-Voltage
The default under-voltage lockout and overvoltage shutdown
thresholds of the DPA-Switch are programmed with a single
resistor (RLS) connected from the positive input voltage
to the L-pin. The default overvoltage and under-voltage
thresholds have a fixed ratio (ratio approximately 2.7:1).
In a PoE system, the Power Sourcing Equipment (PSE)
provides a minimum operating voltage of 44 VDC.
However, the PoE specification allows CAT-5 (Ethernet)
cable lengths up to 100 meters/ 300 ft (with up to
20 Ω of cable impedance). At peak operating current
(350 mA), the voltage at the PD can drop to approximately
+
R3
174 kΩ
1%
L
CONTROL
-
This circuit takes advantage of accurate DPA-Switch L-pin
current sensing as the basis for a new composite threshold,
programmed for 42 VDC turn-on and 34 VDC turn-off.
The DPA-Switch detects the input voltage via current in the
L-pin resistor RLS. Above an UV-on threshold (50 µA), the
DPA-Switch begins switching and below an UV-off threshold
(47 µA), the DPA-Switch is disabled. Transistor Q1 is turned
on via bias resistor R2, causing a voltage drop across R3 and
subtracting a fixed current of approximately 10 µA (moving the
effective threshold to 60 µA) from the L-pin. When the power
supply becomes operational, the bias voltage pulls up via R1,
turning off Q1, cutting off the R3 current and returning to the
default UV-off threshold (47 µA).
ON
IUV(ON)
IOV(OFF)
RLS Only
+
DC Input
Voltage
DPA-Switch
Operation
OFF
RLS
649 kΩ
1%
D
37 VDC (350 mA × 20 Ω). A minimum of 7 VDC undervoltage hysteresis is required to accommodate the cable drop
voltage and prevent nuisance lockouts from occurring.
Bias
Voltage
25
50
75
47 µA
R1
10 kΩ
Q1
MMST3906
C
0
100
125
131 µA
PI-4064-111005
IL
135 µA
ON
10 µA
RLS with
Q1 Circuit
R2
10 kΩ
S
150
OFF
0
25
Figure 1. DPA-Switch with Wide Hysteresis UVLO.
50
60 µA
75
100
L Pin Current (µA)
125
150
IL
PI-4068-111005
Figure 2. L-Pin Current without/with Wide UVLO Circuit.
*UNH-IOC test reports are available on the PI website www.powerint.com/poe
DI-101
www.powerint.com
November 2005
DI-101
Design Formulae
Component values can be calculated according to the following
formulae and parameters:
Design parameters were selected as follows:
VUV_ON = 42 VDC
VUV_OFF = 34 VDC
VDIN = 1.4 VDC
R1 = 10 kΩ
Input under-voltage on-threshold
Default under-voltage offthreshold
Diode drop for PoE reverse
protection input diodes
This value is assumed
β = 100
V $R
VQ1(BE)REV = RBIAS+ R 2 - VL
1
2
•
Transistor base-emitter voltage
80% of the max reverse baseemitter voltage
Transistor minimum current gain
•
•
Resistor values RLS, R2 and R3 are calculated as follows:
RLS =
VOV_OFF = IOV_OFF $ RLS + VL + VDIN
•
Bias Voltage (VBIAS) = 8 VDC
VL - VQ1(BE)
m $ RLS + VL + VDIN
R3
VUV_OFF = IUV_OFF $ RLS + VL + VDIN
•
L-pin current for UV turn on
L-pin current for UV turn off
L-pin voltage at IL = IUV_ON
Control-pin voltage
We can assume:
VQ1(BE) = 0.6 VDC
VQ1(BE)REV < 4 VDC
VUV_ON = c IUV_ON +
Key Design Points
From the DPA-Switch data sheet we have the following:
IUV_ON = 50 µA
IUV_OFF = 47 µA
VL = 2.35 VDC
VC = 5.8 VDC
For design verification:
Use a 1% resistor for RLS to maintain the highest accuracy
for the turn-on/turn-off thresholds.
The over-voltage threshold is fixed at IOV_OFF = 135 µA,
and can be calculated according to the formula above
(VOV_OFF).
The bias voltage (VBIAS) is divided by R2 and R1. The
reverse base emitter voltage VQ1(BE)REV is the divided
bias voltage minus VL. Make sure VQ1(BE)REV stays below
5 V (the transistor rating).
For PoE applications, make sure to include voltage drops
of input diodes (VDIN) and pass-FET drop when calculating
RLS. For non-PoE applications, assume VDIN = 0.
Note: Due to the L-pin synchronization function (with a
1 V threshold), resistor R2 should be sufficiently large to
prevent Q1 turn-on below L-pin voltage 1 V.
VUV_OFF - VL - VDIN
IUV_OFF
^VL - VQ1(BE)h $ RLS
R3 = V
IUV_ON $ RLS - VL - VDIN
UV_ON
R1 $ ^VQ1(BE)REV + VLh
R2 1 V - V - V
BIAS
L
Q1 (BE) REV
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©Copyright 2005, Power Integrations, Inc.
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