MAXIM MAX1021

19-4009; Rev 1; 3/08
KIT
ATION
EVALU
E
L
B
AVAILA
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Features
The MAX1021/MAX1043 integrate a multichannel, 10-bit,
analog-to-digital converter (ADC) and a 10-bit, digital-toanalog converter (DAC) in a single IC. The devices also
include a temperature sensor and configurable generalpurpose I/O ports (GPIOs) with a 25MHz SPI™-/QSPI™-/
MICROWIRE™-compatible serial interface. The ADC is
available in an eight input-channel version. The DAC outputs settle within 2.0µs, and the ADC has a 225ksps conversion rate.
All devices include an internal reference (2.5V) to provide
a well-regulated, low-noise reference for both the ADC
and DAC. Programmable reference modes for the ADC
and DAC allow the use of an internal reference, an external reference, or a combination of both. Features such as
an internal ±1°C accurate temperature sensor, FIFO,
scan modes, programmable internal or external clock
modes, data averaging, and AutoShutdown™ allow users
to minimize both power consumption and processor
requirements. The low glitch energy (4nV•s) and low digital feedthrough (0.5nV•s) of the integrated DACs make
these devices ideal for digital control of fast-response
closed-loop systems.
The devices are guaranteed to operate with a supply voltage from +2.7V to +5.25V. They consume 2.5mA at
225ksps throughput, only 22µA at 1ksps throughput, and
under 0.2µA in the shutdown mode. The MAX1021/
MAX1043 offer four GPIOs that can be configured as
inputs or outputs.
The MAX1021/MAX1043 are available in 36-pin thin QFN
packages. These devices are specified over the -40°C to
+85°C temperature range.
♦ 10-Bit, 225ksps ADC
Analog Multiplexer with True-Differential
Track/Hold (T/H)
Eight Single-Ended Channels or Four
Differential
Channels (Unipolar or Bipolar)
Excellent Accuracy: ±0.5 LSB INL, ±0.5 LSB
DNL, No Missing Codes Over Temperature
♦ 10-Bit, Octal, 2µs Settling DAC (MAX1021)
Ultra-Low-Glitch Energy (4nV•s)
Power-Up Options from Zero Scale or Full Scale
Excellent Accuracy: ±0.5 LSB INL
♦ Internal Reference or External Single-Ended/
Differential Reference
Internal Reference Voltage (2.5V)
♦ Internal ±1°C Accurate Temperature Sensor
♦ On-Chip FIFO Capable of Storing 16 ADC
Conversion Results and One Temperature Result
♦ On-Chip Channel-Scan Mode and Internal
Data-Averaging Features
♦ Analog Single-Supply Operation
+2.7V to +5.25V
♦ Digital Supply: +2.7V to AVDD
♦ 25MHz, SPI/QSPI/MICROWIRE Serial Interface
♦ AutoShutdown Between Conversions
♦ Low-Power ADC
2.5mA at 225ksps
22µA at 1ksps
0.2µA at Shutdown
♦ Low-Power DAC: 1.5mA
♦ Evaluation Kit Available (Order MAX1258EVKIT)
Applications
Closed-Loop Controls for Optical Components
and Base Stations
System Supervision and Control
Data-Acquisition Systems
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
Pin Configurations appear at end of data sheet.
Ordering Information/Selector Guide
PART
PIN-PACKAGE
REF
ANALOG SUPPLY RESOLUTION
ADC
VOLTAGE (V)
VOLTAGE (V)
BITS**
CHANNELS
DAC
CHANNELS
GPIOs
MAX1021BETX
36 Thin QFN-EP*
2.5
2.7 to 5.25
10
8
8
4
MAX1043BETX
36 Thin QFN-EP*
2.5
2.7 to 5.25
10
8
4
4
Note: All devices are specified over the -40°C to +85°C operating temperature range.
*EP = Exposed pad.
**Number of resolution bits refers to both DAC and ADC.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX1021/MAX1043
General Description
MAX1021/MAX1043
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ABSOLUTE MAXIMUM RATINGS
Maximum Current into OUT_.............................................100mA
Continuous Power Dissipation (TA = +70°C)
36-Pin Thin QFN (6mm x 6mm)
(derate 26.3mW/°C above +70°C) ..........................2105.3mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
AVDD to AGND .........................................................-0.3V to +6V
DGND to AGND.....................................................-0.3V to +0.3V
DVDD to AVDD .......................................................-3.0V to +0.3V
Digital Inputs to DGND.............................................-0.3V to +6V
Digital Outputs to DGND .........................-0.3V to (DVDD + 0.3V)
Analog Inputs, Analog Outputs and REF_
to AGND...............................................-0.3V to (AVDD + 0.3V)
Maximum Current into Any Pin (except AGND, DGND, AVDD,
DVDD, and OUT_) ...........................................................50mA
Note: If the package power dissipation is not exceeded, one output at a time can be shorted to AVDD, DVDD, AGND, or DGND
indefinitely.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = 2.7V to 5.25V, external reference VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless
otherwise noted. Typical values are at AVDD = DVDD = 3V, TA = +25°C. Outputs are unloaded, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ADC
DC ACCURACY (Note 1)
Resolution
10
Bits
Integral Nonlinearity
INL
±0.5
±1.0
LSB
Differential Nonlinearity
DNL
±0.5
±1
LSB
Offset Error
Gain Error
(Note 2)
±0.25
±2.0
LSB
±0.025
±2.0
LSB
Gain Temperature Coefficient
±1.4
ppm/°C
Channel-to-Channel Offset
±0.1
LSB
SINAD
61
dB
Total Harmonic Distortion
(Up to the Fifth Harmonic)
THD
-70
dBc
Spurious-Free Dynamic Range
SFDR
66
dBc
dBc
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, VIN = 2.5VP-P, 225ksps, fCLK = 3.6MHz)
Signal-to-Noise Plus Distortion
Intermodulation Distortion
fIN1 = 9.9kHz, fIN2 = 10.2kHz
72
Full-Linear Bandwidth
IMD
SINAD > 70dB
100
kHz
Full-Power Bandwidth
-3dB point
1
MHz
External reference
0.8
µs
Internal reference (Note 4)
218
Conversion
clock
cycles
CONVERSION RATE (Note 3)
Power-Up Time
2
tPU
_______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
(AVDD = DVDD = 2.7V to 5.25V, external reference VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless
otherwise noted. Typical values are at AVDD = DVDD = 3V, TA = +25°C. Outputs are unloaded, unless otherwise noted.)
PARAMETER
SYMBOL
Acquisition Time
tACQ
Conversion Time
tCONV
External Clock Frequency
fCLK
CONDITIONS
(Note 5)
MIN
TYP
MAX
0.6
Internally clocked
µs
5.5
µs
Externally clocked
3.6
Externally clocked conversion (Note 5)
0.1
3.6
40
60
Duty Cycle
UNITS
MHz
%
Aperture Delay
30
ns
Aperture Jitter
< 50
ps
ANALOG INPUTS
Unipolar
Input Voltage Range (Note 6)
Bipolar
0
VREF
-VREF / 2
+VREF / 2
Input Leakage Current
±0.01
Input Capacitance
±1
24
V
µA
pF
INTERNAL TEMPERATURE SENSOR
Measurement Error (Notes 5, 7)
TA = +25°C
±0.7
TA = TMIN to TMAX
±1.0
Temperature Resolution
±3.0
1/8
°C
°C/LSB
INTERNAL REFERENCE
REF1 Output Voltage
REF1 Voltage Temperature
Coefficient
(Note 8)
2.482
2.518
±30
TCREF
REF1 Output Impedance
REF1 Short-Circuit Current
2.50
VREF = 2.5V
V
ppm/°C
6.5
kΩ
0.39
mA
EXTERNAL REFERENCE
REF1 Input Voltage Range
VREF1
REF2 Input Voltage Range
(Note 4)
VREF2
REF1 Input Current (Note 9)
IREF1
REF2 Input Current
IREF2
REF mode 11 (Note 4)
1
AVDD +
0.05
REF mode 01
1
AVDD +
0.05
REF mode 11
0
1
VREF = 2.5V, fSAMPLE = 225ksps
25
80
Acquisition between conversions
±0.01
±1
VREF = 2.5V, fSAMPLE = 225ksps
25
80
Acquisition between conversions
±0.01
±1
V
V
µA
µA
_______________________________________________________________________________________
3
MAX1021/MAX1043
ELECTRICAL CHARACTERISTICS (continued)
MAX1021/MAX1043
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = 2.7V to 5.25V, external reference VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless
otherwise noted. Typical values are at AVDD = DVDD = 3V, TA = +25°C. Outputs are unloaded, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
±0.5
±1
LSB
±0.5
LSB
±10
mV
DAC
DC ACCURACY (Note 10)
Resolution
10
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
Offset Error
VOS
Guaranteed monotonic
±3
Offset-Error Drift
Gain Error
Bits
ppm of
FS/°C
±10
GE
±1.25
Gain Temperature Coefficient
±10
LSB
ppm of
FS/°C
±8
DAC OUTPUT
No load
0.02
AVDD 0.02
0.1
AVDD 0.1
Output Voltage Range
V
10kΩ load to either rail
DC Output Impedance
Resistive Load to AGND
Ω
0.5
Capacitive Load
(Note 11)
RL
AVDD = 2.7V, VREF = 2.5V, gain error < 1%
1
nF
Ω
2000
From power-down mode, AVDD = 5V
25
From power-down mode, AVDD = 2.7V
21
1kΩ Output Termination
Programmed in power-down mode
1
kΩ
100kΩ Output Termination
At wake-up or programmed in
power-down mode
100
kΩ
Wake-Up Time (Note 12)
µs
DYNAMIC PERFORMANCE (Notes 5, 13)
Output-Voltage Slew Rate
SR
Positive and negative
Output-Voltage Settling Time
tS
To 1 LSB, 400 - C00 hex (Note 7)
Digital Feedthrough
Code 0, all digital inputs from 0 to DVDD
Major Code Transition Glitch
Impulse
Between codes 2047 and 2048
Output Noise (0.1Hz to 50MHz)
Output Noise (0.1Hz to 500kHz)
DAC-to-DAC Transition
Crosstalk
4
3
V/µs
2
5
µs
0.5
nV•s
4
nV•s
From VREF
660
Using internal reference
720
From VREF
260
Using internal reference
320
0.5
_______________________________________________________________________________________
µVP-P
µVP-P
nV•s
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
(AVDD = DVDD = 2.7V to 5.25V, external reference VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless
otherwise noted. Typical values are at AVDD = DVDD = 3V, TA = +25°C. Outputs are unloaded, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
2.482
2.50
2.518
UNITS
INTERNAL REFERENCE
REF1 Output Voltage
REF1 Temperature Coefficient
TCREF
REF1 Short-Circuit Current
VREF = 2.5V
V
±30
ppm/°C
0.39
mA
EXTERNAL REFERENCE INPUT
REF1 Input Voltage Range
VREF1
REF1 Input Impedance
RREF1
REF modes 01, 10, and 11 (Note 4)
0.7
70
100
AVDD
V
130
kΩ
DIGITAL INTERFACE
DIGITAL INPUTS (SCLK, DIN, CS, CNVST, LDAC)
Input-Voltage High
VIH
Input-Voltage Low
VIL
Input Leakage Current
Input Capacitance
DVDD = 2.7V to 5.25V
2.4
V
DVDD = 3.6V to 5.25V
0.8
DVDD = 2.7V to 3.6V
0.6
IL
0.01
CIN
15
±10
V
µA
pF
DIGITAL OUTPUT (DOUT) (Note 14)
Output-Voltage Low
VOL
ISINK = 2mA
Output-Voltage High
VOH
ISOURCE = 2mA
0.4
DVDD 0.5
V
Tri-State Leakage Current
Tri-State Output Capacitance
±10
COUT
V
15
µA
pF
DIGITAL OUTPUT (EOC) (Note 14)
Output-Voltage Low
VOL
Output-Voltage High
VOH
ISINK = 2mA
ISOURCE = 2mA
0.4
DVDD 0.5
V
Tri-State Leakage Current
Tri-State Output Capacitance
±10
COUT
V
15
µA
pF
DIGITAL OUTPUTS (GPIO_) (Note 14)
GPIOC_ Output-Voltage Low
ISINK = 2mA
0.4
ISINK = 4mA
0.8
GPIOC_ Output-Voltage High
ISOURCE = 2mA
GPIOA_ Output-Voltage Low
ISINK = 15mA
GPIOA_ Output-Voltage High
ISOURCE = 15mA
DVDD 0.5
V
0.8
DVDD 0.8
±10
COUT
V
V
Tri-State Leakage Current
Tri-State Output Capacitance
V
15
µA
pF
_______________________________________________________________________________________
5
MAX1021/MAX1043
ELECTRICAL CHARACTERISTICS (continued)
MAX1021/MAX1043
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = 2.7V to 5.25V, external reference VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless
otherwise noted. Typical values are at AVDD = DVDD = 3V, TA = +25°C. Outputs are unloaded, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
AVDD
V
POWER REQUIREMENTS (Note 15)
Digital Positive-Supply Voltage
DVDD
Digital Positive-Supply Current
DIDD
Analog Positive-Supply Voltage
AVDD
2.7
Idle, all blocks shut down
0.2
Only ADC on, external reference
4
1
2.70
Idle, all blocks shut down
µA
mA
5.25
V
µA
0.2
2
fSAMPLE = 225ksps
2.8
4.2
fSAMPLE = 100ksps
2.6
Analog Positive-Supply Current
AIDD
Only ADC on,
external reference
All DACs on, no load, internal reference
1.5
REF1 Positive-Supply Rejection
PSRR
AVDD = 2.7V
-77
DAC Positive-Supply Rejection
PSRD
Output
AVDD = 2.7V to 5.25V
code =
FFFhex
±0.1
±0.5
mV
ADC Positive-Supply Rejection
PSRA
Fullscale
input
±0.06
±0.5
mV
AVDD = 2.7V to 5.25V
mA
4.0
dB
TIMING CHARACTERISTICS (Figures 6–13)
SCLK Clock Period
tCP
40
ns
SCLK Pulse-Width High
tCH
40/60 duty cycle
16
ns
SCLK Pulse-Width Low
tCL
60/40 duty cycle
16
ns
GPIO Output Rise/Fall After
CS Rise
GPIO Input Setup Before CS Fall
LDAC Pulse Width
tGOD
CLOAD = 20pF
100
tGSU
0
tLDACPWL
20
ns
ns
ns
CLOAD = 20pF, SLOW = 0
1.8
12.0
CLOAD = 20pF, SLOW = 1
10
40
CLOAD = 20pF, SLOW = 0
1.8
12.0
CLOAD = 20pF, SLOW = 1
10
40
SCLK Fall to DOUT Transition
(Note 16)
tDOT
SCLK Rise to DOUT Transition
(Notes 16, 17)
tDOT
CS Fall to SCLK Fall Setup Time
tCSS
10
SCLK Fall to CS Rise Setup
Time
tCSH
0
DIN to SCLK Fall Setup Time
tDS
10
ns
DIN to SCLK Fall Hold Time
tDH
0
ns
tCSPWH
50
ns
CS Pulse-Width High
CS Rise to DOUT Disable
tDOD
CLOAD = 20pF
CS Fall to DOUT Enable
tDOE
CLOAD = 20pF
EOC Fall to CS Fall
tRDS
6
30
_______________________________________________________________________________________
ns
ns
2000
25
1.5
ns
25.0
ns
ns
ns
ns
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
(AVDD = DVDD = 2.7V to 5.25V, external reference VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless
otherwise noted. Typical values are at AVDD = DVDD = 3V, TA = +25°C. Outputs are unloaded, unless otherwise noted.)
PARAMETER
CS or CNVST Rise to EOC
Fall—Internally Clocked
Conversion Time
CNVST Pulse Width
SYMBOL
tDOV
tCSW
CONDITIONS
MIN
TYP
MAX
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference on
65
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference
initially off
140
CKSEL = 01 (voltage conversion)
9
CKSEL = 10 (voltage conversion),
internal reference on
9
CKSEL = 10 (voltage conversion),
internal reference initially off
80
UNITS
µs
CKSEL = 00, CKSEL = 01 (temp sense)
40
ns
CKSEL = 01 (voltage conversion)
1.4
µs
Note 1: Tested at DVDD = AVDD = 2.7V.
Note 2: Offset nulled.
Note 3: No bus activity during conversion. Conversion time is defined as the number of conversion clock cycles multiplied by the
clock period.
Note 4: See Table 5 for reference-mode details.
Note 5: Not production tested. Guaranteed by design.
Note 6: See the ADC/DAC References section.
Note 7: Fast automated test, excludes self-heating effects.
Note 8: Specified over the -40°C to +85°C temperature range.
Note 9: REFSEL[1:0] = 00 or when DACs are not powered up.
Note 10: DAC linearity, gain, and offset measurements are made between codes 115 and 3981.
Note 11: The DAC buffers are guaranteed by design to be stable with a 1nF load.
Note 12: Time required by the DAC output to power up and settle within 1 LSB in the external reference mode.
Note 13: All DAC dynamic specifications are valid for a load of 100pF and 10kΩ.
Note 14: Only one digital output (either DOUT, EOC, or the GPIOs) can be indefinitely shorted to either supply at one time.
Note 15: All digital inputs at either DVDD or DGND. DVDD should not exceed AVDD.
Note 16: See the Reset Register section and Table 9 for details on programming the SLOW bit.
Note 17: Clock mode 11 only.
_______________________________________________________________________________________
7
MAX1021/MAX1043
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(AVDD = DVDD = 3V, external VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at
REF, TA = +25°C, unless otherwise noted.)
0.3
0.2
0.1
0
3.0
3.5
4.0
4.5
5.0
0.2
0.1
MAX1040 toc03
0.1
0
-0.1
-0.2
-0.3
-40
5.5
-15
10
35
60
85
0
256
512
1024
768
TEMPERATURE (°C)
OUTPUT CODE
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
0
-0.1
-0.2
0.2
0.1
0
-0.1
-0.2
0.3
0
256
512
0
1024
768
0.2
0.1
0
-0.1
-0.2
-0.3
-0.3
-0.3
MAX1040 toc06
MAX1040 toc05
AVDD = DVDD = 5V
EXTERNAL REFERENCE = 4.096V
DIFFERENTIAL NONLINEARITY (LSB)
0.1
0.3
DIFFERENTIAL NONLINEARITY (LSB)
MAX1040 toc04
0.2
256
512
768
0
1024
256
512
1024
768
OUTPUT CODE
OUTPUT CODE
OUTPUT CODE
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
ADC OFFSET ERROR
vs. TEMPERATURE
ADC GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
0.3
0.2
0
0
-0.50
-1.0
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
5.5
0
-0.25
-0.5
0.1
MAX1021 toc09
0.25
0.5
GAIN ERROR (LSB)
OFFSET ERROR (LSB)
0.4
0.50
MAX1021 toc08
1.0
MAX1021 toc07
0.5
2.5
AVDD = DVDD = 5V
EXTERNAL REFERENCE = 4.096V
0.2
SUPPLY VOLTAGE (V)
0.3
INTEGRAL NONLINEARITY (LSB)
0.3
0.3
0
2.5
8
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX1021 toc02
0.4
0.4
ANALOG SHUTDOWN CURRENT (μA)
MAX1021 toc01
ANALOG SHUTDOWN CURRENT (μA)
0.5
ANALOG SHUTDOWN CURRENT
vs. TEMPERATURE
INTEGRAL NONLINEARITY (LSB)
ANALOG SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
OFFSET ERROR (LSB)
MAX1021/MAX1043
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
-40
-15
10
35
TEMPERATURE (°C)
60
85
2.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
5.0
5.5
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ADC GAIN ERROR
vs. TEMPERATURE
-0.5
-1.0
-15
10
35
60
20
10
0.5
0
50
100
150
200
250
0
300
50
100
150
200
250
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
DAC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
1.94
1.92
2.00
1.98
1.96
1.94
1.92
AVDD = DVDD = 3V
0.3
1.88
3.0
3.5
4.0
4.5
5.0
5.5
0.1
0
-0.1
-0.2
1.90
1.90
AVDD = DVDD = 5V
EXTERNAL REFERENCE = 4.096V
0.2
-0.3
-40
-15
10
35
60
85
0
256
512
768
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
OUTPUT CODE
DAC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
DAC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
DAC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
0
-0.1
-0.2
0.05
0
-0.05
256
512
OUTPUT CODE
768
1024
0.05
0
-0.05
-0.10
-0.10
-0.3
0.10
1024
MAX1040 toc18
AVDD = DVDD = 5V
EXTERNAL REFERENCE = 4.096V
DIFFERENTIAL NONLINEARITY (LSB)
0.1
MAX1040 toc17
0.2
0.10
DIFFERENTIAL NONLINEARITY (LSB)
MAX1040 toc16
0.3
300
MAX1040 toc15
AVDD = DVDD = 5V
INTEGRAL NONLINEARITY (LSB)
1.96
2.02
MAX1021 toc14
MAX1021 toc13
1.98
0
1.0
SAMPLING RATE (ksps)
2.00
2.5
1.5
0
0
85
MAX1040 toc12
MAX1040 toc11
30
2.0
SAMPLING RATE (ksps)
2.02
SUPPLY CURRENT (mA)
40
2.5
TEMPERATURE (°C)
2.04
INTEGRAL NONLINEARITY (LSB)
50
3.0
ANALOG SUPPLY CURRENT (mA)
0
60
ANALOG SUPPLY CURRENT (mA)
GAIN ERROR (LSB)
0.5
ADC EXTERNAL REFERENCE INPUT CURRENT (μA)
MAX1021 toc10
1.0
-40
ANALOG SUPPLY CURRENT
vs. SAMPLING RATE
ADC EXTERNAL REFERENCE
INPUT CURRENT vs. SAMPLING RATE
1023
1026
1029
1032
OUTPUT CODE
1035
1038
1023
1026
1029
1032
1035
1038
OUTPUT CODE
_______________________________________________________________________________________
9
MAX1021/MAX1043
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V, external VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at
REF, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V, external VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at
REF, TA = +25°C, unless otherwise noted.)
0.2
0.1
MAX1021 toc20
2
1
0
EXTERNAL
REFERENCE = 4.096V
-1
3
DAC FULL-SCALE ERROR (LSB)
0.3
3
DAC FULL-SCALE ERROR (LSB)
MAX1021 toc19
0.4
DAC FULL-SCALE ERROR (LSB)
DAC FULL-SCALE ERROR
vs. TEMPERATURE
DAC FULL-SCALE ERROR
vs. TEMPERATURE
INTERNAL
REFERENCE
2
1
0
EXTERNAL
REFERENCE = 2.5V
-1
-2
-2
AVDD = DVDD = 3V
AVDD = DVDD = 5V
3.0
3.5
4.0
4.5
5.0
5.5
-15
10
35
60
-40
85
35
60
DAC FULL-SCALE ERROR
vs. REFERENCE VOLTAGE
DAC FULL-SCALE ERROR
vs. REFERENCE VOLTAGE
DAC FULL-SCALE ERROR
vs. LOAD CURRENT
0.25
0
-0.25
-0.50
-1.0
-1.5
-2.0
-2.5
-0.75
1
2
3
4
5
0
-1
-2
-3
AVDD = DVDD = 5V
EXTERNAL REFERENCE = 4.096V
-4
-3.0
-1.00
0
0.5
1.0
1.5
2.0
2.5
0
3.0
5
10
15
20
25
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
LOAD CURRENT (mA)
DAC FULL-SCALE ERROR
vs. LOAD CURRENT
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
ADC REFERENCE SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
-2
-3
-4
2.51
2.50
2.49
1.0
1.5
2.0
LOAD CURRENT (mA)
2.5
3.0
MAX1021 toc27
30
25.0
24.9
24.8
24.7
2.48
0.5
25.1
ADC REFERENCE SUPPLY CURRENT (μA)
-1
MAX1021 toc26
0
2.52
INTERNAL REFERENCE VOLTAGE (V)
MAX1040 toc25
1
85
MAX1040 toc24
-0.5
1
DAC FULL-SCALE ERROR (LSB)
0.50
0
MAX1040 toc23
MAX1040 toc22
0.75
0
10
TEMPERATURE (°C)
AVDD = DVDD = 5V
0
-15
TEMPERATURE (°C)
1.00
DAC FULL-SCALE ERROR (LSB)
-40
SUPPLY VOLTAGE (V)
DAC FULL-SCALE ERROR (LSB)
2.5
10
-3
-3
0
MAX1021 toc21
DAC FULL-SCALE ERROR
vs. ANALOG SUPPLY VOLTAGE
DAC FULL-SCALE ERROR (LSB)
MAX1021/MAX1043
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
-40
-15
10
35
TEMPERATURE (°C)
60
85
2.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
______________________________________________________________________________________
5.0
5.5
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ADC REFERENCE SUPPLY CURRENT
vs. TEMPERATURE
40.7
40.6
AVDD = DVDD = 5V
EXTERNAL REFERENCE = 4.096V
-60
-80
-100
-120
24.8
AVDD = DVDD = 3V
-140
60
-160
-40
85
-15
10
35
60
0
85
ADC IMD PLOT
ADC CROSSTALK PLOT
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
-20
AMPLITUDE (dB)
-80
-100
-60
-80
-100
2.06
2.05
2.04
2.03
-120
-140
-140
2.01
-160
-160
2.00
200
150
AVDD = DVDD = 5V
EXTERNAL REFERENCE = 4.096V
2.07
-120
100
SINKING
SOURCING
2.02
DAC OUTPUT = MIDSCALE
0
50
100
150
200
-30
0
30
90
60
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
OUTPUT CURRENT (mA)
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
GPIO OUTPUT VOLTAGE
vs. SOURCE CURRENT
GPIO OUTPUT VOLTAGE
vs. SOURCE CURRENT
1.27
1.26
1.25
1.24
SINKING
1.23
SOURCING
4
GPIOA0, GPIOA1 OUTPUTS
3
2
GPIOC0, GPIOC1 OUTPUTS
1
AVDD = DVDD = 5V
EXTERNAL REFERENCE = 4.096V
DAC OUTPUT = MIDSCALE
0
-20
0
10
-10
OUTPUT CURRENT (mA)
20
30
GPIOA0, GPIOA1 OUTPUTS
2.5
2.0
GPIOC0,
GPIOC1 OUTPUTS
1.5
1.0
0.5
1.22
1.21
3.0
GPIO OUTPUT VOLTAGE (V)
GPIO OUTPUT VOLTAGE (V)
1.28
MAX1040 toc35
5
MAX1040 toc34
1.29
200
2.08
DAC OUTPUT VOLTAGE (V)
fCLK = 5.24288MHz
fIN1 = 10.080kHz
fIN2 = 8.0801kHz
SNR = 61.11dBc
THD = 73.32dBc
ENOB = 9.86 BITS
SFDR = 86.34dBc
MAX1040 toc32
MAX1040 toc31
0
-40
-60
-30
150
ANALOG INPUT FREQUENCY (kHz)
-40
50
100
TEMPERATURE (°C)
fCLK = 5.24288MHz
fIN1 = 9.0kHz
fIN2 = 11.0kHz
AIN = -6dBFS
IMD = 78.0dBc
0
50
TEMPERATURE (°C)
MAX1040 toc33
35
MAX1040 toc36
10
-20
AMPLITUDE (dB)
24.9
24.7
-15
0
DAC OUTPUT VOLTAGE (V)
-40
25.0
EXTERNAL REFERENCE = 2.5V
40.5
-40
fSAMPLE = 32.768kHz
fANALOG_)N = 10.080kHz
fCLK = 5.24288MHz
SINAD = 61.21dBc
SNR = 61.21dBc
THD = 73.32dBc
SFDR = 81.25dBc
-20
AMPLITUDE (dB)
40.8
0
MAX1021 toc29
40.9
ADC FFT PLOT
25.1
ADC REFERENCE SUPPLY CURRENT (μA)
MAX1021 toc28
ADC REFERENCE SUPPLY CURRENT (μA)
41.0
MAX1040 toc30
ADC REFERENCE SUPPLY CURRENT
vs. TEMPERATURE
0
20
40
60
SOURCE CURRENT (mA)
80
100
0
0
20
40
60
80
100
SOURCE CURRENT (mA)
______________________________________________________________________________________
11
MAX1021/MAX1043
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V, external VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at
REF, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V, external VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at
REF, TA = +25°C, unless otherwise noted.)
GPIO OUTPUT VOLTAGE
vs. SINK CURRENT
GPIO OUTPUT VOLTAGE
vs. SINK CURRENT
600
GPIOA0, GPIOA1 OUTPUTS
300
1200
900
600
GPIOA0, GPIOA1
OUTPUTS
300
0
0
20
40
60
80
100
SINK CURRENT (mA)
0.50
0.25
0
-0.25
-0.50
-1.00
0
10
20
30
40
50
60
SINK CURRENT (mA)
-40
-15
10
35
85
DYNAMIC RESPONSE RISE TIME
(RLOAD = 10kΩ, CLOAD = 100pF)
MAX1040 toc42
MAX1040 toc41
MAX1040 toc40
60
TEMPERATURE (°C)
DAC-TO-DAC CROSSTALK
(RLOAD = 10kΩ, CLOAD = 100pF)
DAC-TO-DAC CROSSTALK
(RLOAD = 10kΩ, CLOAD = 100pF)
VOUTA
1V/div
VOUTA
2V/div
VOUT
1V/div
VOUTB
10mV/div
AC-COUPLED
VOUTB
10mV/div
AC-COUPLED
CS
1V/div
AVDD = DVDD = 5V
EXTERNAL REFERENCE = 4.096V
MAX1043
100μs/div
100μs/div
1μs/div
DYNAMIC RESPONSE RISE TIME
(RLOAD = 10kΩ, CLOAD = 100pF)
DYNAMIC RESPONSE FALL TIME
(RLOAD = 10kΩ, CLOAD = 100pF)
DYNAMIC RESPONSE FALL TIME
(RLOAD = 10kΩ, CLOAD = 100pF)
MAX1040 toc43
CS
2V/div
VOUT
1V/div
VOUT
2V/div
CS
1V/div
AVDD = DVDD = 5V
EXTERNAL REFERENCE = 4.096V
1μs/div
MAX1040 toc45
MAX1040 toc44
CS
2V/div
12
0.75
-0.75
AVDD = DVDD = 5V
EXTERNAL REFERENCE = 4.096V
0
1.00
MAX1040 toc39
GPIOC0, GPIOC1
OUTPUTS
TEMPERATURE SENSOR ERROR (°C)
900
MAX1040 toc38
1200
GPIO OUTPUT VOLTAGE (mV)
GPIOC0, GPIOC1 OUTPUTS
TEMPERATURE SENSOR ERROR
vs. TEMPERATURE
1500
MAX1040 toc37
1500
GPIO OUTPUT VOLTAGE (mV)
MAX1021/MAX1043
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
VOUT
2V/div
AVDD = DVDD = 5V
EXTERNAL REFERENCE = 4.096V
1μs/div
______________________________________________________________________________________
1μs/div
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
MAJOR CARRY TRANSITION
(RLOAD = 10kΩ, CLOAD = 100pF)
DAC DIGITAL FEEDTHROUGH
(RLOAD = 10kΩ, CLOAD = 100pF,
CS = HIGH, DIN = LOW)
MAJOR CARRY TRANSITION
(RLOAD = 10kΩ, CLOAD = 100pF)
MAX1040 toc46
MAX1040 toc48
MAX1040 toc47
CS
2V/div
CS
1V/div
VOUT
10mV/div
AC-COUPLED
SCLK
1V/div
VOUT
100mV/div
AC-COUPLED
VOUT
20mV/div
AC-COUPLED
AVDD = DVDD = 5V
EXTERNAL REFERENCE = 4.096V
1μs/div
200ns/div
1μs/div
DAC DIGITAL FEEDTHROUGH
(RLOAD = 10kΩ, CLOAD = 100pF,
CS = HIGH, DIN = LOW)
NEGATIVE FULL-SCALE SETTLING TIME
(RLOAD = 10kΩ, CLOAD = 100pF)
MAX1040 toc50
MAX1040 toc49
SCLK
2V/div
VOUT
1V/div
VOUT
100mV/div
AC-COUPLED
VLDAC
1V/div
AVDD = DVDD = 5V
EXTERNAL REFERENCE = 4.096V
200ns/div
1μs/div
______________________________________________________________________________________
13
MAX1021/MAX1043
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V, external VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at
REF, TA = +25°C, unless otherwise noted.)
MAX1021/MAX1043
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics (continued)
(AVDD = DVDD = 3V, external VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at
REF, TA = +25°C, unless otherwise noted.)
NEGATIVE FULL-SCALE SETTLING TIME
(RLOAD = 10kΩ, CLOAD = 100pF)
POSITIVE FULL-SCALE SETTLING TIME
(RLOAD = 10kΩ, CLOAD = 100pF)
POSITIVE FULL-SCALE SETTLING TIME
(RLOAD = 10kΩ, CLOAD = 100pF)
MAX1040 toc51
MAX1040 toc53
MAX1040 toc52
VLDAC
2V/div
VLDAC
2V/div
VOUT_
1V/div
VOUT_
2V/div
VOUT_
2V/div
VLDAC
1V/div
AVDD = DVDD = 5V
EXTERNAL REFERENCE = 4.096V
2μs/div
AVDD = DVDD = 5V
EXTERNAL REFERENCE = 4.096V
1μs/div
1μs/div
ADC REFERENCE FEEDTHROUGH
(RLOAD = 10kΩ, CLOAD = 100pF)
ADC REFERENCE FEEDTHROUGH
(RLOAD = 10kΩ, CLOAD = 100pF)
MAX1040 toc54
MAX1040 toc55
VREF2
1V/div
VREF2
2V/div
ADC REFERENCE SWITCHING
VDAC-OUT
10mV/div
AC-COUPLED
ADC REFERENCE SWITCHING
200μs/div
14
AVDD = DVDD = 5V
EXTERNAL REFERENCE = 4.096V
VDAC-OUT
2mV/div
AC-COUPLED
200μs/div
______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
PIN
MAX1021
MAX1043
1, 2
1, 2
3
3
4
5
NAME
FUNCTION
GPIOA0, GPIOA1 General-Purpose I/O A0, A1. GPIOA0, GPIOA1 can sink and source 15mA.
EOC
Active-Low, End-of-Conversion Output. Data is valid after the falling edge of EOC.
4
DVDD
Digital Positive-Power Input. Bypass DVDD to DGND with a 0.1µF capacitor.
5
DGND
Digital Ground. Connect DGND to AGND.
6
6
DOUT
Serial-Data Output. Data is clocked out on the falling edge of the SCLK clock in
modes 00, 01, and 10. Data is clocked out on the rising edge of the SCLK clock
in mode 11. It is high impedance when CS is high.
7
7
SCLK
Serial-Clock Input. Clocks data in and out of the serial interface. (Duty cycle must be
40% to 60%). See Table 5 for details on programming the clock mode.
8
8
DIN
Serial-Data Input. DIN data is latched into the serial interface on the falling edge
of SCLK.
—
9–12
OUT0–OUT3
DAC Outputs
9–12, 16–19
—
OUT0–OUT7
DAC Outputs
13
13
AVDD
Positive Analog Power Input. Bypass AVDD to AGND with a 0.1µF capacitor.
Analog Ground
14
14
AGND
15, 23, 32, 33
15, 23, 32, 33
N.C.
20
20
LDAC
21
21
CS
22
22
RES_SEL
24, 25
24, 25
No Connection. Not internally connected.
Active-Low, Load DAC. LDAC is an asynchronous active-low input that updates
the DAC outputs. Drive LDAC low to make the DAC registers transparent.
Active-Low, Chip-Select Input. When CS is low, the serial interface is enabled.
When CS is high, DOUT is high impedance.
Reset Select. Select DAC wake-up mode. Set RES_SEL low to wake up the DAC
outputs with a 100kΩ resistor to GND or set RES_SEL high to wake up the DAC outputs
with a 100kΩ resistor to VREF. The default is the external VREF.
GPIOC0, GPIOC1 General-Purpose I/O C0, C1. GPIOC0, GPIOC1 can sink 4mA and source 2mA.
Reference 1 Input. Reference voltage; leave unconnected to use the internal
reference (2.5V). REF1 is the positive reference in ADC differential mode. Bypass
REF1 to AGND with a 0.1µF capacitor in external reference mode only. See the
ADC/DAC References section.
26
26
REF1
27–31, 34
27–31, 34
AIN0–AIN5
Analog Inputs
Reference 2 Input/Analog Input Channel 6. See Table 5 for details on
programming the setup register.
35
35
REF2/AIN6
36
36
CNVST/AIN7
—
16-19
D.C.
—
—
EP
Active-Low, Conversion-Start Input/Analog Input 7. See Table 5 for details on
programming the setup register.
Do Not Connect. Do not connect to this pin.
Exposed Pad. Must be externally connected to AGND. Do not use as a ground
connect.
______________________________________________________________________________________
15
MAX1021/MAX1043
Pin Description
MAX1021/MAX1043
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Detailed Description
The MAX1021/MAX1043 integrate a multichannel 10-bit
ADC and a 10-bit DAC in a single IC. These devices
also include a temperature sensor and configurable
GPIOs with a 25MHz SPI-/QSPI-/MICROWIRE-compatible serial interface. The ADC is available in an 8 inputchannel version. The DAC outputs settle within 2.0µs,
and the ADC has a 225ksps conversion rate.
These devices include an internal reference (2.5V) providing a well-regulated, low-noise reference for both the
ADC and DAC. Programmable reference modes for the
ADC and DAC allow the use of an internal reference, an
external reference, or a combination of both. Features
such as an internal ±1°C accurate temperature sensor,
FIFO, scan modes, programmable internal or external
clock modes, data averaging, and AutoShutdown allow
users to minimize both power consumption and processor requirements. The low glitch energy (4nV•s) and
low digital feedthrough (0.5nV • s) of the integrated
DACs make these devices ideal for digital control of
fast-response closed-loop systems.
The devices are guaranteed to operate with a supply
voltage from +2.7V to +5.25V. They consume 2.5mA at
225ksps throughput, only 0.22µA at 1ksps throughput,
and under 0.2µA in shutdown mode. The MAX1021/
MAX1043 offer four GPIOs that can be configured as
inputs or outputs.
Figure 1 shows the MAX1021 functional diagram. The
MAX1021/MAX1043 only include the GPIO A0, A1, GPIO
C0, C1 blocks. The output-conditioning circuitry takes the
internal parallel data bus and converts it to a serial data
format at DOUT, with the appropriate wake-up timing. The
arithmetic logic unit (ALU) performs the averaging function.
SPI-Compatible Serial Interface
The MAX1021/MAX1043 feature a serial interface that is
compatible with SPI and MICROWIRE devices. For SPI,
ensure the SPI bus master (typically a microcontroller
(µC)) runs in master mode so that it generates the
serial-clock signal. Select the SCLK frequency of
25MHz or less, and set the clock polarity (CPOL) and
phase (CPHA) in the µC control registers to the same
value. The MAX1021/MAX1043 operate with SCLK
idling high or low, and thus operate with CPOL = CPHA
= 0 or CPOL = CPHA = 1. Set CS low to latch any input
data at DIN on the falling edge of SCLK. Output data at
16
DOUT is updated on the falling edge of SCLK in clock
modes 00, 01, and 10. Output data at DOUT is updated
on the rising edge of SCLK in clock mode 11. See
Figures 6–11. Bipolar true-differential results and temperature-sensor results are available in two’s complement format, while all other results are in binary.
A high-to-low transition on CS initiates the data-input
operation. Serial communications to the ADC always
begin with an 8-bit command byte (MSB first) loaded
from DIN. The command byte and the subsequent data
bytes are clocked from DIN into the serial interface on
the falling edge of SCLK. The serial-interface and fastinterface circuitry is common to the ADC, DAC, and
GPIO sections. The content of the command byte
determines whether the SPI port should expect 8, 16, or
24 bits and whether the data is intended for the ADC,
DAC, or GPIOs (if applicable). See Table 1. Driving CS
high resets the serial interface.
The conversion register controls ADC channel selection, ADC scan mode, and temperature-measurement
requests. See Table 4 for information on writing to the
conversion register. The setup register controls the
clock mode, reference, and unipolar/bipolar ADC configuration. Use a second byte, following the first, to
write to the unipolar-mode or bipolar-mode registers.
See Table 5 for details of the setup register and see
Tables 6, 7, and 8 for setting the unipolar- and bipolarmode registers. Hold CS low between the command
byte and the second and third byte. The ADC averaging register is specific to the ADC. See Table 9 to
address that register. Table 11 shows the details of the
reset register.
Begin a write to the DAC by writing 0001XXXX as a
command byte. The last 4 bits of this command byte
are don’t-care bits. Write another 2 bytes (holding CS
low) to the DAC interface register following the command byte to select the appropriate DAC and the data
to be written to it. See the DAC Serial Interface section
and Tables 10, 17, and 18.
Write to the GPIOs (if applicable) by issuing a command byte to the appropriate register. Writing to the
MAX1021/MAX1043 GPIOs requires 1 additional byte
following the command byte. See Tables 12–16 for
details on GPIO configuration, writes, and reads. See
the GPIO Command section. Command bytes written to
the GPIOs on devices without GPIOs are ignored.
______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
AVDD
GPIOC0,
GPIOC1
MAX1021/MAX1043
GPIOA0,
GPIOA1
DVDD
MAX1021
USER-PROGRAMMABLE
I/O
GPIO
CONTROL
OSCILLATOR
INPUT
REGISTER
DAC
REGISTER
10-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT0
INPUT
REGISTER
DAC
REGISTER
10-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT1
INPUT
REGISTER
DAC
REGISTER
10-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT2
INPUT
REGISTER
DAC
REGISTER
10-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT3
INPUT
REGISTER
DAC
REGISTER
10-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT4
INPUT
REGISTER
DAC
REGISTER
10-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT5
INPUT
REGISTER
DAC
REGISTER
10-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT6
INPUT
REGISTER
DAC
REGISTER
10-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT7
SCLK
CS
DIN
SPI
PORT
DOUT
TEMPERATURE
SENSOR
ADDRESS
EOC
LOGIC
CONTROL
CNVST
AIN0
AIN5
REF2/
AIN6
CNVST/
AIN7
REF1
T/H
10-BIT
SAR
ADC
FIFO AND
ALU
REF2
INTERNAL
REFERENCE
LDAC
AGND
DGND
RES_SEL
Figure 1. MAX1021 Functional Diagram
______________________________________________________________________________________
17
MAX1021/MAX1043
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 1. Command Byte (MSB First)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Conversion
REGISTER NAME
1
X
CHSEL2
CHSEL1
CHSEL0
SCAN1
SCAN0
TEMP
Setup
0
1
CKSEL1
CKSEL0
REFSEL1
REFSEL0
DIFFSEL1
DIFFSEL0
ADC Averaging
0
0
1
AVGON
NAVG1
NAVG0
NSCAN1
NSCAN0
DAC Select
0
0
0
1
X
X
X
X
Reset
0
0
0
0
1
RESET
SLOW
FBGON
GPIO Configure
0
0
0
0
0
0
1
1
GPIO Write
0
0
0
0
0
0
1
0
GPIO Read
0
0
0
0
0
0
0
1
No Operation
0
0
0
0
0
0
0
0
X = Don’t care.
Power-Up Default State
The MAX1021/MAX1043 power up with all blocks in
shutdown (including the reference). All registers power
up in state 00000000, except for the setup register and
the DAC input register. The setup register powers up at
00101000 with CKSEL1 = 1 and REFSEL1 = 1. The
DAC input register powers up to 3FFh when RES_SEL
is high, and it powers up to 000h when RES_SEL is low.
10-Bit ADC
The MAX1021/MAX1043 ADCs use a fully differential
successive-approximation register (SAR) conversion
technique and on-chip track-and-hold (T/H) circuitry to
convert temperature and voltage signals into 10-bit digital results. The analog inputs accept both single-ended
and differential input signals. Single-ended signals are
converted using a unipolar transfer function, and differential signals are converted using a selectable bipolar
or unipolar transfer function. See the ADC Transfer
Functions section for more data.
ADC Clock Modes
When addressing the setup, register bits 5 and 4 of the
command byte (CKSEL1 and CKSEL0, respectively)
control the ADC clock modes. See Table 5. Choose
between four different clock modes for various ways to
start a conversion and determine whether the acquisitions are internally or externally timed. Select clock
mode 00 to configure CNVST/AIN_ to act as a conversion start and use it to request internally timed conversions, without tying up the serial bus. In clock mode 01,
use CNVST to request conversions one channel at a
time, thereby controlling the sampling speed without
tying up the serial bus. Request and start internally
18
timed conversions through the serial interface by writing to the conversion register in the default clock mode,
10. Use clock mode 11 with SCLK up to 3.6MHz for
externally timed acquisitions to achieve sampling rates
up to 225ksps. Clock mode 11 disables scanning and
averaging. See Figures 6–9 for timing specifications on
how to begin a conversion.
These devices feature an active-low, end-of-conversion
output. EOC goes low when the ADC completes the last
requested operation and is waiting for the next command byte. EOC goes high when CS or CNVST go low.
EOC is always high in clock mode 11.
Single-Ended or Differential Conversions
The MAX1021/MAX1043 use a fully differential ADC for
all conversions. When a pair of inputs are connected as
a differential pair, each input is connected to the ADC.
When configured in single-ended mode, the positive
input is the single-ended channel and the negative
input is referred to AGND. See Figure 2.
In differential mode, the T/H samples the difference
between two analog inputs, eliminating common-mode
DC offsets and noise. IN+ and IN- are selected from the
following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5,
AIN6/AIN7. See Tables 5–8 for more details on configuring the inputs. For the inputs that are configurable as
CNVST, REF2, and an analog input, only one function
can be used at a time.
______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Analog Input (T/H)
The equivalent circuit of Figure 2 shows the ADC input
architecture of the MAX1021/MAX1043. In track mode,
a positive input capacitor is connected to AIN0–AIN7 in
single-ended mode and AIN0, AIN2, AIN4, and AIN6 in
differential mode. A negative input capacitor is connected to AGND in single-ended mode or AIN1, AIN3,
AIN5, and AIN7 in differential mode. For external T/H
timing, use clock mode 01. After the T/H enters hold
mode, the difference between the sampled positive and
negative input voltages is converted. The input capacitance charging rate determines the time required for
the T/H to acquire an input signal. If the input signal’s
AIN0–AIN7
(SINGLE-ENDED),
AIN0, AIN2,
AIN4, AIN6
(DIFFERENTIAL)
REF1
ACQ
DAC
AGND
CIN+
COMPARATOR
HOLD
CINAGND
(SINGLE-ENDED),
AIN1, AIN3,
AIN5, AIN7
(DIFFERENTIAL)
ACQ
HOLD
ACQ
HOLD
source impedance is high, the required acquisition time
lengthens.
Any source impedance below 300Ω does not significantly affect the ADC’s AC performance. A high-impedance source can be accommodated either by
lengthening tACQ (only in clock mode 01) or by placing
a 1µF capacitor between the positive and negative
analog inputs. The combination of the analog-input
source impedance and the capacitance at the analog
input creates an RC filter that limits the analog input
bandwidth.
Input Bandwidth
The ADC’s input-tracking circuitry has a 1MHz small-signal bandwidth, making it possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias prefiltering
of the input signals is necessary to avoid high-frequency
signals aliasing into the frequency band of interest.
Analog Input Protection
Internal electrostatic-discharge (ESD) protection diodes
clamp all analog inputs to AVDD and AGND, allowing
the inputs to swing from (AGND - 0.3V) to (AVDD +
0.3V) without damage. However, for accurate conversions near full scale, the inputs must not exceed AVDD
by more than 50mV or be lower than AGND by 50mV. If
an analog input voltage exceeds the supplies, limit the
input current to 2mA.
Internal FIFO
The MAX1021/MAX1043 contain a first-in/first-out
(FIFO) buffer that holds up to 16 ADC results plus one
temperature result. The internal FIFO allows the ADC to
process and store multiple internally clocked conversions and a temperature measurement without being
serviced by the serial bus.
If the FIFO is filled and further conversions are requested without reading from the FIFO, the oldest ADC
results are overwritten by the new ADC results. Each
result contains 2 bytes, with the MSB preceded by four
leading zeros. After each falling edge of CS, the oldest
available pair of bytes of data is available at DOUT,
MSB first. When the FIFO is empty, DOUT is zero.
The first 2 bytes of data read out after a temperature
measurement always contain the 10-bit temperature
result, preceded by four leading zeros, MSB first.
AVDD / 2
Figure 2. Equivalent Input Circuit
______________________________________________________________________________________
19
MAX1021/MAX1043
Unipolar or Bipolar Conversions
Address the unipolar- and bipolar-mode registers
through the setup register (bits 1 and 0). See Table 5 for
the setup register. See Figures 3 and 4 for the transferfunction graphs. Program a pair of analog inputs for
differential operation by writing a one to the appropriate
bit of the bipolar- or unipolar-mode register. Unipolar
mode sets the differential input range from 0 to VREF1. A
negative differential analog input in unipolar mode causes the digital output code to be zero. Selecting bipolar
mode sets the differential input range to ±VREF1 / 2. The
digital output code is binary in unipolar mode and two’s
complement in bipolar mode.
In single-ended mode, the MAX1021/MAX1043 always
operate in unipolar mode. The analog inputs are internally referenced to AGND with a full-scale input range
from 0 to the selected reference voltage.
MAX1021/MAX1043
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
The LSB is followed by 2 sub-bits. If another temperature measurement is performed before the first temperature result is read out, the old measurement is
overwritten by the new result. Temperature results are
in degrees Celsius (two’s complement), at a resolution
of 8 LSB per degree. See the Temperature
Measurements section for details on converting the digital code to a temperature.
10-Bit DAC
In addition to the 10-bit ADC, the MAX1021/MAX1043
also include eight (MAX1021) or four (MAX1043) voltage-output, 10-bit, monotonic DACs with less than 1
LSB integral nonlinearity error and less than 0.5 LSB
differential nonlinearity error. Each DAC has a 2µs settling time and ultra-low glitch energy (4nV•s). The 10-bit
DAC code is unipolar binary with 1 LSB = VREF / 1024.
DAC Digital Interface
Figure 1 shows the MAX1021 functional diagram. The
shift register converts a serial 16-bit word to parallel
data for each input register operating with a clock rate
up to 25MHz. The SPI-compatible digital interface to the
shift register consists of CS, SCLK, DIN, and DOUT.
Serial data at DIN is loaded on the falling edge of SCLK.
Pull CS low to begin a write sequence. Begin a write to
the DAC by writing 0001XXXX as a command byte. The
last 4 bits of the DAC select register are don’t-care bits.
See Table 10. Write another 2 bytes to the DAC interface register following the command byte to select the
appropriate DAC and the data to be written to it. See
Tables 17 and 18.
The double-buffered DACs include an input and a DAC
register. The input registers are directly connected to
the shift register and hold the result of the most recent
write operation. The 10-bit DAC registers hold the current output code for the respective DAC. Data can be
transferred from the input registers to the DAC registers
by pulling LDAC low or by writing the appropriate DAC
command sequence at DIN. See Table 17. The outputs
of the DACs are buffered through eight (MAX1021)/ four
(MAX1043) rail-to-rail op amps.
The MAX1021/MAX1043 DAC output voltage range is
based on the internal reference or an external reference. Write to the setup register (see Table 5) to program the reference. If using an external voltage
reference, bypass REF1 with a 0.1µF capacitor to
AGND. The internal reference is 2.5V. When using an
external reference on these devices, the voltage range
is 0.7V to AVDD.
20
DAC Transfer Function
See Table 2 for various analog outputs from the DAC.
DAC Power-On Wake-Up Modes
The state of the RES_SEL input determines the wake-up
state of the DAC outputs. Connect RES_SEL to AVDD or
AGND upon power-up to be sure the DAC outputs
wake up to a known state. Connect RES_SEL to AGND
to wake up all DAC outputs at 000h. While RES_SEL is
low, the 100kΩ internal resistor pulls the DAC outputs to
AGND and the output buffers are powered down.
Connect RES_SEL to AVDD to wake up all DAC outputs
at 3FFh. While RES_SEL is high, the 100kΩ pullup
resistor pulls the DAC outputs to VREF1 and the output
buffers are powered down.
DAC Power-Up Modes
See Table 18 for a description of the DAC power-up
and power-down modes.
GPIOs
In addition to the internal ADC and DAC, the
MAX1021/MAX1043 also provide four GPIO channels,
GPIOA0, GPIOA1, GPIOC0, and GPIOC1.
Read and write to the GPIOs as detailed in Tables 1
and 12–16. Also, see the GPIO Command section. See
Figures 11 and 12 for GPIO timing.
Table 2. DAC Output Code Table
DAC CONTENTS
MSB
LSB
ANALOG OUTPUT
11
1111
1111
⎛ 1023 ⎞
+ VREF ⎜
⎟
⎝ 1024 ⎠
10
0000
0001
⎛ 1023 ⎞
+ VREF ⎜
⎟
⎝ 1024 ⎠
10
0000
0000
⎛ 512 ⎞
⎛ + VREF ⎞
+ VREF ⎜
⎟ = ⎜
⎟
⎝ 1024 ⎠
⎝ 2 ⎠
01
0111
0111
⎛ 511 ⎞
+ VREF ⎜
⎟
⎝ 1024 ⎠
00
0000
0001
⎛ 1 ⎞
+ VREF ⎜
⎟
⎝ 1024 ⎠
00
0000
0000
______________________________________________________________________________________
0
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Clock Modes
Internal Clock
The MAX1021/MAX1043 can operate from an internal
oscillator. The internal oscillator is active in clock
modes 00, 01, and 10. Figures 6, 7, and 8 show how to
start an ADC conversion in the three internally timed
conversion modes.
Read out the data at clock speeds up to 25MHz
through the SPI interface.
External Clock
Set CKSEL1 and CKSEL0 in the setup register to 11 to
set up the interface for external clock mode 11. See
Table 5. Pulse SCLK at speeds from 0.1MHz to
3.6MHz. Write to SCLK with a 40% to 60% duty cycle.
The SCLK frequency controls the conversion timing.
See Figure 9 for clock mode 11 timing. See the ADC
Conversions in Clock Mode 11 section.
ADC/DAC References
Address the reference through the setup register, bits 3
and 2. See Table 5. Following a wake-up delay, set
REFSEL[1:0] = 00 to program both the ADC and DAC
for internal reference use. Set REFSEL[1:0] = 10 to program the ADC for internal reference. Set REFSEL[1:0] =
10 to program the DAC for external reference, REF1.
When using REF1 or REF2/AIN_ in external-reference
mode, connect a 0.1µF capacitor to AGND. Set
REFSEL[1:0] = 01 to program the ADC and DAC for
external-reference mode. The DAC uses REF1 as its
external reference, while the ADC uses REF2 as its
external reference. Set REFSEL[1:0] = 11 to program
the ADC for external differential-reference mode. REF1
is the positive reference and REF2 is the negative reference in the ADC external differential mode.
Table 3. GPIO Maximum Sink/Source
Current
CURRENT
GPIOA0, GPIOA1
(mA)
GPIOC0, GPIOC1
(mA)
Sink
15
4
Source
15
2
When REFSEL[1:0] = 00 or 10, REF2/AIN_ functions as
an analog input channel. When REFSEL[1:0] = 01 or 11,
REF2/AIN_ functions as the device’s negative reference.
Temperature Measurements
Issue a command byte setting bit 0 of the conversion
register to one to take a temperature measurement.
See Table 4. The MAX1021/MAX1043 perform temperature measurements with an internal diode-connected
transistor. The diode bias current changes from 68µA to
4µA to produce a temperature-dependent bias voltage
difference. The second conversion result at 4µA is subtracted from the first at 68µA to calculate a digital value
that is proportional to absolute temperature. The output
data appearing at DOUT is the digital code above,
minus an offset to adjust from Kelvin to Celsius.
The reference voltage used for the temperature measurements is always derived from the internal reference
source to ensure that 1 LSB corresponds to 1/8th of a
degree Celsius. On every scan where a temperature
measurement is requested, the 12-bit temperature conversion is carried out first. The first 2 bytes of data read
from the FIFO contain the result of the 12-bit temperature measurement. If another temperature measurement is performed before the first temperature result is
read out, the old measurement is overwritten by the
new result. Temperature results are in degrees Celsius
(two’s complement). See the Applications Information
section for information on how to perform temperature
measurements in each clock mode.
Register Descriptions
The MAX1021/MAX1043 communicate between the
internal registers and the external circuitry through the
SPI-compatible serial interface. Table 1 details the
command byte, the registers, and the bit names.
Tables 4–12 show the various functions within the conversion register, setup register, unipolar-mode register,
bipolar-mode register, ADC averaging register, DAC
select register, reset register, and GPIO command register, respectively.
Conversion Register
Select active analog input channels, scan modes, and
a single temperature measurement per scan by issuing
a command byte to the conversion register. Table 4
details channel selection, the four scan modes, and
how to request a temperature measurement. Start a
scan by writing to the conversion register when in clock
mode 10 or 11, or by applying a low pulse to the
CNVST pin when in clock mode 00 or 01. See Figures 6
and 7 for timing specifications for starting a scan with
CNVST.
______________________________________________________________________________________
21
MAX1021/MAX1043
Write to the GPIOs by writing a command byte to the
GPIO command register. Write a single data byte to the
MAX1021/MAX1043 following the command byte.
The GPIOs can sink and source current. GPIOA0 and
GPIOA1 can sink and source up to 15mA. GPIOC0 and
GPIOC1 can sink 4mA and source 2mA. See Table 3.
MAX1021/MAX1043
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
A conversion is not performed if it is requested on a
channel or one of the channel pairs that has been configured as CNVST or REF2. For channels configured as
differential pairs, the CHSEL0 bit is ignored and the two
pins are treated as a single differential channel.
Select scan mode 00 or 01 to return one result per single-ended channel and one result per differential pair
within the selected scanning range (set by bits 2 and 1,
SCAN1 and SCAN0), plus one temperature result if
selected. Select scan mode 10 to scan a single input
channel numerous times, depending on NSCAN1 and
NSCAN0 in the ADC averaging register (Table 9).
Select scan mode 11 to return only one result from a
single channel.
Setup Register
Issue a command byte to the setup register to configure the clock, reference, power-down modes, and ADC
single-ended/differential modes. Table 5 details the bits
in the setup-register command byte. Bits 5 and 4
(CKSEL1 and CKSEL0) control the clock mode, acquisition and sampling, and the conversion start. Bits 3
and 2 (REFSEL1 and REFSEL0) set the device for either
internal or external reference. Bits 1 and 0 (DIFFSEL1
and DIFFSEL0) address the ADC unipolar-mode and
bipolar-mode registers and configure the analog input
channels for differential operation.
The ADC reference is always on if any of the following
conditions are true:
1)The FBGON bit is set to one in the reset register.
2)At least one DAC output is powered up and
REFSEL[1:0] (in the setup register) = 00.
3)At least one DAC is powered down through the
100kΩ to VREF and REFSEL[1:0] = 00.
If any of the above conditions exist, the ADC reference
is always on, but there is a 188 clock-cycle delay
before temperature-sensor measurements begin, if
requested.
22
Table 4. Conversion Register*
BIT
NAME
—
BIT
FUNCTION
7 (MSB)
Set to one to select conversion register.
X
6
Don’t care.
CHSEL2
5
Analog-input channel select.
CHSEL1
4
Analog-input channel select.
CHSEL0
3
Analog-input channel select.
SCAN1
2
Scan-mode select.
SCAN0
1
Scan-mode select.
TEMP
0 (LSB)
Set to one to take a single temperature measurement. The first
conversion result of a scan contains
temperature information.
*See below for bit details.
CHSEL2
CHSEL1
CHSEL0
SELECTED
CHANNEL
(N)
0
0
0
AIN0
0
0
1
AIN1
0
1
0
AIN2
0
1
1
AIN3
1
0
0
AIN4
1
0
1
AIN5
1
1
0
AIN6
1
1
1
AIN7
SCAN MODE
(CHANNEL N IS SELECTED BY
BITS CHSEL2, CHSEL1, AND CHSEL0)
SCAN1
SCAN0
0
0
Scans channels 0 through N.
0
1
Scans channels N through the
highest numbered channel.
1
0
Scans channel N repeatedly. The
ADC averaging register sets the
number of results.
1
1
No scan. Converts channel N once only.
______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
BIT NAME
BIT
—
7 (MSB)
Set to zero to select setup register.
—
6
Set to one to select setup register.
CKSEL1
5
Clock mode and CNVST configuration; resets to one at power-up.
MAX1021/MAX1043
Table 5. Setup Register*
FUNCTION
CKSEL0
4
Clock mode and CNVST configuration.
REFSEL1
3
Reference-mode configuration.
REFSEL0
2
Reference-mode configuration.
DIFFSEL1
1
Unipolar-/bipolar-mode register configuration for differential mode.
DIFFSEL0
0 (LSB)
Unipolar-/bipolar-mode register configuration for differential mode.
*See below for bit details.
Table 5a. Clock Modes (see the Clock Modes section)
CKSEL1
CKSEL0
CONVERSION CLOCK
ACQUISITION/SAMPLING
CNVST CONFIGURATION
0
0
Internal
Internally timed.
CNVST
0
1
Internal
Externally timed by CNVST.
CNVST
1
0
Internal
Internally timed.
AIN7
1
1
External (3.6MHz max)
Externally timed by SCLK.
AIN7
Table 5b. Clock Modes 00, 01, and 10
REFSEL1 REFSEL0
VOLTAGE
REFERENCE
OVERRIDE
CONDITIONS
AIN
0
0
Internal (DAC
and ADC)
0
1
1
0
AIN
1
Internal reference required. There is a programmed
delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
Internal reference not used.
Internal reference required. There is a programmed
delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
AIN
Default reference mode. Internal reference turns off
after scan is complete. If internal reference is turned
off, there is a programmed delay of 218 internalconversion clock cycles.
Temperature
1
Internal reference turns off after scan is complete. If
internal reference is turned off, there is a programmed
delay of 218 internal-conversion clock cycles.
Temperature
Internal (ADC)
and external
REF1 (DAC)
External
differential
(ADC), external
REF1 (DAC)
REF2
CONFIGURATION
AIN6
Temperature
External singleended (REF1
for DAC and
REF2 for ADC)
AUTOSHUTDOWN
AIN
Temperature
REF2
AIN6
Internal reference required. There is a programmed
delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
Internal reference not used.
Internal reference required. There is a programmed
delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
REF2
______________________________________________________________________________________
23
MAX1021/MAX1043
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 5c. Clock Mode 11
REFSEL1 REFSEL0
0
0
VOLTAGE
REFERENCE
OVERRIDE
CONDITIONS
AIN
Internal reference turns off after scan is complete. If
internal reference is turned off, there is a programmed
delay of 218 external conversion clock cycles.
Temperature
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
Internal (DAC
and ADC)
AIN
0
1
1
0
External singleended (REF1
for DAC and
REF2 for ADC)
Temperature
AIN
Default reference mode. Internal reference turns off
after scan is complete. If internal reference is turned
off, there is a programmed delay of 218 external
conversion clock cycles.
Temperature
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
1
AIN6
REF2
AIN6
AIN
1
REF2
CONFIGURATION
Internal reference not used.
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
Internal (ADC)
and external
REF1 (DAC)
External
differential
(ADC), external
REF1 (DAC)
AUTOSHUTDOWN
Temperature
Internal reference not used.
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
REF2
Table 5d. Differential Select Modes
DIFFSEL1 DIFFSEL0
24
FUNCTION
0
0
No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged.
0
1
No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged.
1
0
1 byte of data follows the command setup byte and is written to the unipolar-mode register.
1
1
1 byte of data follows the command setup byte and is written to the bipolar-mode register.
______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
BIT NAME
BIT
UCH0/1
7 (MSB)
Configure AIN0 and AIN1 for unipolar differential conversion.
FUNCTION
UCH2/3
6
Configure AIN2 and AIN3 for unipolar differential conversion.
UCH4/5
5
Configure AIN4 and AIN5 for unipolar differential conversion.
UCH6/7
4
Configure AIN6 and AIN7 for unipolar differential conversion.
X
3
Don’t care.
X
2
Don’t care.
X
1
Don’t care.
X
0 (LSB)
Don’t care.
Table 7. Bipolar-Mode Register (Addressed Through the Setup Register)
BIT NAME
BIT
FUNCTION
BCH0/1
7 (MSB)
Set to one to configure AIN0 and AIN1 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN0 and AIN1 for unipolar
single-ended conversion.
BCH2/3
6
Set to one to configure AIN2 and AIN3 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN2 and AIN3 for unipolar
single-ended conversion.
BCH4/5
5
Set to one to configure AIN4 and AIN5 for bipolar differential conversion (MAX1021/MAX1043). Set
the corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN4
and AIN5 for unipolar single-ended conversion.
BCH6/7
4
Set to one to configure AIN6 and AIN7 for bipolar differential conversion (MAX1043). Set the
corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN6 and
AIN7 for unipolar single-ended conversion.
X
3
Don’t care.
X
2
Don’t care.
X
1
Don’t care.
X
0 (LSB)
Don’t care.
______________________________________________________________________________________
25
MAX1021/MAX1043
Table 6. Unipolar-Mode Register (Addressed Through the Setup Register)
MAX1021/MAX1043
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Unipolar/Bipolar Registers
The final 2 bits (LSBs) of the setup register control
the unipolar-/bipolar-mode address registers. Set
DIFFSEL[1:0] = 10 to write to the unipolar-mode register. Set bits DIFFSEL[1:0] = 11 to write to the bipolarmode register. In both cases, the setup command byte
must be followed by 1 byte of data that is written to the
unipolar-mode register or bipolar-mode register. Hold
CS low and run 16 SCLK cycles before pulling CS high.
Table 8. Unipolar/Bipolar Channel Function
UNIPOLARMODE
REGISTER BIT
BIPOLAR-MODE
REGISTER BIT
CHANNEL PAIR
FUNCTION
0
0
Unipolar single-ended
0
1
Bipolar differential
1
0
Unipolar differential
1
1
Unipolar differential
If the last 2 bits of the setup register are 00 or 01, neither the unipolar-mode register nor the bipolar-mode
register is written. Any subsequent byte is recognized
as a new command byte. See Tables 6, 7, and 8 to program the unipolar- and bipolar-mode registers.
Both registers power up at all zeros to set the inputs as
eight unipolar single-ended channels. To configure a
channel pair as single-ended unipolar, bipolar differential, or unipolar differential, see Table 8.
In unipolar mode, AIN+ can exceed AIN- by up to
VREF. The output format in unipolar mode is binary. In
bipolar mode, either input can exceed the other by up
to VREF / 2. The output format in bipolar mode is two’s
complement (see the ADC Transfer Functions section).
ADC Averaging Register
Write a command byte to the ADC averaging register to
configure the ADC to average up to 32 samples for
each requested result, and to independently control the
number of results requested for single-channel scans.
Table 9. ADC Averaging Register*
BIT NAME
BIT
—
7 (MSB)
Set to zero to select ADC averaging register.
FUNCTION
—
6
Set to zero to select ADC averaging register.
Set to one to select ADC averaging register.
—
5
AVGON
4
Set to one to turn averaging on. Set to zero to turn averaging off.
NAVG1
3
Configures the number of conversions for single-channel scans.
NAVG0
2
Configures the number of conversions for single-channel scans.
NSCAN1
1
Single-channel scan count. (Scan mode 10 only.)
NSCAN0
0 (LSB)
*See below for bit details.
Single-channel scan count. (Scan mode 10 only.)
FUNCTION
AVGON
NAVG1
0
X
X
Performs one conversion for each requested result.
1
0
0
Performs four conversions and returns the average for each requested result.
1
0
1
Performs eight conversions and returns the average for each requested result.
1
1
0
Performs 16 conversions and returns the average for each requested result.
1
1
1
Performs 32 conversions and returns the average for each requested result.
26
NAVG0
NSCAN1
NSCAN0
0
0
Scans channel N and returns four results.
FUNCTION (APPLIES ONLY IF SCAN MODE 10 IS SELECTED)
0
1
Scans channel N and returns eight results.
1
0
Scans channel N and returns 12 results.
1
1
Scans channel N and returns 16 results.
______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
DAC Select Register
Write a command byte 0001XXXX to the DAC select
register (as shown in Table 9) to set up the DAC interface and indicate that another word will follow. The last
4 bits of the DAC select register are don’t-care bits. The
word that follows the DAC select-register command
byte controls the DAC serial interface. See Table 17
and the DAC Serial Interface section.
Table 10. DAC Select Register
BIT
NAME
—
BIT
FUNCTION
7 (MSB) Set to zero to select DAC select register.
Reset Register
Write to the reset register (as shown in Table 11) to
clear the FIFO or reset all registers (excluding the DAC
and GPIO registers) to their default states. When the
RESET bit in the reset register is set to 0, the FIFO is
cleared. Set the RESET bit to one to return all the
device registers to their default power-up state. All registers power up in state 00000000, except for the setup
register that powers up in clock mode 10 (CKSEL1 = 1
and REFSEL1 = 1). The DAC and GPIO registers are
not reset by writing to the reset register. Set the SLOW
bit to one to add a 15ns delay in the DOUT signal path
to provide a longer hold time. Writing a one to the
SLOW bit also clears the contents of the FIFO. Set the
FBGON bit to one to force the bias block and bandgap
reference to power up regardless of the state of the
DAC and activity of the ADC block. Setting the FBGON
bit high also removes the programmed wake-up delay
between conversions in clock modes 01 and 11.
Setting the FBGON bit high also clears the FIFO.
GPIO Command
Write a command byte to the GPIO command register
to configure, write, or read the GPIOs, as detailed in
Table 12.
—
6
Set to zero to select DAC select register.
—
5
Set to zero to select DAC select register.
—
4
Set to one to select DAC select register.
X
3
Don’t care.
X
2
Don’t care.
BIT NAME
BIT
FUNCTION
X
1
Don’t care.
—
7 (MSB)
Set to zero to select GPIO register.
X
0
Don’t care.
—
6
Set to zero to select GPIO register.
—
5
Set to zero to select GPIO register.
—
4
Set to zero to select GPIO register.
—
3
Set to zero to select GPIO register.
—
2
Set to zero to select GPIO register.
GPIOSEL1
1
GPIO configuration bit.
GPIOSEL2
0 (LSB)
GPIOSEL1
GPIOSEL2
1
1
GPIO configuration; written data is
entered in the GPIO configuration
register.
1
0
GPIO write; written data is entered
in the GPIO write register.
0
1
GPIO read; the next 8 SCLK cycles
transfer the state of all GPIO
drivers into DOUT.
Table 12. GPIO Command Register
Table 11. Reset Register
BIT
NAME
—
BIT
FUNCTION
7 (MSB) Set to zero to select ADC reset register.
—
6
Set to zero to select ADC reset register.
—
5
Set to zero to select ADC reset register.
—
4
Set to zero to select ADC reset register.
—
3
Set to one to select ADC reset register.
RESET
2
Set to zero to clear the FIFO only. Set to
one to set the device in its power-on
condition.
SLOW
1
Set to one to turn on slow mode.
FBGON
0 (LSB)
Set to one to force internal bias block and
bandgap reference to be always powered
up.
GPIO write bit.
FUNCTION
______________________________________________________________________________________
27
MAX1021/MAX1043
Table 9 details the four scan modes available in the
ADC conversion register. All four scan modes allow
averaging as long as the AVGON bit, bit 4 in the
averaging register, is set to 1. Select scan mode 10 to
scan the same channel multiple times. Clock mode 11
disables averaging. For example, if AVGON = 1,
NAVG[1:0] = 00, NSCAN[1:0] = 11 and SCAN[1:0] =
10, 16 results are written to the FIFO, with each result
being the average of four conversions of channel N.
MAX1021/MAX1043
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
DAC Serial Interface
Write a command byte 0001XXXX to the DAC select
register to indicate the word to follow is written to the
DAC serial interface, as detailed in Tables 1, 10, 17, and
18. Write the next 16 bits to the DAC interface register,
as shown in Tables 17 and 18. Following the high-to-low
transition of CS, the data is shifted synchronously and
latched into the input register on each falling edge of
SCLK. Each word is 16 bits. The first 4 bits are the control bits, followed by 10 data bits (MSB first), followed by
2 sub-bits. See Figures 9–12 for DAC timing specifications.
If CS goes high prior to completing 16 SCLK cycles, the
command is discarded. To initiate a new transfer, drive
CS low again.
For example, writing the DAC serial interface word 1111
0000 and 00110100 disconnects DAC outputs 2 and 3
and forces them to a high-impedance state. DAC outputs 0 and 1 remain in their previous state.
Write the command byte 00000011 to configure the
GPIOs. The eight SCLK cycles following the command
byte load data from DIN to the GPIO configuration register in the MAX1021/MAX1043. See Tables 13 and 14.
The register bits are updated after the last CS rising
edge. All GPIOs default to inputs upon power-up.
The data in the register controls the function of each
GPIO, as shown in Tables 13, 14, and 16.
GPIO Write
Write the command byte 00000010 to indicate a GPIO
write operation. The eight SCLK cycles following the
command byte load data from DIN into the GPIO write
register in the MAX1021/MAX1043. See Tables 14 and
15. The register bits are updated after the last CS rising
edge.
GPIO Read
Write the command byte 00000001 to indicate a GPIO
read operation. The eight SCLK cycles following the
command byte transfer the state of the GPIOs to DOUT
in the MAX1021/MAX1043. See Table 16.
Table 13. MAX1021/MAX1043 GPIO Configuration
DATA PIN
GPIO COMMAND BYTE
DATA BYTE
DIN
0
0
0
0
0
0
1
1
GPIOC1
GPIOC0
GPIOA1
GPIOA0
X
X
X
X
DOUT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 14. MAX1021/MAX1043 GPIO Write
DATA PIN
GPIO COMMAND BYTE
DATA BYTE
DIN
0
0
0
0
0
0
1
0
GPIOC1
GPIOC0
GPIOA1
GPIOA0
X
X
X
X
DOUT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 15. GPIO-Mode Control
CONFIGURATION
BIT
WRITE
BIT
OUTPUT
STATE
GPIO
FUNCTION
1
1
1
Output
1
0
0
Output
0
1
Tri-state
Input
0
Pulldown
(open drain)
0
0
Table 16. MAX1021/MAX1043 GPIO Read
DATA PIN
GPIO COMMAND BYTE
DATA BYTE
DIN
0
0
0
0
0
0
0
1
X
X
X
X
X
X
X
X
DOUT
0
0
0
0
0
0
0
0
0
0
0
0
GPIOC1
GPIOC0
GPIOA1
GPIOA0
28
______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
16-BIT SERIAL WORD
MSB
LSB
CONTROL BITS
C3 C2 C1 C0
0
0
0
0
DATA BITS
D9
D8
X
X
D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
X
X
X
X
X
X
X
X
DESCRIPTION
NOP
FUNCTION
No operation.
Reset all internal registers to
000h and leave output buffers in
their present state.
Preset all internal registers to
FFFh and leave output buffers in
their present state.
0
0
0
1
0
X
X
X
X
X
X
X
X
X
X
X
RESET
0
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
Pull-High
0
0
1
0
—
—
—
—
—
—
—
—
—
—
X
X
DAC0
D9–D0 to input register 0, DAC
output unchanged.
0
0
1
1
—
—
—
—
—
—
—
—
—
—
X
X
DAC1
D9–D0 to input register 1, DAC
output unchanged.
0
1
0
0
—
—
—
—
—
—
—
—
—
—
X
X
DAC2
D9–D0 to input register 2, DAC
output unchanged.
0
1
0
1
—
—
—
—
—
—
—
—
—
—
X
X
DAC3
D9–D0 to input register 3, DAC
output unchanged.
0
1
1
0
—
—
—
—
—
—
—
—
—
—
X
X
DAC4
D9–D0 to input register 4, DAC
output unchanged (MAX1021).
NOP command (MAX1043).
0
1
1
1
—
—
—
—
—
—
—
—
—
—
X
X
DAC5
D9–D0 to input register 5, DAC
output unchanged (MAX1021).
NOP command (MAX1043).
1
0
0
0
—
—
—
—
—
—
—
—
—
—
X
X
DAC6
D9–D0 to input register 6, DAC
output unchanged (MAX1021).
NOP command (MAX1043).
1
0
0
1
—
—
—
—
—
—
—
—
—
—
X
X
DAC7
D9–D0 to input register 7, DAC
output unchanged (MAX1021).
NOP command (MAX1043).
1
0
1
0
—
—
—
—
—
—
—
—
—
—
X
X
DAC0–3
D9–D0 to input registers 0–3 and
DAC register 0–3. DAC outputs
updated (write-through).
DAC4–7
D9–D0 to input registers 4–7 and
DAC register 4–7 (MAX1021).
DAC outputs updated (writethrough). NOP command
(MAX1043).
DAC0–7
D9–D0 to input registers 0–7 and
DAC register 0–7 (MAX1021).
D11–D0 to input registers 0–3
and DAC registers 0–3
(MAX1043). DAC outputs
updated (write-through).
1
1
0
1
1
0
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
______________________________________________________________________________________
29
MAX1021/MAX1043
Table 17. DAC Serial-Interface Configuration
Table 17. DAC Serial-Interface Configuration (continued)
16-BIT SERIAL WORD
MSB
LSB
CONTROL BITS
—
—
—
—
—
DAC0
—
DAC1
0
—
DAC2
1
—
DAC3
1
1
D7 D6 D5 D4 D3 D2 D1 D0
DAC4
1
0
D8
DAC5
1
D9
DAC6
1
DATA BITS
DAC7
C3 C2 C1 C0
—
X
—
X
X
X
X
DESCRIPTION
FUNCTION
X
X
X
DAC0–7
D9–D0 to input registers 0–7
(MAX1021). D9–D0 to input
registers 0–3 (MAX1043). DAC
outputs unchanged.
DAC0–7
Input registers to DAC registers
indicated by ones, DAC outputs
updated, equivalent to software
LDAC. (No effect on DACs
indicated by zeros.) DAC7–
DAC4 are only valid on the
MAX1021. These bits are don’tcare bits for the MAX1043.
Table 18. DAC Power-Up and Power-Down Commands
CONTROL
BITS
1
1
1
1
1
30
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DAC0
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
C3 C2 C1 C0
DATA BITS
DAC7
MAX1021/MAX1043
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
DESCRIPTION
FUNCTION
D3 D2 D1 D0
— — — — — — — — 0
— — — — — — — — 0
— — — — — — — — 1
— — — — — — — — 0
— — — — — — — — 1
0
1
0
0
1
1
0
0
0
1
X
Power-Up
Power up individual DAC buffers indicated by data
in DAC0 through DAC3. A one indicates the DAC
output is connected and active. A zero does not
affect the DAC’s present state.
X
Power down individual DAC buffers indicated by
data in DAC0 through DAC3. A one indicates the
Power-Down 1
DAC output is disconnected and high impedance.
A zero does not affect the DAC’s present state.
X
Power down individual DAC buffers indicated by
data in DAC0 through DAC3. A one indicates the
Power-Down 2 DAC output is disconnected and pulled to AGND
with a 1kΩ resistor. A zero does not affect the DAC’s
present state.
X
Power down individual DAC buffers indicated by
data in DAC0 through DAC3. A one indicates the
Power-Down 3 DAC output is disconnected and pulled to AGND
with a 100kΩ resistor. A zero does not affect the
DAC’s present state.
X
Power down individual DAC buffers indicated by
data in DAC0 through DAC3. A one indicates the
Power-Down 4 DAC output is disconnected and pulled to REF1 with
a 100kΩ resistor. A zero does not affect the DAC’s
present state.
______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ADC Transfer Functions
Figure 3 shows the unipolar transfer function for singleended or differential inputs. Figure 4 shows the bipolar
transfer function for differential inputs. Code transitions
occur halfway between successive-integer LSB values.
Output coding is binary, with 1 LSB = VREF1 / 1024 for
unipolar and bipolar operation, and 1 LSB = +0.125°C
for temperature measurements. Bipolar true-differential
results and temperature-sensor results are available in
two’s complement format, while all others are in binary.
See Tables 6, 7, and 8 for details on which setting
(unipolar or bipolar) takes precedence.
In unipolar mode, AIN+ can exceed AIN- by up to
VREF1. In bipolar mode, either input can exceed the
other by up to VREF1 / 2.
Partial Reads and Partial Writes
If the first byte of an entry in the FIFO is partially read
(CS is pulled high after fewer than eight SCLK cycles),
the remaining bits are lost for that byte. The next byte of
data that is read out contains the next 8 bits. If the first
byte of an entry in the FIFO is read out fully, but the
second byte is read out partially, the rest of that byte is
lost. The remaining data in the FIFO is unaffected and
can be read out normally after taking CS low again, as
long as the 4 leading bits (normally zeros) are ignored.
If CS is pulled low before EOC goes low, a conversion
may not be completed and the FIFO data may not be
correct. Incorrect writes (pulling CS high before completing eight SCLK cycles) are ignored and the register
remains unchanged.
Applications Information
Internally Timed Acquisitions and
Conversions Using CNVST
ADC Conversions in Clock Mode 00
In clock mode 00, the wake-up, acquisition, conversion,
and shutdown sequence is initiated through CNVST
and performed automatically using the internal oscillator. Results are added to the internal FIFO to be read
out later. See Figure 6 for clock mode 00 timing after a
command byte is issued. See Table 5 for details on
programming the clock mode in the setup register.
Initiate a scan by setting CNVST low for at least 40ns
before pulling it high again. The MAX1021/MAX1043
then wake up, scan all requested channels, store the
results in the FIFO, and shut down. After the scan is
complete, EOC is pulled low and the results are available in the FIFO. Wait until EOC goes low before pulling
CS low to communicate with the serial interface. EOC
stays low until CS or CNVST is pulled low again. A temperature-conversion result, if requested, precedes all
other FIFO results. Temperature results are available in
12-bit format.
Do not issue a second CNVST signal before EOC goes
low; otherwise, the FIFO can be corrupted. Wait until all
conversions are complete before reading the FIFO. SPI
communications to the DAC and GPIO registers are permitted during conversion. However, coupled noise may
result in degraded ADC signal-to-noise ratio (SNR).
Externally Timed Acquisitions and
Internally Timed Conversions with CNVST
ADC Conversions in Clock Mode 01
In clock mode 01, conversions are requested one at a
time using CNVST and performed automatically using
the internal oscillator. See Figure 7 for clock mode 01
timing after a command byte is issued.
Setting CNVST low begins an acquisition, wakes up the
ADC, and places it in track mode. Hold CNVST low for
at least 1.4µs to complete the acquisition. If reference
mode 00 or 10 is selected, an additional 45µs is
required for the internal reference to power up. If a temperature measurement is being requested, reference
power-up and temperature measurement is internally
timed. In this case, hold CNVST low for at least 40ns.
______________________________________________________________________________________
31
MAX1021/MAX1043
Output-Data Format
Figures 6–9 illustrate the conversion timing for the
MAX1021/MAX1043. All 10-bit conversion results are output in 2-byte format, MSB first, with four leading zeros
and the LSB followed by 2 sub-bits. Data appears on
DOUT on the falling edges of SCLK. Data is binary for
unipolar mode and two’s complement for bipolar mode
and temperature results. See Figures 3, 4, and 5 for
input/output and temperature-transfer functions.
Internally Timed Acquisitions and
Conversions Using the Serial Interface
ADC Conversions in Clock Mode 10
In clock mode 10, the wake-up, acquisition, conversion,
and shutdown sequence is initiated by writing a command byte to the conversion register, and is performed
automatically using the internal oscillator. This is the
default clock mode upon power-up. See Figure 8 for
clock mode 10 timing.
VREF = VREF+ - VREFVREF
VREF
011....111
OFFSET BINARY OUTPUT CODE (LSB)
Set CNVST high to begin a conversion. Sampling is
completed approximately 500ns after CNVST goes
high. After the conversion is complete, the ADC shuts
down and pulls EOC low. EOC stays low until CS or
CNVST is pulled low again. Wait until EOC goes low
before pulling CS or CNVST low. The number of CNVST
signals must equal the number of conversions requested by the scan and averaging registers to correctly
update the FIFO. Wait until all conversions are complete before reading the FIFO. SPI communications to
the DAC and GPIO registers are permitted during conversion. However, coupled noise may result in degraded ADC SNR.
If averaging is turned on, multiple CNVST pulses need to
be performed before a result is written to the FIFO. Once
the proper number of conversions has been performed
to generate an averaged FIFO result (as specified to the
averaging register), the scan logic automatically switches the analog input multiplexer to the next requested
channel. If a temperature measurement is programmed,
it is performed after the first rising edge of CNVST following the command byte written to the conversion register.
The temperature-conversion result is available on DOUT
once EOC has been pulled low. Temperature results are
available in 12-bit format.
011....110
011....101
FS = VREF / 2 + VCOM
ZS = COM
-FS = -VREF / 2
VREF
1 LSB = VREF / 1024
000....001
000....000
(COM)
111....111
VREF
100....011
100....010
100....001
100....000
-FS
-1 0 +1
(COM)
INPUT VOLTAGE (LSB)
+FS - 1 LSB
Figure 4. Bipolar Transfer Function—Full Scale (±FS) = ±VREF / 2
OUTPUT CODE
FULL-SCALE
TRANSITION
111....111
OFFSET BINARY OUTPUT CODE (LSB)
MAX1021/MAX1043
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
111....110
FS = VREF
111....101
1 LSB = VREF / 1024
011....111
011....110
000....010
000....001
000....000
111....111
000....011
111....110
111....101
000....010
000....001
000....000
0 1 2 3
FS
100....001
100....000
INPUT VOLTAGE (LSB)
FS - 3/2 LSB
-256
0
TEMPERATURE (°C)
Figure 3. Unipolar Transfer Function—Full Scale (FS) = VREF
32
Figure 5. Temperature Transfer Function
______________________________________________________________________________________
+255.5
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
MAX1021/MAX1043
CNVST
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
CS
SCLK
DOUT
MSB1
LSB1
MSB2
tRDS
EOC
Figure 6. Clock Mode 00—After writing a command byte, set CNVST low for at least 40ns to begin a conversion.
tCSW
CNVST
(CONVERSION 2)
(ACQUISITION 1)
(ACQUISITION 2)
CS
tDOV
SCLK
(CONVERSION 1)
DOUT
MSB1
LSB1
MSB2
EOC
Figure 7. Clock Mode 01—After writing a command byte, request multiple conversions by setting CNVST low for each conversion.
Initiate a scan by writing a command byte to the conversion register. The MAX1021/MAX1043 then power up,
scan all requested channels, store the results in the
FIFO, and shut down. After the scan is complete, EOC is
pulled low and the results are available in the FIFO. If a
temperature measurement is requested, the temperature result precedes all other FIFO results. Temperature
results are available in 12-bit format. EOC stays low until
CS is pulled low again. Wait until all conversions are
complete before reading the FIFO. SPI communications
to the DAC and GPIO registers are permitted during
conversion. However, coupled noise may result in
degraded ADC SNR.
Externally Clocked Acquisitions and
Conversions Using the Serial Interface
ADC Conversions in Clock Mode 11
In clock mode 11, acquisitions and conversions are
initiated by writing a command byte to the conversion
register and are performed one at a time using SCLK
as the conversion clock. Scanning, averaging, and the
FIFO are disabled, and the conversion result is available at DOUT during the conversion. Output data is
updated on the rising edge of SCLK in clock mode 11.
See Figure 9 for clock mode 11 timing.
Initiate a conversion by writing a command byte to the
conversion register followed by 16 SCLK cycles. If CS
is pulsed high between the eighth and ninth cycles, the
pulse width must be less than 100µs. To continuously
convert at 16 cycles per conversion, alternate 1 byte of
______________________________________________________________________________________
33
MAX1021/MAX1043
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
DIN
(CONVERSION BYTE)
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
CS
SCLK
DOUT
MSB1
tDOV
LSB1
MSB2
EOC
Figure 8. Clock Mode 10—The command byte to the conversion register begins the acquisition (CNVST is not required).
zeros (NOP byte) between each conversion byte. If 2
NOP bytes follow a conversion byte, the analog cells
power down at the end of the second NOP. Set the
FBGON bit to one in the reset register to keep the internal bias block powered.
If reference mode 00 is requested, or if an external reference is selected, but a temperature measurement is
being requested, wait 45µs with CS high after writing the
conversion byte to extend the acquisition and allow the
internal reference to power up. To perform a temperature
measurement, write 24 bytes (192 cycles) of zeros after
the conversion byte. The temperature result appears on
DOUT during the last 2 bytes of the 192 cycles.
Temperature results are available in 12-bit format.
Conversion-Time Calculations
The conversion time for each scan is based on a number of different factors: conversion time per sample,
samples per result, results per scan, if a temperature
measurement is requested, and if the external reference is in use. Use the following formula to calculate
the total conversion time for an internally timed conversion in clock mode 00 and 10 (see the Electrical
Characteristics, as applicable):
34
Total conversion time =
tCNV x nAVG x nSCAN + tTS + tINT-REF,SU
where:
tCNV = tDOV (where tDOV is dependent on clock mode
and reference mode selected)
nAVG = samples per result (amount of averaging)
nSCAN = number of times each channel is scanned; set
to one unless [SCAN1, SCAN0] = 10
t TS = time required for temperature measurement
(53.1µs); set to zero if temperature measurement is not
requested
tINT-REF,SU = tWU (external-reference wake-up); if a
conversion using the external reference is requested.
In clock mode 01, the total conversion time depends on
how long CNVST is held low or high. Conversion time in
externally clocked mode (CKSEL1, CKSEL0 = 11)
depends on the SCLK period and how long CS is held
high between each set of eight SCLK cycles. In clock
mode 01, the total conversion time does not include the
time required to turn on the internal reference.
______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
(ACQUISITION1)
(CONVERSION1)
(ACQUISITION2)
CS
SCLK
DOUT
MSB1
LSB1
MSB2
EOC
X = DON'T CARE.
Figure 9. Clock Mode 11—Externally Timed Acquisition, Sampling, and Conversion Without CNVST
DAC/GPIO Timing
Figures 10–13 detail the timing diagrams for writing to
the DAC and GPIOs. Figure 10 shows the timing specifications for clock modes 00, 01, and 10. Figure 11
shows the timing specifications for clock mode 11.
Figure 12 details the timing specifications for the DAC
input select register and 2 bytes to follow. Output data
is updated on the rising edge of SCLK in clock mode
11. Figure 13 shows the GPIO timing. Figure 14 shows
the timing details of a hardware LDAC command DACregister update. For a software-command DAC-register
update, tS is valid from the rising edge of CS, which follows the last data bit in the software command word.
LDAC Functionality
Drive LDAC low to transfer the content of the input
registers to the DAC registers. Drive LDAC permanently
low to make the DAC register transparent. The DAC
output typically settles from zero to full scale within ±1
LSB after 2µs. See Figure 14.
Layout, Grounding, and Bypassing
For best performance, use PC boards. Ensure that digital and analog signal lines are separated from each
other. Do not run analog and digital signals parallel to
one another (especially clock signals) or do not run digital lines underneath the MAX1021/MAX1043
package. High-frequency noise in the AV DD power
supply may affect performance. Bypass the AVDD supply with a 0.1µF capacitor to AGND, close to the AVDD
pin. Bypass the DVDD supply with a 0.1µF capacitor to
DGND, close to the DVDD pin. Minimize capacitor lead
lengths for best supply-noise rejection. If the power
supply is very noisy, connect a 10Ω resistor in series
with the supply to improve power-supply filtering.
The MAX1021/MAX1043 thin QFN packages contain an
exposed pad on the underside of the device. Connect
this exposed pad to AGND. Refer to the MAX1258 EV kit
for an example of proper layout.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. INL for
the MAX1021/MAX1043 is measured using the endpoint method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Unipolar ADC Offset Error
For an ideal converter, the first transition occurs at 0.5
LSB, above zero. Offset error is the amount of deviation
between the measured first transition point and the
ideal first transition point.
______________________________________________________________________________________
35
MAX1021/MAX1043
(CONVERSION BYTE)
DIN
MAX1021/MAX1043
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
tCL
SCLK
1
tDS
2
3
D13
D14
D12
D11
D1
D0
tDOT
tDOE
D15
D7
DOUT
32
16
8
5
4
tDH
D15
DIN
tCH
D14
D6
D13
D5
tDOD
D12
D4
D1
D0
tCSS
tCSPWH
tCSH
CS
Figure 10. DAC/GPIO Serial-Interface Timing (Clock Modes 00, 01, and 10)
Bipolar ADC Offset Error
Aperture Jitter
While in bipolar mode, the ADC’s ideal midscale transition occurs at AGND -0.5 LSB. Bipolar offset error is the
measured deviation from this ideal value.
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.
ADC Gain Error
Aperture delay (t AD ) is the time between the rising
edge of the sampling clock and the instant when an
actual sample is taken.
Gain error is defined as the amount of deviation
between the ideal transfer function and the measured
transfer function, with the offset error removed and with
a full-scale analog input voltage applied to the ADC,
resulting in all ones at DOUT.
DAC Offset Error
DAC offset error is determined by loading a code of
all zeros into the DAC and measuring the analog
output voltage.
DAC Gain Error
DAC gain error is defined as the amount of deviation
between the ideal transfer function and the measured
transfer function, with the offset error removed, when
loading a code of all ones into the DAC.
36
Aperture Delay
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analogto-digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N bits):
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise. RMS noise
includes all spectral components to the Nyquist
frequency excluding the fundamental, the first five
harmonics, and the DC offset.
______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
MAX1021/MAX1043
tCH
tCL
SCLK
1
2
3
32
16
8
5
4
tDH
tDS
D15
DIN
D14
D13
D12
D11
D1
D0
tDOE
tDOT
D15
D7
DOUT
D14
D6
tDOD
D13
D5
D12
D4
D1
D0
tCSS
tCSPWH
tCSH
CS
Figure 11. DAC/GPIO Serial-Interface Timing (Clock Mode 11)
SCLK
DIN
1
2
BIT 7 (MSB)
8
BIT 6
BIT 0 (LSB)
10
9
BIT 15
BIT 14
24
BIT 1
BIT 0
DOUT
THE COMMAND BYTE
INITIALIZES THE DAC SELECT
REGISTER
THE NEXT 16 BITS SELECT THE DAC
AND THE DATA WRITTEN TO IT
CS
Figure 12. DAC-Select Register Byte and DAC Serial-Interface Word
______________________________________________________________________________________
37
MAX1021/MAX1043
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
CS
tGOD
tGSU
GPIO INPUT/OUTPUT
Figure 13. GPIO Timing
tLDACPWL
LDAC
tS
±1 LSB
OUT_
Figure 14. LDAC Functionality
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
SINAD(dB) = 20 x log (SignalRMS / NoiseRMS)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the ENOB as follows:
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
THD = 20 x log⎡
⎣⎢
38
(V22 + V32 + V42 + V52 + V62) / V1⎤⎦⎥
where V1 is the fundamental amplitude, and V2 through
V6 are the amplitudes of the first five harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next largest distortion
component.
ADC Channel-to-Channel Crosstalk
Bias the ON channel to midscale. Apply a full-scale sine
wave test tone to all OFF channels. Perform an FFT on
the ON channel. ADC channel-to-channel crosstalk is
expressed in dB as the amplitude of the FFT spur at the
frequency associated with the OFF channel test tone.
Intermodulation Distortion (IMD)
IMD is the total power of the intermodulation products
relative to the total input power when two tones, f1 and
f2, are present at the inputs. The intermodulation products are (f1 ± f2), (2 x f1), (2 x f2), (2 x f1 ± f2), (2 x f2 ±
f1). The individual input tone levels are at -7dBFS.
______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
DAC Digital Feedthrough
DAC digital feedthrough is the amount of noise that
appears on the DAC output when the DAC digital control lines are toggled.
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as fullpower input bandwidth frequency.
ADC Power-Supply Rejection
ADC power-supply rejection (PSR) is defined as the
shift in offset error when the power supply is moved
from the minimum operating voltage to the maximum
operating voltage.
DAC Power-Supply Rejection
DAC PSR is the amount of change in the converter’s
value at full-scale as the power-supply voltage changes
from its nominal value. PSR assumes the converter’s linearity is unaffected by changes in the powersupply voltage.
28
29
30
31
32
EOC
DVDD
3
DGND
DOUT
5
SCLK
DIN
OUT0
7
21
8
20
9
19
OUT7
27
2
26
25
24
23
AIN1
AIN2
AIN3
AIN4
N.C.
N.C.
24 GPIOC0
DGND 5
23 N.C.
MAX1043
DOUT 6
22 RES_SEL
SCLK 7
21 CS
DIN 8
20 LDAC
OUT0 9
D.C.
D.C.
D.C.
N.C.
AGND
AVDD
OUT1
THIN QFN
(6mm x 6mm x 0.8mm)
Package Information
Chip Information
TRANSISTOR COUNT: 58,141
PROCESS: BiCMOS
OUT3
18
OUT6
THIN QFN
OUT2
17
10 11 12 13 14 15 16 17 18
OUT5
19 D.C.
16
15
25 GPIOC1
DVDD 4
11
14
26 REF1
EOC 3
10
12
27 AIN0
GPIOA1 2
OUT2
OUT3
AVDD
AGND
N.C.
OUT4
22
GPIOA0 1
OUT1
13
MAX1021
6
AIN5
36 35 34 33 32 31 30 29 28
1
4
REF2/AIN6
N.C.
N.C.
AIN4
AIN3
AIN2
AIN1
33
TOP VIEW
AIN0
REF1
GPIOC1
GPIOC0
N.C.
RES_SEL
CS
LDAC
GPIOA0
GPIOA1
CNVST/AIN7
REF2/AIN6
AIN5
34
CNVST/AIN7
35
TOP VIEW
36
Pin Configurations
For the latest package outline information, go to
www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
36 TQFN
T3666-3
21-0141
______________________________________________________________________________________
39
MAX1021/MAX1043
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC so the signal’s slew rate does not limit the ADC’s
performance. The input frequency is then swept up to
the point where the amplitude of the digitized conversion result has decreased by -3dB. Note that the T/H
performance is usually the limiting factor for the smallsignal input bandwidth.
MAX1021/MAX1043
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Revision History
REVISION
NUMBER
REVISION
DATE
1
3/08
DESCRIPTION
Changed timing characteristic specification
PAGES
CHANGED
7
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implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products.