19-0183; Rev 0; 9/93 Ultra High-Speed, High-Resolution, Single-/Dual-Supply TTL Comparators These comparators operate either from dual supplies or from a single +5V supply. The input common-mode voltage range extends below the negative supply rail, allowing ground-sensing applications with a single +5V supply. The MAX915 is a single TTL comparator, available in 8-pin DIP and SO packages. The MAX916 is a dual version available in 16-pin DIP and SO packages. For equivalent devices with complementary ECL outputs and 2ns propagation delay, see the single/dual MAX905/MAX906. ________________________Applications ____________________________Features ♦ Oscillation Free: Clocked Architecture ♦ 6ns Propagation Delay ♦ Propagation Delay Insensitive to Overdrive ♦ Single +5V or Dual ±5V Supplies ♦ 2mV Input Resolution (MAX915) ♦ Input Range Includes Negative Supply Rail ♦ Low Power: 14mA (70mW) per Comparator, +5V ♦ 1.5ns Setup Time with 5mV Overdrive ♦ No Minimum Requirement for Input Signal Slew Rate ♦ Complementary TTL Outputs ______________Ordering Information High-Speed A/D Converters TEMP. RANGE PIN-PACKAGE High-Speed Line Receivers MAX915CPA PART 0°C to +70°C 8 Plastic DIP Peak Detectors MAX915CSA MAX915C/D MAX915EPA MAX915ESA MAX915MJA MAX916CPE MAX916CSE MAX916C/D MAX916EPE MAX916ESE 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C -55°C to +125°C 0°C to +70°C 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C Threshold Detectors High-Speed Triggers Synchronous Data Discriminators _________________Pin Configurations V+ 1 8 IN+ 2 7 Q IN- 3 MAX915 V- 4 Q 6 GND 5 CLK 8 SO Dice* 8 Plastic DIP 8 SO 8 CERDIP 16 Plastic DIP 16 Narrow SO Dice* 16 Plastic DIP 16 Narrow SO * Contact factory for dice specifications. ________________Functional Diagram DIP/SO QA 1 16 QB QA 2 15 QB GND 3 CLKA 4 14 GND MAX916 N.C. 5 D Q MASTER D LATCH D CK Q IN- D Q SLAVE D LATCH D CK Q TTL OUTPUT STAGE Q Q 13 CLKB 12 N.C. V- 6 IN+ CLK 11 V+ INA- 7 10 INB- INA+ 8 9 INB+ INPUT AMPLIFIER MASTER/SLAVE FLIP-FLOP OUTPUT STAGE DIP/Narrow SO ________________________________________________________________ Maxim Integrated Products Call toll free 1-800-998-8800 for free samples or literature. 1 MAX915/MAX916 _______________General Description The MAX915/MAX916 high-speed, single and dual TTL voltage comparators eliminate oscillation by separating the comparator input and output stages with a negative edgetriggered master/slave flip-flop. Comparator propagation delay is typically 6ns, and is insensitive to input overdrive. The MAX915 and MAX916 resolve input signals as small as 2mV and 2.4mV, respectively. MAX915/MAX916 Ultra High-Speed, High-Resolution, Single-/Dual-Supply TTL Comparators ABSOLUTE MAXIMUM RATINGS Positive Supply Voltage (V+ to GND) ....................................+6V Negative Supply Voltage (V- to GND).....................................-6V Differential Input Voltage ......................(V- - 0.3V) to (V+ + 0.3V) Common-Mode Input Voltage ..............(V- - 0.3V) to (V+ + 0.3V) Clock Input Voltage..........................(GND - 0.3V) to (V+ + 0.3V) Output Short-Circuit Duration To V+, GND ............................................................Continuous To V- ................................................................................10sec Output Current (Q or Q) ......................................................20mA Continuous Power Dissipation (TA = +70°C) 8-Pin Plastic DIP (derate 9.09mW/°C above +70°C) ....727mW 8-Pin SO (derate 5.88mW/°C above +70°C).................471mW 8-Pin CERDIP (derate 8.00mW/°C above +70°C).........640mW 16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)....842mW 16-Pin Narrow SO (derate 8.70mW/°C above +70°C) ..696mW Storage Temperature Range .............................-65°C to +150°C Junction Temperature Range ............................-65°C to +170°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V+ = +5V, V- = -5V, TA = +25°C, unless otherwise noted.) PARAMETER Input Offset Voltage Input Bias Current SYMBOL CONDITIONS VOS VCM = 0V TYP MAX MAX915 MIN 0.5 1.5 MAX916 0.5 2.0 UNITS mV IB IB+ or IB- 5 10 µA Input Offset Current IOS VCM = 0V 0.2 1.0 µA Input Referred Noise Voltage en (Note 1) 600 900 µV Input Common-Mode Range VCMR Common-Mode Rejection Ratio CMRR (Note 2) Power-Supply Rejection Ratio V- - 0.1 PSRR (Note 3) Output High Voltage VOH (Note 4) Output Low Voltage VOL (Note 4) Clock Input Voltage High VIH Clock Input Voltage Low VIL Clock Input Current High IIH Clock Input Current Low IIL Positive Supply Current (Note 5) I+ Negative Supply Current (Note 5) I- Power Dissipation (Note 5) Propagation Delay (Notes 6, 7, 9) Propagation-Delay Skew Clock Setup Time (Notes 6, 9) 2 2.8 V+ - 2.2 V 90 120 µV/V 60 120 µV/V 3.5 0.3 V 0.4 2 V 0.8 V 0.5 10 µA µA 2.5 10 MAX915 14 18 MAX916 28 36 MAX915 3 4 MAX916 6 8 MAX915 85 115 MAX916 170 230 PD V+ = 5.25V, V- = -5.25V tPD+ Q, Q rising 6 8 tPD- Q, Q falling 6 8 (Notes 6, 7, 8) 0.5 3.0 VOD = 5mV 1.5 VOD = 10mV 1.0 tSKEW tSU V _______________________________________________________________________________________ 2.0 mA mA mW ns ns ns Ultra High-Speed, High-Resolution, Single-/Dual-Supply TTL Comparators (V+ = +5V, V- = -5V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Input Offset Voltage Input Bias Current SYMBOL CONDITIONS VOS VCM = 0V TYP MAX MAX915 MIN 0.5 2.0 MAX916 0.5 3.0 UNITS mV IB IB+ or IB- 5 15 µA Input Offset Current IOS VCM = 0V 0.2 2.0 µA Input Referred Noise Voltage en (Note 1) 600 900 µV Input Common-Mode Range VCMR Common-Mode Rejection Ratio CMRR (Note 2) Power-Supply Rejection Ratio V- - 0.1 PSRR (Note 3) Output High Voltage VOH (Note 4) Output Low Voltage VOL (Note 4) Clock Input Voltage High VIH Clock Input Voltage Low VIL Clock Input Current High IIH Clock Input Current Low IIL Positive Supply Current (Note 5) I+ Negative Supply Current (Note 5) I- Power Dissipation (Note 5) Clock Setup Time (Notes 6, 9) Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: 60 150 µV/V 3.5 0.3 V 0.4 V V 0.5 15 µA µA 15 22 MAX916 28 44 MAX915 3 6 MAX916 6 12 MAX915 85 150 MAX916 170 300 MAX91_C 6 10 MAX91_E 6 12 MAX91_M 6 15 MAX91_C 6 10 MAX91_E 6 12 MAX91_M 6 15 (Notes 6, 7, 8) 0.5 4.0 VOD = 5mV 1.5 VOD = 10mV 1.0 Q, Q rising Q, Q falling V 0.8 14 tPD+ tSU µV/V 2.5 V+ = 5.25V, V- = -5.25V tSKEW 150 MAX915 Propagation Delay (Notes 6, 7, 9) Propagation-Delay Skew V 90 2 PD tPD- 2.8 V+ - 2.2 2.0 mA mA mW ns ns ns Guaranteed by design. Input referred noise voltage uncertainty is specified over the full bandwidth of the device. Common-mode rejection ratio is tested over the full common-mode range. The common-mode range for dual-supply operation is from (V- - 0.1V) to (V+ - 2.2V). The common-mode range for single-supply operation is from -0.1V to (V+ - 2.2V). Tested for 4.75V < V+ < 5.25V and -5.25V < V- < 0V. TTL output voltage high and low tested with V+ = 4.75V, IOH = 4mA, IOL = 8mA. I+, I-, and PD tested for worst-case condition of V+ = 5.25V and V- = -5.25V. Output not loaded. Guaranteed by design. Measured in a high-speed fixture with CL = 15pF, IQ = 2mA. See Figure 1 for timing parameter definitions. Guaranteed for both single- and dual-supply operation. Propagation delay measured with an input signal of 100mV, with 5mV overdrive. Propagation delay skew is defined as the difference in tPD for the complementary outputs, Q and Q (see Figure 1). Clock input voltage rise and fall times should not exceed 100ns for correct triggering of comparator. _______________________________________________________________________________________ 3 MAX915/MAX916 ELECTRICAL CHARACTERISTICS __________________________________________Typical Operating Characteristics (V+ = +5V, V- = -5V, TA = +25°C, unless otherwise noted.) tPD+ 7 VOD = 5mV CL = 15pF 5 25 -15 105 65 tPD+ 8 7 tPD- 6 10 100 1k 0 100k 10k 40 80 160 120 200 TEMPERATURE (°C) SOURCE RESISTANCE (Ω) CL (pF) CLOCK SETUP TIME vs. INPUT OVERDRIVE CLOCK SETUP TIME vs. TEMPERATURE COMMON-MODE REJECTION RATIO vs. TEMPERATURE 0.8 0.7 0.6 1.0 0.5 0 20 40 60 80 100 100 50 VOD = 5mV CL = 15pF CL = 15pF 0.5 MAX915-6 150 1.5 CMRR (µV/V) CLOCK SETUP TIME (ns) 0.9 200 MAX915-5 2.0 MAX915-4 1.0 0 -55 -15 25 65 -55 105 -15 25 65 105 INPUT OVERDRIVE (mV) TEMPERATURE (°C) TEMPERATURE (°C) POWER-SUPPLY REJECTION RATIO vs. TEMPERATURE INPUT OFFSET VOLTAGE vs. TEMPERATURE INPUT OFFSET CURRENT vs. TEMPERATURE 0.5 0.4 VOS (µV) 100 IOS (µA) 50 150 MAX915-10 100 MAX915-7 200 MAX915-8 0 9 5 1 -55 CLOCK SETUP TIME (ns) 10 tPD- 3 0 0.3 0.2 -50 50 0.1 -100 0 -55 -15 25 65 TEMPERATURE (°C) 4 VOD = 5mV PROPAGATION DELAY (ns) 9 10 MAX915-2 100 MAX915-1 VOD = 5mV CL = 15pF tSU (ns) PROPAGATION DELAY (ns) 13 11 PROPAGATION DELAY vs. CAPACITIVE LOAD CLOCK SETUP TIME vs. SOURCE RESISTANCE MAX915-3 PROPAGATION DELAY vs. TEMPERATURE PSRR (µV/V) MAX915/MAX916 Ultra High-Speed, High-Resolution, Single-/Dual-Supply TTL Comparators 105 0 -55 -15 25 65 TEMPERATURE (°C) 105 -55 25 -15 65 TEMPERATURE (°C) _______________________________________________________________________________________ 105 Ultra High-Speed, High-Resolution, Single-/Dual-Supply TTL Comparators INPUT BIAS CURRENTS vs. DIFFERENTIAL INPUT VOLTAGE INPUT BIAS CURRENT vs. COMMON-MODE INPUT VOLTAGE 20 MAX915-11 10 MAX915-9 10 MAX915-12 INPUT BIAS CURRENT vs. TEMPERATURE VIN+ +VIN- = 0V 8 8 16 6 6 12 IB (µA) 4 4 8 2 2 4 0 0 0 -55 -15 25 105 65 -5 -4 -3 -2 -1 OUTPUT VOLTAGE LOW vs. SINK CURRENT 1 2 3 0.3 3.6 0.2 3.4 0.1 3.2 2 4 8 6 10 2 CLOCK SETUP TIME AND PROPAGATION DELAY (Q RISING) 4 6 8 10 I+ 10 I- -15 -55 65 105 CLOCK SETUP TIME AND PROPAGATION DELAY (Q FALLING) tSKEW tSU tPDtPD+ tSKEW IN+ 50mV/div GND 5mV OVERDRIVE CLK 2V/div -5mV OVERDRIVE CLK 2V/div Q 2V/div Q 25 TEMPERATURE (°C) tPD+ IN+ 50mV/div 8 10 20 IOH (mA) tPD- 6 0 0 IOL (mA) tSU 4 15 3.0 0 2 SUPPLY CURRENT PER COMPARATOR vs. TEMPERATURE 5 0 0 OUTPUT VOLTAGE HIGH vs. SOURCE CURRENT I+, I- (mA) 3.8 -10 -8 -6 -4 -2 5 MAX915-14 MAX915-13 0.4 4 DIFFERENTIAL INPUT VOLTAGE, VIN+ – VIN- (V) 4.0 VOH (V) VOL (V) 0 VCM (V) TEMPERATURE (°C) 0.5 IN- MAX915-15 IB (µA) IB (µA) IN+ Q 2V/div Q 5ns/div 5ns/div _______________________________________________________________________________________ 5 MAX915/MAX916 ____________________________Typical Operating Characteristics (continued) (V+ = +5V, V- = -5V, TA = +25°C, unless otherwise noted.) MAX915/MAX916 Ultra High-Speed, High-Resolution, Single-/Dual-Supply TTL Comparators _____________________________________________________________Pin Descriptions MAX915 MAX916 PIN NAME FUNCTION 1 V+ Positive Supply 2 IN+ Noninverting Input 3 IN- Inverting Input 4 V- Negative Supply. Connect to GND for single-supply operation. PIN NAME FUNCTION 1 QA TTL Output, Channel A 2 QA Complementary TTL Output, Channel A 3 GND Ground 4 CLKA Clock Input, Channel A 5, 12 N.C. V- 5 CLK Clock Input 6 GND Ground 7 Q TTL Output 6 8 Q Complementary TTL Output 7 INA- Inverting Input, Channel A 8 INA+ Noninverting Input, Channel A 9 INB+ Noninverting Input, Channel B 10 INB- Inverting Input, Channel B No Connect. Not internally connected. Negative Supply. Connect to GND for single-supply operation. _______________Detailed Description 11 V+ The MAX915 (single) and MAX916 (dual) are very highspeed TTL-compatible comparators. Each has an internal negative edge-triggered master/slave D flip-flop, and complementary TTL outputs. Unlike other TTL comparators, this architecture breaks the input-to-output signal path to accomplish the following: 13 CLKB Clock Input, Channel B 14 GND Ground 15 QB Complementary TTL Output, Channel B 1) Prevent oscillations caused by unwanted parasitic feedback when the comparator is in its linear region. No minimum input slew rate is required. 16 QB TTL Output, Channel B 2) Maintain a constant propagation delay with varying input overdrive. The comparator can be divided into three stages, as shown in the Functional Diagram: 1) Input Amplifier 2) Master/Slave D Flip-Flop 3) TTL Output Stage Positive Supply The input amplifier has no built-in hysteresis. External resistors should not be connected with the aim of creating hysteresis. The master/slave flip-flop makes hysteresis unnecessary, and impossible to add externally. Resolution Input Amplifier The comparator input amplifier is fully differential. Input offset voltage is trimmed to less than 1.5mV (MAX915) or 2mV (MAX916) at +25°C. Input common-mode range extends from 100mV below the negative supply rail (V-) to 2.2V below the positive supply (V+). Total commonmode input voltage range is 7.9V when operating from ±5V supplies. 6 A comparator’s ability to resolve small signal differences— its resolution—is affected by various factors. The most significant of these are: input offset voltage (V OS), input referred noise (en), common-mode rejection error, and power-supply rejection error. If the source has a high impedance, input bias and offset currents may also impact resolution. Avoid unbalanced source impedances. _______________________________________________________________________________________ Ultra High-Speed, High-Resolution, Single-/Dual-Supply TTL Comparators VOD DIFFERENTIAL VIN MAX915/MAX916 The MAX915 can compare input signals as small as 2.0mV over the entire common-mode voltage range (TA = +25°C). Similarly, the MAX916 can resolve input signals of less than 2.4mV (see Table 1). VOS tSU Master/Slave D Flip-Flop The negative edge-triggered master/slave D flip-flop incorporates two D latches, which makes propagation delay independent of input overdrive (VOD). When open, the master latch samples the output of the input amplifier; when closed, it holds the sampled data. When open, the slave latch samples the output of the master latch; when closed, it holds the sampled data. The master and slave latches are open on opposite phases of the clock, preventing a direct path from input to output at all times. This makes the MAX915 and MAX916 different from comparators with simple output latches, and delivers high-speed performance without oscillations, even with slow-moving input signals. The input amplifier continuously monitors the input signal. The master latch samples the output of the input amplifier when the clock is high. The data is held by the master latch and is transferred to the slave latch only on the clock’s falling edge. The TTL outputs do not change on the clock’s rising edge. Clock Cycle When the clock is high, the master stage is transparent, and the data at the slave output is latched. On the clock’s falling edge, the input data is latched into the master stage, just before the slave stage becomes transparent and the new data becomes valid at the output. On the clock’s rising edge, the slave latches the data at its input (which is also present at the flip-flop’s output), just before the master becomes transparent to new data 50% CLK tPD+ 50% Q tSKEW Q 50% tPD- Figure 1. Timing Diagram at its input. Thus the comparator’s inputs are sampled and the new data is transferred to the TTL outputs on the falling edge of the clock. TTL Output Stage The complementary TTL outputs can drive high-speed Schottky TTL with a fan-out of four. __________Applications Information Maximum Clock Rate The maximum permitted clock rate exceeds 50MHz and is a function of the device’s propagation delay. The maximum output toggle rate is half the clock frequency because the comparator triggers only on the falling edge of each clock cycle. Table 1. Input-Referred Error/Resolution TEMPERATURE TA = +25°C TA = TMIN to TMAX ERROR/RESOLUTION MAX915 MAX916 UNITS RMS error 2.0 2.4 mV Worst-case error 3.4 3.9 mV RSOURCE* 3.4 3.9 kΩ RMS error 2.5 3.4 mV Worst-case error 4.2 5.2 mV RSOURCE* 2.1 2.6 kΩ *RSOURCE is the balanced source resistance that will contribute the same input-referred error as the sum of the worst-case errors from the other four sources (VOS, CMRR, en, PSRR) _______________________________________________________________________________________ 7 MAX915/MAX916 Ultra High-Speed, High-Resolution, Single-/Dual-Supply TTL Comparators +5V +5V 100nF 100nF V+ V+ MAX915 IN+ IN- Q MAX915 IN+ Q IN- CLK Q Q CLK V- GND V- 100nF -5V CLK, Q, Q ARE TTL SIGNALS REFERRED TO GND. GND CLK, Q, Q ARE TTL SIGNALS REFERRED TO GND (V- = GND). Figure 2. Dual-Supply Operation Figure 3. Single-Supply Operation Power Supplies The MAX915/MAX916 are tested while operating from ±5V supplies, providing an input common-mode voltage range (VCMR) of 7.9V (-5.1V to +2.8V) (see Figure 2). Operation from a single +5V supply provides a VCMR from -0.1V to +2.2V below V+ (-0.1V to +2.8V). Connect V- to GND for single-supply operation (see Figure 3). Bypass V+ and V- to GND with 100nF ceramic capacitors placed very close to the IC supply pins. Keep the leads of through-hole capacitors as short as possible. Do not connect bypass capacitors directly from V+ to V-. ___________________Chip Topography The V+ supply provides power to the analog input stage and to the digital circuitry, whereas the V- supply only powers the analog section. Pay special attention to bypassing the V+ pin if the V+ supply is noisy. QA QA QB QB (V+) (Q) Input Slew Rate The MAX915/MAX916’s master/slave architecture eliminates the minimum input slew-rate requirement common to standard comparator architectures. As long as the comparator is clocked after the minimum data-to-clock setup time requirement, and the input is greater than the comparator’s total DC error, the output will be valid without oscillations. It is not necessary to bypass the input, even if the input signal is very slow moving. GND (Q) GND CLKA (IN+) (IN-) V- 0.085" (2.159mm) CLKB (GND) V+ Board Layout and Bypassing As with all high-speed components, careful high-speed board layout and bypassing are essential for optimal performance; although forgiving, the clocked architecture is not a substitute for good layout and decoupling. A printed circuit board with an unbroken ground plane is recommended. Pay close attention to the bandwidth of the bypass components, and keep ground leads short. Avoid sockets; solder the IC and other components directly to the board to minimize unwanted parasitic capacitance. INA- (V-) (CLK) INBINA+ INB+ 0.072" (1.829mm) ( ) INDICATE MAX915 CALLOUTS. TRANSISTOR COUNT: MAX915–82; MAX916–164; SUBSTRATE CONNECTED TO V-. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 ___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1993 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.