TSM917 Data Sheet

TSM917
1.8V Nanopower Comparator with Internal 1.245V Reference
FEATURES
♦ Second-source for MAX917
♦ Guaranteed to Operate Down to +1.8V
♦ Ultra-Low Supply Current: 750nA
♦ Internal 1.245V ±1.5% Reference
♦ Input Voltage Range Extends 200mV Outside-the-Rails
♦ No Phase Reversal for Overdriven Inputs
♦ Push-pull Output
♦ Crowbar-Current-Free Switching
♦ Internal Hysteresis for Clean Switching
♦ 5-pin SOT23 and 8-pin SOIC Packaging
APPLICATIONS
2-Cell Battery Monitoring/Management
Medical Instruments
Threshold Detectors/Discriminators
Sensing at Ground or Supply Line
Ultra-Low-Power Systems
Mobile Communications
Telemetry and Remote Systems
DESCRIPTION
The TSM917 nanopower analog comparator is
electrically and form-factor identical to the MAX917
analog comparator. Ideally suited for all 2-cell batterymanagement/monitoring applications, this 5-pin
SOT23 analog comparator guarantees +1.8V
operation, draws very little supply current, and has a
robust input stage that can tolerate input voltages
beyond its power supply. The TSM917 draws 750nA
of supply current and includes an on-board 1.245V
±1.5% reference.
The TSM917’s push-pull output drivers were
designed to drive 8mA loads from one supply rail to
the other supply rail. The TSM917 is also available in
an 8-pin SOIC package.
TYPICAL APPLICATION CIRCUIT
Page 1
© 2014 Silicon Laboratories, Inc. All rights reserved.
TSM917
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC to VEE) ............................................ +6V
Voltage Inputs (IN+, IN-, REF) .... (VEE - 0.3V) to (VCC + 0.3V)
Output Voltage
TSM917 ................................... (VEE - 0.3V) to (VCC + 0.3V)
Current Into Input Pins ................................................ ±20mA
Output Current ............................................................ ±50mA
Output Short-Circuit Duration ............................................ 10s
Continuous Power Dissipation (TA = +70°C)
5-Pin SC70 (Derate 2.5mW/°C above +70°C) ........ 200mW
8-Pin SOIC (Derate 5.88mW/°C above +70°C) ...... 471mW
Operating Temperature Range ...................... -40°C to +85°C
Junction Temperature ................................................ +150°C
Storage Temperature Range ....................... -65°C to +150°C
Lead Temperature (soldering, 10s) ............................... +300°
Electrical and thermal stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections
of the specifications is not implied. Exposure to any absolute maximum rating conditions for extended periods may affect device reliability and
lifetime.
PACKAGE/ORDERING INFORMATION
ORDER
NUMBER
PART
CARRIER QUANTITY
MARKING
ORDER
NUMBER
PART
CARRIER QUANTITY
MARKING
TSM917EUK+
Tape
& Reel
-----
TSM917ESA+
Tube
97
Tape
& Reel
3000
Tape
& Reel
2500
TAAA
TSM917EUK+T
TS917E
TSM917ESA+T
Lead-free Program: Silicon Labs supplies only lead-free packaging.
Consult Silicon Labs for products specified with wider operating temperature ranges.
Page 2
TSM917 Rev. 1.0
TSM917
ELECTRICAL CHARACTERISTICS
VCC = +5V, VEE = 0V, VIN+ = VREF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
See Note 1.
PARAMETER
SYMBOL
Supply Voltage Range
VCC
Supply Current
ICC
IN+ Voltage Range
VIN+
Input Offset Voltage
VOS
Input-Referred Hysteresis
VHB
Input Bias Current
Power-Supply Rejection Ratio
IB
PSRR
Output-Voltage Swing High
VCC - VOH
Output-Voltage Swing Low
VOL
Output Short-Circuit Current
ISC
High-to-Low Propagation Delay
(Note 4)
Low-to-High Propagation Delay
(Note 4)
Rise Time
Fall Time
tRISE
tFALL
Power-Up Time
tON
Reference Voltage
tPDtPD+
VREF
CONDITIONS
Inferred from the
PSRR test
VCC = 1.6V
MIN
TA = +25°C
TA = +25°C
TA = +25°C
VCC = 5V
TA = TMIN to TMAX
Inferred from the output swing test
TA = +25°C
(Note 2)
TA = TMIN to TMAX
(Note 3)
TA = +25°C
TA = TMIN to TMAX
VCC = 1.8V to 5.5V
TA = +25°C
VCC = 5V,
ISOURCE = 8mA
TA = TMIN to TMAX
TA = +25°C
VCC = 1.8V,
ISOURCE = 1mA
TA = TMIN to TMAX
TA = +25°C
VCC = 5V, ISINK = 8mA
TA = TMIN to TMAX
TA = +25°C
VCC = 1.8V,
ISINK = 1mA
TA = TMIN to TMAX
VCC = 5V
Sourcing, VO = VEE
VCC = 1.8V
VCC = 5V
Sinking, VO = VCC
VCC = 1.8V
VCC = 1.8V
VCC = 5V
VCC = 1.8V
VCC = 5V
CL = 15pF
CL = 15pF
0.75
0.80
VEE - 0.2
1
4
0.15
0.1
190
55
190
55
95
8
98
10
17
22
30
95
6
4
MAX
UNITS
5.5
V
1.30
1.60
VCC + 0.2
5
10
μA
1
2
1
400
500
200
300
400
500
200
300
ΔVREF/ ΔVCC
Reference Load Regulation
ΔVREF/ ΔIOUT ΔIOUT = 10nA
TCVREF
1.227
1.200
1.245
95
BW = 10Hz to 100kHz
BW = 10Hz to 100kHz, CREF = 1nF
VCC = 1.8V to 5.5V
600
215
0.1
±0.2
V
mV
mV
nA
mV/V
mV
mV
mA
µs
µs
µs
µs
1.2
TA = +25°C
TA = TMIN to TMAX
Reference Voltage
Temperature Coefficient
Reference Output Voltage
Noise
Reference Line Regulation
en
TYP
1.8
ms
1.263
1.290
V
ppm/°C
µVRMS
mV/V
mV/nA
Note 1: All specifications are 100% tested at TA = +25°C. Specification limits over temperature (TA = TMIN to TMAX) are guaranteed by
design, not production tested.
Note 2: VOS is defined as the center of the hysteresis band at the input.
Note 3: The hysteresis-related trip points are defined by the edges of the hysteresis band, measured with respect to the center of the
hysteresis band (i.e., VOS) (See Figure 2).
Note 4: Specified with an input overdrive (VOVERDRIVE) of 100mV, and load capacitance of CL = 15pF. VOVERDRIVE is defined above and
beyond the offset voltage and hysteresis of the comparator input. For the TSM917, reference voltage error should also be
added.
TSM917 Rev. 1.0
Page 3
TSM917
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = +5V; VEE = 0V; CL = 15pF; VOVERDRIVE = 100mV; TA = +25°C, unless otherwise noted.
Supply Current
vs Supply Voltage and Temperature
Supply Current vs Temperature
1.3
1.1
SUPPLY CURENT - µA
SUPPLY CURENT - µA
1
1.1
TA = +85°C
0.9
0.7
TA = +25°C
TA = -40°C
0.5
0.9
VCC =+5V
0.8
VCC =+3V
0.7
0.6
VCC =+1.8V
0.5
0.4
1.5
2.5
4.5
3.5
5.5
-40
-15
Supply Current vs Output Transition Frequency
85
Output Voltage Low vs. Sink Current
35
250
30
VCC =+1.8V
200
25
VCC =+5V
20
15
VOL - mV
SUPPLY CURRENT - nA
60
TEMPERATURE - °C
SUPPLY VOLTAGE - Volt
VCC =+3V
10
VCC =+1.8V
5
150
VCC =+5V
VCC =+3V
100
50
0
0
1
10
1k
100
10k
0
2
OUTPUT TRANSITION FREQUENCY - Hz
8
10
12
14
16
0.5
VCC =+1.8V
TA = +85°C
VCC =+3V
0.4
VCC – VOH - V
200
TA = +25°C
VOL - mV
6
Output Voltage High vs Source Current
And
300
4
SINK CURRENT- mA
Output Voltage Low
vs. Sink Current and Temperature
100
TA = -40°C
0.3
VCC =+5V
0.2
0.1
0
0
0
2
4
6
8
10
12
SINK CURRENT- mA
Page 4
35
10
14
16
0
2
4
6
8 10 12 14 16 18 20
SOURCE CURRENT- mA
TSM917 Rev. 1.0
TSM917
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = +5V; VEE = 0V; CL = 15pF; VOVERDRIVE = 100mV; TA = +25°C, unless otherwise noted.
Output Voltage High
Short-Circuit Sink Current vs Temperature
vs Source Current and Temperature
0.6
120
0.5
100
SINK CURRENT- mA
VCC – VOH - V
TA = +85°C
0.4
0.3
TA = +25°C
0.2
TA = -40°C
0.1
0
VCC =+5V
80
60
VCC =+3V
40
VCC =+1.8V
20
0
4
8
12
16
0
20
-40
85
2.6
120
2.4
100
VCC =+5V
VOS - mV
SOURCE CURRENT- mA
60
Offset Voltage vs Temperature
Short-Circuit Source Current vs Temperature
140
80
60
VCC =+3V
0
-15
10
35
VCC =+1.8V, 3V
2.0
1.6
VCC =+1.8V
-40
2.2
1.8
40
20
60
1.4
85
VCC =+5V
-40
TEMPERATURE - °C
-15
10
35
60
85
TEMPERATURE - °C
Reference Voltage vs Temperature
Hysteresis Voltage vs Temperature
1.246
5.5
REFERENCE VOLTAGE - V
5
4.5
VHB - mV
35
TEMPERATURE - °C
SOURCE CURRENT- mA
4
3.5
3
2.5
10
-15
-40
-15
10
35
TEMPERATURE - °C
TSM917 Rev. 1.0
60
85
VCC =+1.8V
1.245
1.244
VCC =+3V
1.243
VCC =+5V
1.242
1.241
-40
-15
10
35
60
85
TEMPERATURE - °C
Page 5
TSM917
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = +5V; VEE = 0V; CL = 15pF; VOVERDRIVE = 100mV; TA = +25°C, unless otherwise noted.
Reference Voltage vs Reference Source Current
Reference Voltage vs Supply Voltage
1.246
REFERENCE VOLTAGE - V
REFERENCE VOLTAGE - V
1.246
1.245
1.244
1.243
1.242
1.241
1.5
2.5
3.5
4.5
1.244
1.243
VCC =+1.8V
VCC =+5V
1.242
VCC =+3V
1.241
1.240
1.239
5.5
0
4
2
10
SOURCE CURRENT- nA
Reference Voltage vs Reference Sink Current
Propagation Delay (tPD-) vs Temperature
30
20
tPD- - µs
1.2485
VCC =+5V
1.2475
1.2465
VCC =+3V
15
VCC =+1.8V
10
VCC =+3V
1.2455
5
1.2445
1.2435
VCC =+5V
25
VCC =+1.8V
1.2495
0
2
4
6
8
0
-40
10
-15
10
35
60
85
TEMPERATURE - °C
SINK CURRENT- nA
Propagation Delay (tPD+) vs Temperature
Propagation Delay (tPD-) vs Capacitive Load
140
100
120
VCC =+5V
80
VCC =+3V
60
80
tPD- - µs
100
tPD+ - µs
8
6
SUPPLY VOLTAGE - Volt
1.2515
6
1.2505
REFERENCE VOLTAGE - V
1.245
60
VCC =+1.8V
VCC =+3V
40
VCC =+5V
40
VCC =+1.8V
20
20
0
-40
-15
10
35
TEMPERATURE - °C
Page 6
60
85
0
0.01
0.1
1
10
100
1000
CAPACITIVE LOAD - nF
TSM917 Rev. 1.0
TSM917
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = +5V; VEE = 0V; CL = 15pF; VOVERDRIVE = 100mV; TA = +25°C, unless otherwise noted.
Propagation Delay (tPD+) vs Capacitive Load
Propagation Delay (tPD-) vs Input Overdrive
160
90
VCC =+5V
140
80
VCC =+3V
120
70
tPD- - µs
tPD+ - µs
100
80
60
40
0.1
1
VCC =+1.8V
40
20
0
0.01
VCC =+3V
50
30
VCC =+1.8V
20
VCC =+5V
60
10
100
10
1000
CAPACITIVE LOAD - nF
0
10
20
30
40
50
INPUT OVERDRIVE - mV
Propagation Delay (tPD-) at VCC = +5V
Propagation Delay (tPD+) vs Input Overdrive
140
INPUT
120
VCC =+3V
80
60
OUTPUT
tPD+ - µs
VCC =+5V
100
VCC =+1.8V
40
0
10
20
30
40
50
20µs/DIV
Propagation Delay (tPD+) at VCC = +5V
Propagation Delay (tPD-) at VCC = +3V
OUTPUT
OUTPUT
INPUT
INPUT
INPUT OVERDRIVE - mV
20µs/DIV
TSM917 Rev. 1.0
20µs/DIV
Page 7
TSM917
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = +5V; VEE = 0V; CL = 15pF; VOVERDRIVE = 100mV; TA = +25°C, unless otherwise noted.
Propagation Delay (tPD-) at VCC = +1.8V
INPUT
OUTPUT
OUTPUT
INPUT
Propagation Delay (tPD+) at VCC = +3V
Propagation Delay (tPD+) at VCC = +1.8V
10kHz Transient Response at VCC = +1.8V
OUTPUT
OUTPUT
INPUT
20µs/DIV
INPUT
20µs/DIV
20µs/DIV
20µs/DIV
Power-Up/Power-Down Transient Response
OUTPUT
OUTPUT
INPUT
INPUT
1kHz Transient Response at VCC = +5V
200µs/DIV
Page 8
0.2s/DIV
TSM917 Rev. 1.0
TSM917
PIN FUNCTIONS
TSM917
5-pin
8-pin
SOT23
SOIC
1
6
2
4
3
3
NAME
OUT
VEE
IN+
4
2
REF
5
—
—
7
—
1, 5, 8
VCC
INNC
FUNCTION
Comparator Output
Negative Supply Voltage
Comparator Noninverting Input
1.245V Reference Output and
Comparator Inverting Input
Positive Supply Voltage
Comparator Inverting Input
No Connection. Not internally connected.
BLOCK DIAGRAMS
DESCRIPTION OF OPERATION
Guaranteed to operate from +1.8V supplies, the
TSM917 analog comparator only draws 750nA
supply current, features a robust input stage that can
tolerate input voltages 200mV beyond the power
supply rails, and includes an on-board +1.245V
±1.5% voltage reference. To insure clean output
switching behavior, the TSM917 features 4mV
internal hysteresis. The TSM917’s push-pull output
drivers were designed to minimize supply-current
surges while driving ±8mA loads with rail-to-rail
output swings.
TSM917 Rev. 1.0
Input Stage Circuitry
The robust design of the analog comparator’s input
stage can accommodate any differential input
voltage from VEE - 0.2V to VCC + 0.2V. Input bias
currents are typically ±0.15nA so long as the applied
input voltage remains between the supply rails. ESD
protection diodes - connected internally to the supply
rails - protect comparator inputs against overvoltage
conditions. However, if the applied input voltage
exceeds either or both supply rails, an increase in
input current can occur when these ESD protection
diodes start to conduct.
Page 9
TSM917
Output Stage Circuitry
Many conventional analog comparators can draw
orders of magnitude higher supply current when
switching. Because of this behavior, additional
power supply bypass capacitance may be required
to provide additional charge storage during
switching. The design of the TSM917’s rail-to-rail
output stage implements a technique that virtually
eliminates supply-current surges when output
transitions occur. As shown on Page 4 of the Typical
Operating Characteristics, the supply-current
change as a function of output transition frequency
exhibited by this analog comparator family is very
small. Material benefits of this attribute to batterypower applications are the increase in operating
time and in reducing the size of power-supply filter
capacitors.
TSM917’s Internal +1.245V VREF
The TSM917’s internal +1.245V voltage reference
exhibits a typical temperature coefficient of
95ppm/°C over the full -40°C to +85°C temperature
range. An equivalent circuit for the reference section
is illustrated in Figure 1. Since the output impedance
of the voltage reference is typically 200kΩ, its output
can be bypassed with a low-leakage capacitor and is
stable for any capacitive load. An external buffer –
Figure 1: TSM917’s Internal VREF Output
Equivalent Circuit
such as the TS1001 – can be used to buffer the
voltage reference output for higher output current
drive or to reduce reference output impedance.
APPLICATIONS INFORMATION
Low-Voltage, Low-Power Operation
Because it was designed specifically for any lowpower, battery-operated application, the TSM917
analog comparator is an excellent choice. Under
nominal conditions, approximate operating times for
this analog comparator is illustrated in Table 1 for a
number of battery types and their corresponding
charge capacities.
Internal Hysteresis
As a result of circuit noise or unintended parasitic
feedback, many analog comparators often break into
oscillation within their linear region of operation
especially when the applied differential input voltage
approaches 0V (zero volt). Externally-introduced
hysteresis is a well-established technique to
stabilizing analog comparator behavior and requires
external components. As shown in Figure 2, adding
comparator hysteresis creates two trip points: VTHR
(for the rising input voltage) and VTHF (for the falling
input voltage). The hysteresis band (VHB) is defined
as the voltage difference between the two trip points.
When a comparator’s input voltages are equal,
hysteresis effectively forces one comparator input to
Table 1: Battery Applications using the TSM917
Alkaline (2 Cells)
No
3.0
1.8
2000
TSM917
OPERATING TIME
(hrs)
2.5 x 106
Nickel-Cadmium (2 Cells)
Yes
2.4
1.8
750
937,500
Lithium-Ion (1 Cell)
Nickel-Metal- Hydride (2
Cells)
Yes
3.5
2.7
1000
1.25 x 106
Yes
2.4
1.8
1000
1.25 x 106
BATTERY TYPE
Page 10
RECHARGEABLE
VFRESH
(V)
VEND-OF-LIFE (V)
CAPACITY, AA
SIZE (mA-h)
TSM917 Rev. 1.0
TSM917
move quickly past the other input, moving the input
out of the region where oscillation occurs. Figure 2
illustrates the case in which an IN- input is a fixed
voltage and an IN+ is varied. If the input signals
were reversed, the figure would be the same with an
inverted output. To save cost and external pcb area,
an internal 4mV hysteresis circuit was added to the
TSM917.
point is (VREF - VOUT)/R2.
In solving for R2, there are two formulas –
one each for the two possible output states:
R2 = VREF/IR2
or
R2 = (VCC - VREF)/IR2
From the results of the two formulae, the
smaller of the two resulting resistor values is
chosen. For example, when using the
TSM917 (VREF = 1.245V) at a VCC = 3.3V
and if IR2 = 0.2μA is chosen, then the
formulae above produce two resistor values:
6.23MΩ and 10.24MΩ - the 6.2MΩ standard
value for R2 is selected.
Figure 2: TSM917’s Threshold Hysteresis Band
Adding Hysteresis to the TSM917
The TSM917 exhibits an internal hysteresis band
(VHB) of 4mV. Additional hysteresis can be
generated with three external resistors using positive
feedbackas shown in Figure 3. Unfortunately, this
method also reduces the hysteresis response time.
The design procedure below can be used to
calculate resistor values.
2) Next, the desired hysteresis band (VHYSB) is
set. In this example, VHYSB is set to 100mV.
3) Resistor R1 is calculated according to the
following equation:
R1 = R2 x (VHB/VCC)
and substituting the values selected in 1)
and 2) above yields:
R1 = 6.2MΩ x (100mV/3.3V) = 187.88kΩ
The 187kΩ standard value for R1 is
selected.
4) The trip point for VIN rising (VTHR) is chosen
such that VTHR > VREF x (R1 + R2)/R2 (where
VTHF is the trip point for VIN falling). This is
the threshold voltage at which the
comparator switches its output from low to
high as VIN rises above the trip point. In this
example, VTHR is set to 3V.
5) With the VTHR from Step 4 above, resistor R3
is then computed as follows:
Figure 3: Using Three Resistors Introduces Additional
Hysteresis in the TSM917.
1) Setting R2. As the leakage current at the IN
pin is under 2nA, the current through R2
should be at least 0.2μA to minimize offset
voltage errors caused by the input leakage
current. The current through R2 at the trip
TSM917 Rev. 1.0
R3 = 1/[VTHR/(VREF x R1) - (1/R1) - (1/R2)]
R3 = 1/[3V/(1.245V x 187kΩ) - (1/187kΩ)
- (1/6.2MΩ)] = 135.56kΩ
In this example, a 137kΩ, 1% standard
value resistor is selected for R3.
Page 11
TSM917
6) The trip voltages and hysteresis band
should be verified as follows:
For VIN rising: VTHR = VREF x R1 x [(1/R1)
+ (1 / R2) + (1 / R3)] = 3V
For VIN falling: VTHF = VTHR - (R1 x VCC/R2) =
2.9V
and Hysteresis Band = VTHR – VTHF = 100mV
Page 12
PC Board Layout and Power-Supply Bypassing
While power-supply bypass capacitors are not
typically required, it is always good engineering
practice to use 0.1uF bypass capacitors close to the
device’s power supply pins when the power supply
impedance is high, the power supply leads are long,
or there is excessive noise on the power supply
traces. To reduce stray capacitance, it is also good
engineering practice to make signal trace lengths as
short as possible. Also recommended are a ground
plane and surface mount resistors and capacitors.
TSM917 Rev. 1.0
TSM917
PACKAGE OUTLINE DRAWING
5-Pin SOT23 Package Outline Drawing
(N.B., Drawings are not to scale)
NOTES:
1. Dimensions and tolerances are as per ANSI Y14.5M, 1982.
2.80 - 3.00
2. Package surface to be matte finish VDI 11~13.
5
3. Die is facing up mold and facing down for trim/form,
ie, reverse trim/form.
0.95 0.950
TYP
4. The foot length measuring is based on the gauge plane method.
5. Dimensions are exclusive of mold flash and gate burr.
2.60 - 3.00
5
1.50 - 1.75
TYP
6. Dimensions are exclusive of solder plating.
7. All dimensions are in mm.
8. This part is compliant with EIAJ spec. and JEDEC MO-178 AA
0.30 - 0.50
9. Lead span/stand off height/coplanarity are considered as special
characteristic.
1.90 Max
10º TYP
1.50 – 1.75
10º TYP
0.09 – 1.45
0.60 – 0.80
0.90 - 1.30
0º- 8º
10º TYP
0.00 - 0.15
10º TYP
0.10 Max
5 0.09 - 0.20
0.25
Gauge Plane
0.30 - 0.55
0.50 – 0.70
0.50 Max
0.30 Min
0.20 Max
0.09 Min
TSM917 Rev. 1.0
Page 13
TSM917
PACKAGE OUTLINE DRAWING
8-Pin SOIC Package Outline Drawing
(N.B., Drawings are not to scale)
0.546 REF
0.33 - 0.51
5.80 – 6.20
1.27 TYP
4.80 - 5.00
LEADFARME
THICKNESS
0.19 – 0.25
1
1.32 – 1.52
7' REF ALL SIDE
1.75 Max
3.73 - 3.89
7' REF
ALL SIDE
2
0.48 Max
0.28 Min
45' Angle
0.76 Max
0.66 Min
GAUGE PLANE
3.81 – 3.99
0.25
0.10 – 0.25
0.10 Max
Notes:
1
Does not include mold flash, protrusions or gate burns.
Mold flash, protrusions or gate burrs shall not exceed
0.15 mm per side.
2
Does not include inter-lead flash or protrusions. Inter-lead
flash or protrusions shall not exceed 0.25 mm per side.
3.
Lead span/stand off height/coplanarity are considered as
special characteristic (s).
4.
Controlling dimensions are in mm.
5.
This part is compliant with JEDEC specification MS-012
6.
Lead span/stand off height/coplanarity are considered as
Special characteristic.
2
0 - 8°
0.406 – 0.863
Patent Notice
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