SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 D D D D D D D D D D D D D D D Organization: – DRAM: 262 144 by 16 Bits – SAM: 256 by 16 Bits Dual-Port Accessibility – Simultaneous and Asynchronous Access From the DRAM and SAM Ports Data-Transfer Function From the DRAM to the Serial-Data Register (4 × 4) × 4 Block-Write Feature for Fast Area-Fill Operations; as Many as Four Memory-Address Locations Written Per Cycle From the 16-Bit On-Chip Color Register Write-Per-Bit Feature for Selective Write to Each RAM I/O; Two Write-Per-Bit Modes to Simplify System Design Byte-Write Control (CASL, CASU) Provides Flexibility Extended Data Output for Faster System Cycle Time Enhanced Page-Mode Operation for Faster Access CAS-Before-RAS (CBR) and Hidden-Refresh Modes Long Refresh Period Every 8 ms (Maximum) Up to 45-MHz Uninterrupted Serial-Data Streams 256 Selectable Serial-Register Starting Locations SE-Controlled Register-Status QSF Split-Register-Transfer Read for Simplified Real-Time Register Load Performance Ranges: SMJ55161-75 SMJ55161-80 HKC PACKAGE ( TOP VIEW ) VCC TRG VSS SQ0 DQ0 SQ1 DQ1 VCC SQ2 DQ2 SQ3 DQ3 VSS SQ4 DQ4 SQ5 DQ5 VCC SQ6 DQ6 SQ7 DQ7 VSS CASL WE RAS A8 A7 A6 A5 A4 VCC D D D D D ACCESS TIME ROW ENABLE ta(R) (MAX) ACCESS TIME SERIAL DATA ta(SQ) (MAX) DRAM CYCLE TIME tc(W) (MIN) DRAM PAGE MODE tc(P) (MIN) 75 ns 80 ns 23 ns 25 ns 140 ns 150 ns 48 ns 50 ns 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SC SE VSS SQ15 DQ15 SQ14 DQ14 VCC SQ13 DQ13 SQ12 DQ12 VSS SQ11 DQ11 SQ10 DQ10 VCC SQ9 DQ9 SQ8 DQ8 VSS DSF NC / GND CASU QSF A0 A1 A2 A3 VSS Programmable Split-Register Stop Point 3-State Serial Outputs Allow Easy Multiplexing of Video-Data Streams All Inputs/Outputs and Clocks TTL Compatible Compatible With JEDEC Standards Designed to Work With the Texas Instruments Graphics Family OPERATING CURRENT OPERATING CURRENT SERIAL CYCLE TIME SERIAL PORT STAND- SERIAL PORT ACtc(SC) ICC1 ICC1A BY TIVE (MIN) (MAX) (MAX) 24 ns 30 ns 165 mA 160 mA 210 mA 195 mA Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PIN NOMENCLATURE A0 – A8 CASL, CASU DQ0 – DQ15 DSF NC/GND QSF RAS SC SE SQ0 – SQ15 TRG VCC VSS WE Address Inputs Column-Address Strobe / Byte Selects DRAM Data I/O, Write Mask Data Special-Function Select No Connect / Ground (Important: Not connected internally to VSS) Special-Function Output Row-Address Strobe Serial Clock Serial Enable Serial-Data Output Output Enable, Transfer Select 5-V Supply (TYP) Ground DRAM Write-Enable Select GB PACKAGE (BOTTOM VIEW ) J H G F E D C B A 1 2 2 3 4 POST OFFICE BOX 1443 5 6 7 8 • HOUSTON, TEXAS 77251–1443 9 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 GB Package Pin Assignments – By Location NO. PIN NAME NO. PIN NAME NO. PIN NAME NO. PIN NAME NO. PIN NAME NO. PIN NAME NO. PIN NAME NO. PIN NAME NO. PIN NAME J1 DQ1 J2 SQ3 J3 DQ3 J4 DQ4 J5 DQ5 J6 DQ6 J7 SQ7 J8 CASL J9 A8 H1 DQ0 H2 SQ2 H3 DQ2 H4 SQ4 H5 SQ5 H6 SQ6 H7 DQ7 H8 WE H9 A7 G1 SQ0 G2 SQ1 G3 VSS2 G6 VDD2 G7 RAS G9 A6 F2 F3 F8 A5 SC E2 VDD1 VSS1 F9 E1 VSS1 VDD1 VSS2 VDD1 G8 TRG VDD2 VDD1 G4 F1 E9 A4 D1 SE D2 SQ15 C2 VSS1 VSS1 D3 C1 C3 VDD1 VDD2 C4 B1 DQ15 B2 DQ14 B3 DQ13 A1 SQ14 A2 SQ13 A3 SQ12 F7 E8 D7 B4 VSS2 DQ12 C6 B5 DQ11 A4 SQ11 A5 SQ10 VSS1 VSS2 D8 A3 D9 A2 C8 CASU C9 A1 B7 SQ8 B8 DSF B9 A0 A7 DQ9 A8 DQ8 A9 QSF C7 B6 VDD2 DQ10 A6 SQ9 GB Package Pin Assignments – By Signal PIN NAME PIN NO. NAME A0 B9 A1 C9 A2 PIN PIN PIN PIN NO. NAME NO. NAME NO. NAME NO. NAME NO. DQ1 J1 DQ12 B4 SQ2 H2 SQ13 A2 H3 DQ13 B3 SQ3 J2 SQ14 A1 VDD2 VDD2 G6 DQ2 D9 DQ3 J3 DQ14 B2 SQ4 H4 SQ15 C1 F2 A3 D8 DQ4 J4 DQ15 B1 SQ5 H5 TRG F1 VSS1 VSS1 A4 E9 DQ5 J5 DSF B8 SQ6 H6 E2 A5 F9 DQ6 J6 QSF A9 SQ7 J7 VDD1 VDD1 A6 G9 DQ7 H7 RAS G8 SQ8 B7 D3 A7 H9 DQ8 A8 SC E1 SQ9 A6 VDD1 VDD1 F3 F7 A8 J9 DQ9 A7 SE D1 SQ10 A5 CASL J8 DQ10 B6 SQ0 G1 SQ11 A4 VDD1 VDD2 G3 CASU C8 DQ11 B5 SQ1 G2 SQ12 A3 VDD2 C3 DQ0 H1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 F8 VSS1 VSS1 C6 D2 C2 D7 VSS1 VSS2 G4 VSS2 VSS2 G7 VSS2 WE E8 C4 C7 H8 3 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 description The SMJ55161 multiport-video random-access memory (RAM) is a high-speed, dual-port memory device. It consists of a dynamic RAM (DRAM) module organized as 262 144 words of 16 bits each interfaced to a serial-data register (serial-access memory [SAM]) organized as 256 words of 16 bits each. The SMJ55161 supports three basic types of operation: random access to and from the DRAM, serial access from the serial register, and transfer of data from any row in the DRAM to the serial register. Except during transfer operations, the SMJ55161 can be accessed simultaneously and asynchronously from the DRAM and SAM ports. The SMJ55161 is equipped with several features designed to provide higher system-level bandwidth and to simplify design integration on both the DRAM and SAM ports. On the DRAM port, greater pixel-draw rates are achieved by the device’s (4 × 4) × 4 block-write feature. The block-write mode allows 16 bits of data (present in an on-chip color-data register) to be written to any combination of four adjacent column-address locations. As many as 64 bits of data can be written to memory during each CAS cycle time. Also, on the DRAM port, a write mask or a write-per-bit feature allows masking of any combination of the 16 inputs/outputs on any write cycle. The persistent write-per-bit feature uses a mask register that, once loaded, can be used on subsequent write cycles without reloading. The SMJ55161 also offers byte control which can be applied in read cycles, write cycles, block-write cycles, load-write-mask-register cycles, and load-color-register cycles. The SMJ55161 also offers extended-data-output (EDO) mode. The EDO mode is effective in both the page-mode and standard DRAM cycles. The SMJ55161 offers a split-register-transfer read (DRAM-to-SAM) feature for the serial register (SAM port) that enables real-time-register-load implementation for continuous serial-data streams without critical timing requirements. The register is divided into a high half and a low half. While one half is being read out of the SAM port, the other half can be loaded from the memory array. For applications not requiring real-time register load (for example, loads done during CRT-retrace periods), the full-register mode of operation is retained to simplify system design. The SAM port is designed for maximum performance. Data can be accessed from the SAM at serial rates up to 45 MHz. During the split-register-transfer read operations, internal circuitry detects when the last bit position is accessed from the active half of the register and immediately transfers control to the opposite half. A separate output, QSF, is included to indicate which half of the serial register is active. All inputs, outputs, and clock signals on the SMJ55161 are compatible with Series 74 TTL. All address lines and data-in lines are latched on-chip to simplify system design. All data-out lines are unlatched to allow greater system flexibility. The SMJ55161 is offered in a 68-pin ceramic pin-grid-array package (GB suffix) and a 64-pin ceramic flatpack (HKC suffix). The SMJ55161 and other TI multiport-video RAMs are supported by a broad line of graphic processors and control devices from TI. See Table 2 and Table 4 for additional information. 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 functional block diagram 1 of 4 Subblocks (see next page) Input Buffer DSF DRAM Input Buffer DQ0 – DQ15 SpecialFunction Logic Column Buffer 9 1 of 4 Subblocks (see next page) 16 A0 – A8 Row Buffer DRAM Output Buffer SC 1 of 4 Subblocks (see next page) SQ0 – SQ15 16 SerialAddress Counter SplitRegister Status SerialOutput Buffer QSF SE 1 of 4 Subblocks (see next page) RAS CASx TRG WE Refresh Counter SE Timing Generator POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 functional block diagram (continued) DSF Input Buffer SpecialFunction Logic Color Register DRAM Input Buffer DQi DQi+1 DQi+2 DQi+3 W/B Unlatch MUX W/B Latch Address Mask WritePer-Bit Control DRAM Output Buffer Column DEC RAS CASx TRG WE Column Buffer Sense AMP Timing Generator A0 – A8 512 × 512 Memory Array Row Buffer Row Decoder Serial -Data Register SC Serial - Data Pointer SQi SQi + 1 SQi +2 SQi + 3 SerialAddress Counter SerialOutput Buffer SE 1 of 4 Subblocks Refresh Counter SplitRegister Status QSF SE 6 9 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 functional operation description Table 1 lists the DRAM and SAM functions, summarizing Table 3 and Table 4. Table 1. DRAM and SAM Functions CASx FALL RAS FALL ADDRESS DQ0 – DQ15† FUNCTION Reserved (do not use) CBR refresh (no reset) and stop-point set¶ CBR refresh (option reset)|| CASx§ RAS CASL CASU WE X X X X X — H X Stop Point # X X X CBRS TRG WE DSF DSF L L L L L X L MNE CODE RAS CASx‡ L X H L X X X X X CBR CBR refresh (no reset)k L X H H X X X X X CBRN Full-register-transfer read H L H L X Row Address Tap Point X X RT Split-register-transfer read H L H H X Row Address Tap Point X X SRT DRAM write (nonpersistent write-per-bit) H H L L L Row Address Column Address Write Mask Valid Data RWM DRAM block write (nonpersistent write-per-bit) H H L L H Row Address Block Address A2 – A8 Write Mask Column Mask BWM DRAM write (persistent write-per-bit) H H L L L Row Address Column Address X Valid Data RWM DRAM block write (persistent write-per-bit) H H L L H Row Address Block Address A2 – A8 X Column Mask BWM DRAM write (nonmasked) H H H L L Row Address Column Address X Valid Data RW DRAM block write (nonmasked) H H H L H Row Address Block Address A2 – A8 X Column Mask BW Load write-mask registerh H H H H L Refresh Address X X Write Mask LMR Load color register H H H H H Refresh Address X X Color Data LCR Legend: Col Mask = H: Write to address/column enabled Write Mask = H: Write to I/O enabled X = Don’t care † DQ0 – DQ15 are latched on either the first falling edge of CASx or the falling edge of WE, whichever occurs later. ‡ Logic L is selected when either or both CASL and CASU are low. § The column address and block address are latched on the first falling edge of CASx. ¶ CBRS cycle should be performed immediately after the powerup initialization cycle. # A0 – A3, A8: don’t care; A4 – A7: stop-point code || CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode. k CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode. h Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option reset) cycle. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 pin definitions Table 2. Pin Description Versus Operational Mode PIN DRAM TRANSFER A0 – A8 Row, column address Row address, tap point CASL CASU Column-address strobe, DQ output enable Tap-address strobe DQ DRAM data I/O, write mask DSF Block-write enable Write-mask-register load enable Color-register load enable CBR (option reset) Split-register-transfer enable RAS Row-address strobe Row-address strobe SAM SE SQ output enable, QSF output enable SC Serial clock SQ Serial-data output TRG DQ output enable WE Write enable, write-per-bit enable Transfer enable QSF Special-function output NC/GND VCC† Either make no external connection or tie to system GND (VSS) Serial-register status 5-V supply † VSS Ground † For proper device operation, all VCC pins must be connected to a 5-V supply, and all VSS pins must be tied to ground. address (A0 – A8) Eighteen address bits are required to decode each one of the 262 144 storage cell locations. Nine row-address bits are set up on pins A0 – A8 and latched onto the chip on the falling edge of RAS. Nine column-address bits are set up on pins A0 – A8 and latched onto the chip on the first falling edge of CASx. All addresses must be stable on or before the falling edge of RAS and the first falling edge of CASx. During the full-register-transfer read operation, the states of A0 – A8 are latched on the falling edge of RAS to select one of the 512 rows where the transfer occurs. At the first falling edge of CASx, the column-address bits A0–A8 are latched. The most significant column-address bit (A8) selects which half of the row is transferred to the SAM. The appropriate 8-bit column address (A0 –A7) selects one of 256 tap points (starting positions) for the serial-data output. During the split-register-transfer read operation, address bit A7 is ignored at the falling edge of CASx. An internal counter selects which half of the register is used. If the high half of the SAM is currently in use, the low half of the SAM is loaded with the low half of the DRAM half row and vice versa. Column address (A8) selects the DRAM half row. The remaining seven address bits (A0 –A6) are used to select one of 127 possible starting locations within the SAM. Locations 127 and 255 are not valid tap points. row-address strobe (RAS) RAS is similar to a chip enable so that all DRAM cycles and transfer cycles are initiated by the falling edge of RAS. RAS is a control input that latches the states of the row address, WE, TRG, CASL, CASU, and DSF onto the chip to invoke DRAM and transfer-read functions of the SMJ55161. 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 column-address strobe (CASL, CASU) CASL and CASU are control inputs that latch the states of the column address and DSF to control DRAM and transfer functions of the SMJ55161. CASx also acts as output enable for the DRAM output pins DQ0 – DQ15. In DRAM operation, CASL enables data to be written to or read from the lower byte (DQ0 – DQ7), and CASU enables data to be written to or from the upper byte (DQ8 – DQ15). In transfer operations, address bits A0 – A8 are latched at the first falling edge of CASx as the start position (tap) for the serial-data output (SQ0 – SQ15). output enable/transfer select (TRG) TRG selects either DRAM or transfer operation as RAS falls. For DRAM operation, TRG must be held high as RAS falls. During DRAM operation, TRG functions as an output enable for the DRAM output pins DQ0 – DQ15. For transfer operation, TRG must be brought low before RAS falls. write-mask select, write enable (WE) In DRAM operation, WE enables data to be written to the DRAM. WE is also used to select the DRAM write-per-bit mode. Holding WE low on the falling edge of RAS invokes the write-per-bit operation. The SMJ55161 supports both the nonpersistent write-per-bit mode and the persistent write-per-bit mode. special-function select (DSF) The DSF input is latched on the falling edge of RAS or the first falling edge of CASx, similar to an address. DSF determines which of the following functions are invoked on a particular cycle: D D D D D D D CBR refresh with reset (CBR) CBR refresh with no reset (CBRN) CBR refresh with no reset and stop-point set (CBRS) Block write Loading write-mask register for the persistent write-per-bit mode (LMR) Loading color register for the block-write mode Split-register-transfer read DRAM data I/O, write mask data (DQ0 – DQ15) DRAM data is written or read through the common I/O DQ pins. The 3-state DQ-output buffers provide direct TTL compatibility (no pullup resistors) with a fanout of one Series 54 TTL load. Data out is the same polarity as data in. During a normal access cycle, the outputs remain in the high-impedance state until TRG is brought low. Data appears at the outputs until TRG returns high, CASx returns high following RAS returning high, or RAS returns high following CASx returning high. The write mask is latched into the device through the random DQ pins by the falling edge of RAS and is used on all write-per-bit cycles. In a transfer operation, the DQ outputs remain in the high-impedance state for the entire cycle. serial-data outputs (SQ0 – SQ15) Serial data is read from the SQ pins. The SQ output buffers provide direct TTL compatibility (no pullup resistors) with a fanout of one Series 54 TTL load. The serial outputs are in the high-impedance (floating) state as long as the serial-enable pin, SE, is high. The serial outputs are enabled when SE is brought low. serial clock (SC) Serial data is accessed out of the data register during the rising edge of SC. The SMJ55161 is designed to work with a wide range of clock duty cycles to simplify system design. There is no refresh requirement because the data registers that comprise the SAM are static. There is also no minimum SC-clock operating frequency. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 serial enable (SE) During serial-access operations, SE is used as an enable / disable for the SQ outputs. SE low enables the serial-data output while SE high disables the serial-data output. SE is also used as an enable / disable for output pin QSF. IMPORTANT: While SE is held high, the serial clock is not disabled. External SC pulses increment the internal serial-address counter regardless of the state of SE. This ungated serial-clock scheme minimizes access time of serial output from SE low because the serial-clock input buffer and the serial-address counter are not disabled by SE. special-function output (QSF) QSF is an output pin that indicates which half of the SAM is being accessed. When QSF is low, the serial-address pointer is accessing the lower (least significant) 128 bits of the serial register (SAM). When QSF is high, the pointer is accessing the higher (most significant) 128 bits of the SAM. During full-register-transfer operations, QSF can change state upon completing the cycle. This state is determined by the tap point loaded during the transfer cycle. QSF is enabled by SE; therefore, if SE is high, the QSF output is in the high-impedance state. no connect / ground (NC / GND) NC/ GND must be tied to system ground or left floating for proper device operation. 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 random access operation Table 3 lists the DRAM functions. Table 3. DRAM Functions CASx FALL RAS FALL ADDRESS DQ0 – DQ15† FUNCTION Reserved (do not use) CBR refresh (no reset) and stop-point set¶ CBR refresh (option reset)|| CBR refresh (no reset)k MNE CODE RAS CASx§ RAS CASL CASU WE X X X X X — H X Stop Point # X X X CBRS H L X X X X X CBR H H X X X X X CBRN Column Address Write Mask Valid Data RWM CASx‡ TRG WE DSF DSF L L L L L X L L X L X DRAM write (nonpersistent write-per-bit) H H L L L Row Address DRAM block write (nonpersistent write-per-bit) H H L L H Row Address Block Address A2 – A8 Write Mask Column Mask BWM DRAM write (persistent write-per-bit) H H L L L Row Address Column Address X Valid Data RWM DRAM block write (persistent write-per-bit) H H L L H Row Address Block Address A2 – A8 X Column Mask BWM DRAM write (nonmasked) H H H L L Row Address Column Address X Valid Data RW DRAM block write (nonmasked) H H H L H Row Address Block Address A2 – A8 X Column Mask BW Load write-mask register h H H H H L Refresh Address X X Write Mask LMR Load color register H H H H H Refresh Address X X Color Data LCR Legend: Col Mask = H: Write to address / column enabled Write Mask = H: Write to I/O enabled X = Don’t care † DQ0 – DQ15 are latched on either the first falling edge of CASx or the falling edge of WE, whichever occurs later. ‡ Logic L is selected when either or both CASL and CASU are low. § The column address and block address are latched on the first falling edge of CASx. ¶ CBRS cycle should be performed immediately after the power-up initialization cycle. # A0 – A3, A8: don’t care; A4 – A7: stop-point code || CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode. k CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode. h Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option reset) cycle. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 enhanced page mode Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. This mode eliminates the time required for row-address setup, row-address hold, and address multiplex. The maximum RAS low time and CAS page cycle time used determine the number of columns that can be accessed. Unlike conventional page-mode operations, the enhanced page mode allows the SMJ55161 to operate at a higher data bandwidth. Data retrieval begins as soon as the column address is valid rather than when CASx transitions low. A valid column address can be presented immediately after the row-address hold time has been satisfied, usually well in advance of the falling edge of CASx. In this case, data is obtained after ta(C) MAX ( access time from CASx low) if ta(CA) MAX (access time from column address) has been satisfied. refresh CAS-before-RAS (CBR) refresh CBR refreshes are accomplished by bringing either or both CASL and CASU low earlier than RAS. The external row address is ignored, and the refresh row address is generated internally. Three types of CBR refresh cycles are available. The CBR refresh (option reset) ends the persistent write-per-bit mode and the stop-point mode. The CBRN and CBRS refreshes (no reset) do not end the persistent write-per-bit mode or the stop-point mode. The 512 rows of the DRAM do not necessarily need to be refreshed consecutively as long as the entire refresh is completed within the required time period, trf(MA). The output buffers remain in the high-impedance state during the CBR refresh cycles regardless of the state of TRG. hidden refresh A hidden refresh is accomplished by holding both CASL and CASU low in the DRAM read cycle and cycling RAS. The output data of the DRAM read cycle remains valid while the refresh is carried out. Like the CBR refresh, the refreshed row addresses are generated internally during the hidden refresh. RAS-only refresh A RAS-only refresh is accomplished by cycling RAS at every row address. Unless CASx and TRG are low, the output buffers remain in the high-impedance state to conserve power. Externally-generated addresses must be supplied during RAS-only refresh. Strobing each of the 512 row addresses with RAS causes all bits in each row to be refreshed. 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 extended data output The SMJ55161 features EDO during DRAM accesses. While RAS and TRG are low, the DRAM output remains valid. The output remains valid even when CASx returns high until WE is low, TRG is high, or both CASx and RAS are high (see Figure 1 and Figure 2). The EDO mode functions during all read cycles including DRAM read, page-mode read, and read-modify-write cycles (see Figure 3). RAS CASx tdis(RH) DQ0 – DQ15 Valid Output tdis(G) TRG Figure 1. DRAM Read Cycle With RAS-Controlled Output RAS CASx tdis(CH) DQ0 – DQ15 Valid Output tdis(G) TRG Figure 2. DRAM Read Cycle With CASx-Controlled Output POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 13 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 extended-data output (continued) RAS CASx A0 – A8 Row Column Column ta(CP) ta(CA) ta(C) ta(C) ta(CA) th(CLQ) Valid Output DQ0 – DQ15 Valid Output TRG Figure 3. DRAM Page-Read Cycle With Extended Output 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 byte operation Byte operation can be applied in DRAM-read cycles, write cycles, block-write cycles, load-write-mask-register cycles, and load-color-register cycles. In byte operation, the column address (A0 –A8) is latched at the first falling edge of CASx. In read cycles, CASL enables the lower byte (DQ0 –DQ7) and CASU enables the upper byte (DQ8 – DQ15) (see Figure 4). RAS CASL CASU tsu(CA) th(CLCA) A0 – A8 Column Row ta(C) Lower Byte Output DQ0 – DQ7 ta(C) Upper Byte Output DQ8 – DQ15 ta(G) TRG Figure 4. Example of a Byte-Read Cycle POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 15 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 byte operation (continued) In byte-write operation, CASL enables data to be written to the lower byte (DQ0 –DQ7), and CASU enables data to be written to the upper byte (DQ8 – DQ15). In an early write cycle, WE is brought low prior to both CASx signals, and data setup and hold times for DQ0 – DQ15 are referenced to the first falling edge of CASx (see Figure 5). RAS WE CASL tsu(CA) CASU th(CLCA) A0 – A8 Row Column tsu(DCL) th(CLD) DQ0 – DQ15 Valid Input Figure 5. Example of an Early-Write Cycle 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 byte operation (continued) For late-write or read-modify-write cycles, WE is brought low after either or both CASL and CASU fall. The data is strobed in with data setup and hold times for DQ0 – DQ15 referenced to WE (see Figure 6). RAS CASL CASU WE tsu(DWL) th(WLD) DQ0 – DQ15 Valid Input Figure 6. Example of a Late-Write Cycle POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 17 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 write-per-bit The write-per-bit feature allows masking any combination of the 16 DQs on any write cycle. The write-per-bit operation is invoked when WE is held low on the falling edge of RAS. If WE is held high on the falling edge of RAS, the write operation is performed without any masking. The SMJ55161 offers two write-per-bit modes: nonpersistent write-per-bit and persistent write-per-bit. nonpersistent write-per-bit When WE is low on the falling edge of RAS, the write mask is reloaded. A 16-bit binary code (the write-per-bit mask) is input to the device through the DQ pins and latched on the falling edge of RAS. The write-per-bit mask selects which of the 16 I / Os are to be written and which are not. After RAS has latched the on-chip write-per-bit mask, input data is driven onto the DQ pins and is latched on either the first falling edge of CASx or the falling edge of WE, whichever occurs later. CASL enables the lower byte (DQ0 – DQ7) to be written through the mask and CASU enables the upper byte (DQ8 – DQ15) to be written through the mask. If a data low (write mask = 0) is strobed into a particular I / O pin on the falling edge of RAS, data is not written to that I / O. If a data high (write mask = 1) is strobed into a particular I / O pin on the falling edge of RAS, data is written to that I / O (see Figure 7). RAS CASL CASU WE tsu(DQR) th(WLD) th(RDQ) tsu(DWL) DQ0 – DQ15 Write Mask Valid Input Figure 7. Example of a Nonpersistent Write-Per-Bit (Late-Write) Operation 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 persistent write-per-bit The persistent write-per-bit mode is initiated by performing a load-write-mask-register (LMR) cycle. In the persistent write-per-bit mode, the write-per-bit mask is overwritten but remains valid over an arbitrary number of write cycles until another LMR cycle is performed or power is removed. The LMR cycle is performed using DRAM write-cycle timing with DSF held high on the falling edge of RAS and held low on the first falling edge of CASx. A binary code is input to the write-mask register via the random I / O pins and latched on either the first falling edge of CASx or the falling edge of WE, whichever occurs later. Byte write control can be applied to the write mask during the LMR cycle. The persistent write-per-bit mode can then be used in exactly the same way as the nonpersistent write-per-bit mode except that the input data on the falling edge of RAS is ignored. When the device is set to the persistent write-per-bit mode, it remains in this mode and is reset only by a CBR refresh ( option-reset) cycle (see Figure 8). Load-Write-Mask Register Persistent Write-Per-Bit CBR Refresh (option reset) RAS CASx A0 – A8 Refresh Address Row Column DSF WE DQ0 – DQ15 Write-Mask Data Valid Input Mask Data = 1: Write to I / O enabled = 0: Write to I / O disabled Figure 8. Example of a Persistent Write-Per-Bit Operation POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 19 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 block write The block-write feature allows up to 64 bits of data to be written simultaneously to one row of the memory array. This function is implemented as four columns by four DQs and repeated in four quadrants. In this manner, each of the four 1M-bit quadrants can have up to four consecutive columns written at a time with up to four DQs per column (see Figure 9). DQ15 DQ14 4th Quadrant DQ13 DQ12 DQ11 DQ10 3rd Quadrant DQ9 DQ8 One Row of 0 – 511 DQ7 DQ6 2nd Quadrant DQ5 DQ4 DQ3 DQ2 1st Quadrant DQ1 DQ0 Four Consecutive Columns of 0 – 511 Figure 9. Block-Write Operation Each 1M-bit quadrant has a 4-bit column mask to mask off and prevent any or all of the four columns from being written with data. Nonpersistent write-per-bit or persistent write-per-bit functions can be applied to the block-write operation to provide write-masking options. The DQ data is provided by 4 bits from the on-chip color register. Bits 0 – 3 from the 16-bit write-mask register, bits 0 – 3 from the 16-bit column-mask register, and bits 0 – 3 from the 16-bit color-data register configure the block write for the first quadrant, while bits 4 – 7, 8 – 11, and 12 – 15 of the corresponding registers control the other quadrants in a similar fashion (see Figure 10). 20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 block write (continued) DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 12 13 14 15 DQ9 DQ8 One Row of 0 – 511 DQ7 DQ6 8 9 10 11 DQ5 DQ4 DQ3 DQ2 4 5 6 7 DQ1 Column Mask DQ0 0 1 2 3 3 7 Write Mask 1 5 1 2 3 4 5 15 14 9 8 4 0 0 11 10 6 2 6 7 8 13 12 9 10 11 12 13 14 15 Color Register Figure 10. Block Write With Masks POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 21 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 block write (continued) A set of four columns makes a block, resulting in 128 blocks along one row. Block 0 comprises columns 0 – 3, block 1 comprises columns 4 – 7, block 2 comprises columns 8 – 11, etc., as shown in Figure 11. Block 0 ...................... Block 1 Block 127 One Row of 0 – 511 0 1 2 3 4 5 6 7 ........................... 511 Columns Figure 11. Block Columns Organization During block-write cycles, only the seven most significant column addresses (A2 – A8) are latched on the first falling edge of CASx to decode one of the 128 blocks. Address bits A0 – A1 are ignored. Each 1M-bit quadrant has the same block selected. A block-write cycle is entered in a manner similar to a DRAM write cycle except DSF is held high on the first falling edge of CASx. As in a DRAM write operation, CASL and CASU enable the corresponding lower and upper DRAM DQ bytes to be written. The column-mask data is input via the DQs and is latched on either the first falling edge of CASx or the falling edge of WE, whichever occurs later. The 16-bit color-data register must be loaded prior to performing a block write as described below. Refer to the write-per-bit section for details on use of the write-mask capability, allowing additional performance options. Example of block write: Block-write column address Color-data register Write-mask register Column-mask register = 110000000 (A0 – A8 from left to right) bit 0 = 1011 = 1110 = 1111 1st Quad 1011 1111 0000 2nd Quad 1100 1111 0111 3rd Quad bit 15 0111 1011 1010 4th Quad Column-address bits A0 and A1 are ignored. Block 0 (columns 0 – 3) is selected for each 1M-bit quadrant. The first quadrant has DQ0 – DQ2 written with bits 0 – 2 from the color-data register (101) to all four columns of block 0. DQ3 is not written and retains its previous data due to write-mask-register-bit 3 being 0. The second quadrant (DQ4 – DQ7) has all four columns masked off due to column-mask bits 4 – 7 being 0 so that no data is written. The third quadrant (DQ8 – DQ11 ) has its four DQs written with bits 8 – 11 from the color-data register (1100) to columns 1 – 3 of its block 0. Column 0 is not written and retains its previous data on all four DQs due to column-mask-register-bit 8 being 0. 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 block write (continued) The fourth quadrant (DQ12 – DQ15 ) has DQ12, DQ14, and DQ15 written with bits 12, 14, and 15 from the color-data register to column 0 and column 2 of its block 0. DQ13 retains its previous data on all columns due to the write mask. Columns 1 and 3 retain their previous data on all DQs due to the column mask. If the previous data for the quadrant is all 0s, the fourth quadrant contains the data pattern shown in Figure 12 after the block-write operation shown in the previous example. DQ15 1 DQ14 1 0 0 1 1 0 0 4th Quadrant DQ13 0 0 DQ12 0 0 0 0 Columns 0 1 2 3 0 0 Figure 12. Example of Fourth Quadrant After a Block-Write Operation load color register The load-color-register cycle is performed using normal DRAM write-cycle timing except that DSF is held high on the falling edges of RAS, CASL, and CASU. The color register is loaded from pins DQ0 – DQ15, which are latched on either the first falling edge of CASx or the falling edge of WE, whichever occurs later. If only one CASx is low, only the corresponding byte of the color register is loaded. When the color register is loaded, it retains data until power is lost or until another load-color-register cycle is performed (see Figure 13 and Figure 14 ). Load-Color-Register Cycle Block-Write Cycle (no write mask) Block-Write Cycle (load and use write mask) RAS CASx A0 – A8 1 2 3 2 3 WE TRG DSF DQ0 – DQ15 4 6 5 6 Legend: 1. Refresh address 2. Row address 3. Block address (A2 – A8) is latched on the first falling edge of CASx. 4. Color-register data 5. Write-mask data: DQ0 – DQ15 are latched on the falling edge of RAS. 6. Column-mask data: DQi – DQi+3 (i = 0, 4, 8, 12) are latched on either the first falling edge of CASx or the falling edge of WE, whichever occurs later. = don’t care Figure 13. Example of Block Writes POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 23 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 load color register (continued) Load-Write-Mask-Register Cycle Persistent Block-Write Cycle (use loaded write mask) Load-Color-Register Cycle RAS CASx A0 – A8 1 2 1 3 WE TRG DSF DQ0 – DQ15 5 6 4 Legend: 1. Refresh address 2. Row address 3. Block address (A2 – A8) is latched on the first falling edge of CASx. 4. Color-register data 5. Write-mask data: DQ0 – DQ15 are latched on the falling edge of RAS. 6. Column-mask data: DQi – DQi+3 (i = 0, 4, 8, 12) are latched on either the first falling edge of CASx or the falling edge of WE, whichever occurs later. = don’t care Figure 14. Example of a Persistent Block Write DRAM-to-SAM transfer operation During the DRAM-to-SAM transfer operation, one half of a row (256 columns) in the DRAM array is selected to be transferred to the 256-bit serial-data register. The transfer operation is invoked by TRG being brought low and WE being held high on the falling edge of RAS. The state of DSF, which is latched on the falling edge of RAS, determines whether the full-register-transfer read operation or the split-register-transfer read operation is performed (see Table 4). Table 4. SAM Function Table CASx FALL RAS FALL FUNCTION ADDRESS DQ0 – DQ15 MNE CODE CASx† TRG WE DSF DSF RAS CASx RAS CASx WE Full-register-transfer read H L H L X Row Addr Tap Point X X RT Split-register-transfer read H L H H X Row Addr Tap Point X X SRT † Logic L is selected when either CASL or CASU are low. X = don’t care 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 full-register-transfer read A full-register-transfer read operation loads data from a selected half of a row in the DRAM into the SAM. TRG is brought low and latched at the falling edge of RAS. Nine row-address bits (A0 – A8) are also latched at the falling edge of RAS to select one of the 512 rows available for the transfer. The nine column-address bits (A0– A8) are latched at the first falling edge of CASx, where address bit A8 selects which half of the row is transferred. Address bits A0 – A7 select one of the SAM’s 256 available tap points from which the serial data is read out (see Figure 15). 0 A8 = 0 255 256 A8 = 1 511 512 × 512 Memory Array 256-Bit Data Register 0 255 Figure 15. Full-Register-Transfer Read A full-register-transfer read can be performed in three ways: early load, real-time load (or midline load), or late load. Each of these offers the flexibility of controlling the TRG trailing edge in the full-register-transfer read cycle (see Figure 16). Early Load Real-Time Load Late Load RAS CASx A0 – A8 Row Tap Point Row Tap Point Row Tap Point TRG WE SC Old Data Tap Bit Old Data Old Data Tap Bit Old Data Old Data Tap Bit Figure 16. Example of Full-Register-Transfer Read Operations POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 25 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 split-register-transfer read In the split-register-transfer-read operation, the serial-data register is split into halves. The low half contains bits 0 – 127, and the high half contains bits 128 – 255. While one half is being read out of the SAM port, the other half can be loaded from the memory array. A8 = 0 0 255 256 A8 = 1 511 512 × 512 Memory Array 256-Bit Data Register 0 255 Figure 17. Split-Register-Transfer Read To invoke a split-register-transfer-read cycle, DSF is brought high, TRG is brought low, and both are latched at the falling edge of RAS. Nine row-address bits (A0 – A8) are also latched at the falling edge of RAS to select one of the 512 rows available for the transfer. Eight of the nine column-address bits (A0 – A6 and A8) are latched at the first falling edge of CASx. Column-address bit A8 selects which half of the row is to be transferred. Column-address bits A0 – A6 selects one of the 127 tap points in the specified half of the SAM. Column-address bit A7 is ignored, and the split-register transfer is controlled internally to select the inactive register half. Full XFER RAS Split XFER Split XFER A8 = 1 A8 = 1 A8 = 0 0 511 A A7 = 0† 511 0 A B B C Split XFER A8 = 0 A7 = 1† 511 0 A B C 0 A7 = 0† D A C E D D E DRAM 0 SAM 511 B 0 255 A 255 C B SQ 0 B 255 C 0 D SQ SQ 255 SQ † A7 shown as internally controlled. Figure 18. Example of a Split-Register-Transfer Read Operation A full-register-transfer-read cycle must precede the first split-register-transfer-read cycle to ensure proper operation. After the full-register-transfer-read cycle, the first split-register-transfer-read cycle can follow immediately without any minimum SC-clock requirement. 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 split-register-transfer read (continued) QSF indicates which half of the register is being accessed during serial-access operation. When QSF is low, the serial-address pointer is accessing the lower (least significant) 128 bits of the SAM. When QSF is high, the pointer is accessing the higher (most significant) 128 bits of the SAM. QSF changes state upon completing a full-register-transfer-read cycle. The tap point loaded during the current transfer cycle determines the state of QSF. QSF also changes state when a boundary between two register halves is reached. Full-Register-Transfer Read With Tap Point N Split-RegisterTransfer Read RAS CASx TRG DSF SC Tap Point N td(CLQSF) td(GHQSF ) QSF Figure 19. Example of a Split-Register-Transfer Read After a Full-Register-Transfer Read Split-RegisterTransfer Read With Tap Point N Split-RegisterTransfer Read RAS CASx TRG DSF td(MSRL) td(RHMS) SC 127 or 255 Tap Point N td(SCQSF) QSF Figure 20. Example of Successive Split-Register-Transfer-Read Operations POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 27 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 serial-read operation The serial-read operation can be performed through the SAM port simultaneously and asynchronously with DRAM operations except during transfer operations. Serial data can be read from the SAM by clocking SC starting at the tap point loaded by the preceding transfer cycle, proceeding sequentially to the most significant bit (bit 255), and then wrapping around to the least significant bit (bit 0), as shown in Figure 21. 0 1 2 Tap 254 255 Figure 21. Serial-Pointer Direction for Serial Read For split-register-transfer-read operation, serial data can be read out from the active half of the SAM by clocking SC starting at the tap point loaded by the preceding split-register-transfer cycle. The serial pointer then proceeds sequentially to the most significant bit of the half, bit 127 or bit 255. If there is a split-register-transfer read to the inactive half during this period, the serial pointer points next to the tap point location loaded by that split-register transfer (see Figure 22). 0 Tap 126 127 128 Tap 254 255 Figure 22. Serial Pointer for Split-Register Read – Case I If there is no split-register-transfer read to the inactive half during this period, the serial pointer points next to bit 128 or bit 0, respectively (see Figure 23). 0 Tap 126 127 128 Tap 254 255 Figure 23. Serial Pointer for Split-Register Read – Case II split-register programmable stop point The SMJ55161 offers a programmable stop-point mode for split-register-transfer read operations. This mode can be used to improve two-dimensional drawing performance in a nonscanline data format. For a split-register-transfer-read operation, the stop point is defined as a register location at which the serial output stops coming from one half of the SAM and switches to the opposite half of the SAM. While in stop-point mode, the SAM is divided into partitions whose length is programmed via row addresses A4 – A7 in a CBR set (CBRS) cycle. The last serial-address location of each partition is the stop point (see Figure 24). 127 0 128 255 Partition Length Stop Points Figure 24. Example of the SAM With Partitions 28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 split-register programmable stop point (continued) Stop-point mode is not active until the CBRS cycle is initiated. The CBRS operation is enabled by holding CASx and WE low and DSF high on the falling edge of RAS. The falling edge of RAS also latches row addresses A4– A7 which are used to define the SAM’s partition length. The other row-address inputs are don’t cares. Stop-point mode should be initiated after the initialization cycles are performed (see Table 5). Table 5. Programming Code for Stop-Point Mode MAXIMUM PARTITION LENGTH A8 A7 A6 A5 A4 A0 – A3 NUMBER OF PARTITIONS 16 X L L L L X 16 15, 31, 47, 63, 79, 95, 111, 127, 143, 159, 175, 191, 207, 223, 239, 255 32 X L L L H X 8 31, 63, 95, 127, 159, 191, 223, 255 64 X L L H H X 4 63, 127, 191, 255 128 (default) X L H H H X 2 127, 255 ADDRESS AT RAS IN CBRS CYCLE STOP POINT LOCATIONS STOP-POINT In stop-point mode, the tap point loaded during the split-register-transfer read cycle determines the SAM partition in which the serial output begins and at which stop point the serial output stops coming from one half of the SAM and switches to the opposite half of the SAM (see Figure 25). RAS Full Read XFER Split Read XFER Split Read XFER Split Read XFER Tap = H1 Tap = L1 Tap = H2 Tap = L2 H1 191 L1 63 H2 255 L2 SC 0 L1 SAM Low Half 63 L2 127 128 H1 SAM High Half 191 H2 255 Figure 25. Example of Split-Register Operation With Programmable Stop Points POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 29 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 256- / 512-bit compatibility of split-register programmable stop point The stop-point mode is designed to be compatible with both 256-bit SAM and 512-bit SAM devices. After the CBRS cycle is initiated, the stop-point mode becomes active. In stop-point mode only, column-address bits AY7 and AY8 are internally swapped to assure compatibility (see Figure 26). This address-bit swap applies to the column address and is effective for all DRAM and transfer cycles. For example, during the split-register-transfer cycle with stop point, column-address bit AY8 is a don’t care and AY7 decodes the DRAM half-row for the split-register transfer. During stop-point mode, a CBR ( option reset ) cycle is not recommended because this ends the stop-point mode and restores address bits AY7 and AY8 to their normal functions. Consistent use of CBR cycles ensures that the SMJ55161 remains in normal mode. NONSTOP-POINT MODE AY8 = 0 AY8 = 1 AY7 = 0 AY7 = 1 AY7 = 0 AY7 = 1 0 STOP-POINT MODE AY8 = 0 AY8 = 1 AY7 = 0 AY7 = 1 AY7 = 0 AY7 = 1 512 × 512 Memory Array 512 × 512 Memory Array 256 - Bit Data Register 256 - Bit Data Register 255 0 255 Figure 26. DRAM-to-SAM Mapping, Nonstop-Point Versus Stop Point IMPORTANT: For proper device operation, a stop-point-mode (CBRS) cycle should be initiated immediately after the power-up initialization cycles are performed. power up To achieve proper device operation, an initial pause of 200 µs is required after power up followed by a minimum of eight RAS cycles or eight CBR cycles to initialize the DRAM port. A full-register-transfer-read cycle and two SC cycles are required to initialize the SAM port. After initialization, the internal state of the SMJ55161 is as shown in Table 6. Table 6. Internal State of SMJ55161 STATE AFTER INITIALIZATION QSF Write mode Write-mask register Color register Serial-register tap point SAM port 30 Defined by the transfer cycle during initialization Nonpersistent mode Undefined Undefined Defined by the transfer cycle during initialization Output mode POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Voltage range on any pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX 4.5 5 5.5 UNIT VCC VSS Supply voltage VIH VIL High-level input voltage 2.4 6.5 V Low-level input voltage (see Note 2) –1 0.8 V Supply voltage 0 V V TA Operating free-air temperature – 55 125 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS ‡ PARAMETER VOH VOL High-level output voltage SAM PORT IOH = – 1 mA IOL = 2 mA Low-level output voltage ’55161-75 ’55161- 80 MIN MIN MAX 2.4 MAX 2.4 UNIT V 0.4 0.4 V ± 10 ± 10 µA ± 10 ± 10 µA II Input current (leakage) VCC = 5.5 V, VI = 0 V to 5.8 V, All other pins at 0 V to VCC IO ICC1 Output current (leakage) (see Note 3) Operating current § VCC = 5.5 V, VO = 0 V to VCC See Note 4 Standby 165 160 mA ICC1A ICC2 Operating current § tc(SC) = MIN All clocks = VCC Active 210 195 mA Standby 12 12 mA ICC2A ICC3 Standby current Active 70 65 mA RAS-only refresh current tc(SC) = MIN See Note 4 Standby 165 160 mA ICC3A ICC4 RAS-only refresh current Page-mode current § tc(SC) = MIN, tc(P) = MIN, (See Note 5) Active 215 195 mA (See Note 5) Standby 100 95 mA ICC4A ICC5 Page-mode current § tc(SC) = MIN, See Note 4 (See Note 5) Active 145 130 mA Standby 165 160 mA ICC5A ICC6 CBR current tc(SC) = MIN, See Note 4 (See Note 5) Active 210 195 mA Standby 180 170 mA 225 200 mA Standby current CBR current Data-transfer current ICC6A Data-transfer current tc(SC) = MIN Active ‡ For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. § Measured with outputs open NOTES: 3. SE is disabled for SQ output leakage tests. 4. Measured with one address change while RAS = VIL; tc(rd ), tc( W ), tc( TRD) = MIN 5. Measured with one address change while CASx = VIH POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 31 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 6) TYP MAX Ci(A) Input capacitance, address inputs PARAMETER MIN 5 10 UNIT pF Ci(RC) Input capacitance, address-strobe inputs 8 10 pF Ci(W) Input capacitance, write-enable input 7 10 pF Ci(SC) Input capacitance, serial clock 6 10 pF Ci(SE) Input capacitance, serial enable 7 10 pF Ci(DSF) Input capacitance, special function 7 10 pF Ci(TRG) Input capacitance, transfer-register input 7 10 pF Co(O) Output capacitance, SQ and DQ 12 15 pF Co(QSF) Output capacitance, QSF 10 12 pF NOTE 6: VCC = 5 V ± 0.5 V, and the bias on pins under test is 0 V. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 7) PARAMETER TEST CONDITIONS† ALT. SYMBOL ’55161-75 ’55161-80 MIN MIN MAX MAX UNIT ta(C) Access time from CASx td(RLCL) = MAX tCAC 20 20 ns ta(CA) Access time from column address td(RLCL) = MAX tAA 38 40 ns ta(CP) Access time from CASx high td(RLCL) = MAX tCPA 43 45 ns ta(R) Access time from RAS td(RLCL) = MAX tRAC 75 80 ns ta(G) Access time of DQ from TRG low tOEA 20 20 ns ta(SQ) Access time of SQ from SC high CL = 30 pF tSCA 23 25 ns ta(SE) Access time of SQ from SE low CL = 30 pF tSEA 18 20 ns tdis(CH) Disable time, random output from CASx high (see Note 8) CL = 50 pF tOFF tdis(RH) Disable time, random output from RAS high (see Note 8) CL = 50 pF tdis(G) Disable time, random output from TRG high (see Note 8) CL = 50 pF tdis(WL) Disable time, random output from WE low (see Note 8) tdis(SE) Disable time, serial output from SE high (see Note 8) 0 20 0 20 ns 0 20 0 20 ns tOEZ 0 20 0 20 ns CL = 50 pF tWEZ 0 25 0 25 ns CL = 30 pF tSEZ 0 18 0 20 ns † For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. NOTES: 7. Switching times for RAM-port output are measured with a load equivalent to one TTL load and 50 pF. Data-out reference level: VOH / VOL = 2 V/0.8 V. Switching times for SAM-port output are measured with a load equivalent to one TTL load and 30 pF. Serial-data out reference level: VOH / VOL = 2 V/0.8 V. 8. tdis(CH), tdis(RH), tdis(G), tdis( WL ), and tdis(SE) are specified when the output is no longer driven. 32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 timing requirements over recommended ranges of supply voltage and operating free-air temperature† ALT. SYMBOL tc(rd) tc(W) Cycle time, read tc(rdW) tc(P) Cycle time, read-modify-write tc(RDWP) tc(TRD) Cycle time, page-mode read-modify-write tc(SC) tw(CH) Cycle time, serial clock (see Note 9) tw(CL) tw(RH) Pulse duration, CASx low (see Note 10) tw(RL) tw(WL) Pulse duration, RAS low (see Note 11) tw(TRG) tw(SCH) Pulse duration, TRG low Pulse duration, SC high tw(SCL) tw(GH) Pulse duration, SC low tw(RL)P tsu(CA) Pulse duration, RAS low (page mode) tsu(SFC) tsu(RA) Setup time, DSF before CASx low tsu(WMR) tsu(DQR) Setup time, WE before RAS low tsu(TRG) tsu(SFR) Setup time, TRG high before RAS low tsu(DCL) tsu(DWL) Setup time, data valid before CASx low tsu(rd) tsu(WCL) Setup time, read command, WE high before CASx low tsu(WCH) tsu(WRH) Setup time, WE low before CASx high, write th(CLCA) th(SFC) Hold time, column address after CASx low Cycle time, write Cycle time, page-mode read, write Cycle time, transfer read Pulse duration, CASx high Pulse duration, RAS high Pulse duration, WE low Pulse duration, TRG high Setup time, row address before RAS low Setup time, DQ before RAS low Setup time, DSF low before RAS low Setup time, data valid before WE low Setup time, early-write command, WE low before CASx low Setup time, WE low before RAS high, write Hold time, DSF after CASx low MAX ’55161-80 MIN MAX UNIT tRC tWC 140 150 ns 140 150 ns tRMW tPC 188 200 ns 48 50 ns tPRMW tRC 88 90 ns 140 150 ns tSCC tCPN 24 30 ns 10 10 ns tCAS tRP 20 tRAS tWP 75 10 000 55 20 10 000 60 10 000 80 ns ns 10 000 ns 13 15 ns 20 20 ns tSC 9 10 ns tSCP tTP 9 10 ns 20 20 ns 75 100 000 80 100 000 ns tRASP tASC Setup time, column address before CASx low ’55161-75 MIN 0 0 ns tFSC tASR 0 0 ns 0 0 ns tWSR tMS 0 0 ns 0 0 ns tTHS tFSR 0 0 ns 0 0 ns tDSC tDSW tRCS 0 0 ns 0 0 ns 0 0 ns tWCS tCWL 0 0 ns 18 20 ns tRWL tCAH 20 20 ns 13 15 ns tCFH tRAH 15 15 ns th(RA) Hold time, row address after RAS low 10 10 ns † Timing measurements are referenced to VIL MAX and VIH MIN. NOTES: 9. Cycle time assumes tt = 3 ns. 10. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the transition times, this can require additional CASx low time [tw(CL)]. 11. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the transition times, this can require additional RAS low time [tw(RL)]. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 33 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued) † ALT. SYMBOL th(TRG) th(RWM) Hold time, TRG after RAS low th(RDQ) th(SFR) Hold time, DQ after RAS low (write-mask operation) th(RLCA) th(CLD) Hold time, column address valid after RAS low (see Note 12) th(RLD) th(WLD) Hold time, data valid after RAS low (see Note 12) th(CHrd) th(RHrd) Hold time, read, WE high after CASx high (see Note 13) th(CLW) th(RLW) Hold time, write, WE low after CASx low th(WLG) th(SHSQ) Hold time, TRG high after WE low (see Note 14) th(RSF) th(CLQ) Hold time, DSF after RAS low td(RLCH) Dela time, Delay time RAS low lo to CASx CAS high td(CHRL) td(CLRH) Delay time, CASx high to RAS low td(CLWL) td(RLCL) Delay time, CASx low to WE low (see Notes 16 and 17) td(CARH) td(CACH) Delay time, column address valid to RAS high td(RLWL) td(CAWL) Delay time, RAS low to WE low (see Note 16) td(CLRL) td(RHCL) Delay time, CASx low to RAS low (see Note 15) Hold time, write mask after RAS low Hold time, DSF after RAS low Hold time, data valid after CASx low Hold time, data valid after WE low Hold time, read, WE high after RAS high (see Note 13) Hold time, write, WE low after RAS low (see Note 12) Hold time, SQ valid after SC high Hold time, output valid after CASx low (See Note 15) Delay time, CASx low to RAS high Delay time, RAS low to CASx low (see Note 18) Delay time, column address valid to CASx high Delay time, column address valid to WE low (see Note 16) Delay time, RAS high to CASx low (see Note 15) ’55161-75 ’55161-80 MIN MIN MAX POST OFFICE BOX 1443 UNIT tTHH tRWH tMH 15 15 ns 15 15 ns 15 15 ns tRFH tAR 10 10 ns 33 35 ns tDH 15 15 ns tDHR tDH 35 35 ns 15 15 ns tRCH tRRH 0 0 ns 0 0 ns tWCH tWCR 15 15 ns 35 35 ns tOEH tSOH 10 10 ns 2 2 ns tFHR tDHC 35 35 ns 0 0 ns tCSH tCHR tCRP 75 80 13 15 0 0 ns tRSH tCWD tRCD 20 20 ns 48 50 ns tRAL tCAL 38 40 ns 38 40 ns tRWD tAWD 100 105 ns 63 65 ns tCSR tRPC 0 0 ns 0 0 ns 20 ns 15 ns 20 td(CLGH) Delay time, CASx low to TRG high for DRAM read cycles 20 td(GHD) Delay time, TRG high before data applied at DQ tOED 15 † Timing measurements are referenced to VIL MAX and VIH MIN. NOTES: 12. The minimum value is measured when td(RLCL) is set to td(RLCL) MIN as a reference. 13. Either th(RHrd) or td(CHrd) must be satisfied for a read cycle. 14. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle. 15. CBR refresh operation only 16. Read-modify-write operation only 17. TRG must disable the output buffers prior to applying data to the DQ pins. 18. The maximum value is specified only to assure RAS access time. 34 MAX • HOUSTON, TEXAS 77251–1443 50 20 ns 60 ns SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued)† ALT. SYMBOL td(RLTH) td(RLSH) Delay time, RAS low to TRG high (see Note 19) td(RLCA) td(GLRH) Delay time, RAS low to column address valid td(CLSH) td(SCTR) Delay time, CASx low to first SC high after TRG high (see Note 20) td(THRH) td(THRL) Delay time, TRG high to RAS high (see Note 19) ’55161-75 ’55161-80 MIN MIN MAX MAX tRTH tRSD 58 tRAD tROH 15 20 20 ns tCSD tTSL 23 25 ns 5 5 ns tTRD tTRP – 10 – 10 ns Delay time, TRG high to RAS low (see Note 21) 55 60 ns td(THSC) Delay time, TRG high to SC high (see Note 19) tTSD 18 20 ns td(RHMS) Delay time, RAS high to last (most significant) rising edge of SC before boundary switch during split-register-transfer read cycles 20 20 ns td(CLTH) td(CASH) td(CAGH) td(DCL) td(DGL) Delay time, RAS low to first SC high after TRG high (see Note 20) Delay time, TRG low to RAS high Delay time, SC high to TRG high (see Notes 19 and 20) Delay time, CASx low to TRG high in real-time-transfer read cycles 60 UNIT 75 ns 80 35 15 ns 40 ns tCTH tASD 15 15 ns Delay time, column address to first SC in early-load-transfer read cycles 28 30 ns Delay time, column address to TRG high in real-time-transfer read cycles tATH 20 20 ns tDZC tDZO 0 0 ns 0 0 ns 20 20 ns Delay time, data to CASx low Delay time, data to TRG low td(MSRL) Delay time, last (most significant) rising edge of SC to RAS low before boundary switch during split-register-transfer read cycles td(SCQSF) Delay time, last (127 or 255) rising edge of SC to QSF switching at the boundary during split-register-transfer read cycles (see Note 22) tSQD 28 30 ns td(CLQSF) Delay time, CASx low to QSF switching in transfer-read cycles (see Note 22) tCQD 33 35 ns td(GHQSF) Delay time, TRG high to QSF switching in transfer-read cycles (see Note 22) tTQD 28 30 ns td(RLQSF) Delay time, RAS low to QSF switching in transfer-read cycles (see Note 22) tRQD 73 75 ns trf(MA) Refresh time interval, memory tREF 8 8 ms tt Transition time tT 3 50 3 50 ns † Timing measurements are referenced to VIL MAX and VIH MIN. NOTES: 19. Real-time-load transfer read or late-load-transfer read cycle only 20. Early-load-transfer read cycle only 21. Full-register-(read) transfer cycles only 22. Switching times for QSF output are measured with a load equivalent to one TTL load and 30 pF, and the output reference level is VOH / VOL = 2 V/0.8 V. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 35 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tc(rd) tw(RL) td(RLCH) RAS tw(RH) tt td(CLRH) td(RLCL) tw(CL) td(CHRL) CASx tw(CH) td(RLCA) td(CARH) th(RA) th(RLCA) td(CACH) tsu(RA) th(CLCA) tsu(CA) Row A0 – A8 Column th(SFR) tsu(SFR) DSF td(CLGH) tsu(TRG) td(GLRH) tw(TRG) th(TRG) TRG th(RHrd) tsu(rd) th(CHrd) WE tdis(CH) tdis(G) td(DGL) DQ0 – DQ15 ta(G) Data In Data Out ta(C) ta(CA) ta(R) Figure 27. Read-Cycle Timing With CASx-Controlled Output 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tc(rd) tw(RL) td(RLCH) RAS tw(RH) tt td(CLRH) td(RLCL) tw(CL) td(CHRL) CASx tw(CH) td(RLCA) td(CARH) th(RA) th(RLCA) td(CACH) tsu(RA) th(CLCA) tsu(CA) Row A0 – A8 Column th(SFR) tsu(SFR) DSF td(CLGH) td(GLRH) tsu(TRG) th(TRG) tw(TRG) TRG tsu(rd) th(RHrd) th(CHrd) WE td(DGL) DQ0 – DQ15 ta(G) Data In tdis(G) tdis(RH) Data Out ta(C) ta(CA) ta(R) Figure 28. Read-Cycle Timing With RAS-Controlled Output POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 37 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tc(W) tw(RL) RAS tw(RH) tt td(RLCH) tt td(CLRH) td(RLCL) td(CHRL) td(CHRL) tw(CL) CASx tw(CH) th(RLCA) th(RA) tsu(CA) td(CACH) th(CLCA) td(CARH) td(RLCA) tsu(RA) Row A0 – A8 Column tsu(SFC) tsu(SFR) th(RSF) th(SFR) th(SFC) DSF th(TRG) tsu(TRG) TRG tsu(WCH) tsu(WMR) tsu(WRH) th(RLW) th(CLW) tsu(WCL) tw(WL) th(RWM) 1 WE tsu(DCL) tsu(DQR) th(CLD) th(RDQ) th(RLD) DQ0 – DQ15 2 3 Figure 29. Early-Write-Cycle Timing Table 7. Early-Write-Cycle State Table STATE CYCLE 1 2 3 Write operation (nonmasked) H Don’t care Valid data Write operation with nonpersistent write-per-bit L Write mask Valid data Write operation with persistent write-per-bit L Don’t care Valid data 38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tc(W) tw(RL) RAS tw(RH) td(RLCH) tt td(CLRH) td(CHRL) td(RLCL) td(CHRL) tt tw(CL) CASx td(RLCA) th(RLCA) tw(CH) tsu(CA) td(CACH) th(CLCA) td(CARH) th(RA) tsu(RA) Row A0 – A8 Column th(RSF) tsu(SFR) th(SFR) tsu(SFC) th(SFC) DSF tsu(rd) TRG tsu(WRH) tsu(TRG) tsu(WCH) th(CLW) td(GHD) th(RLW) tsu(WMR) th(WLG) th(RWM) WE tw(WL) 1 tsu(DWL) tsu(DQR) th(WLD) th(RDQ) th(RLD) 2 DQ0 – DQ15 3 Figure 30. Late-Write-Cycle Timing (Output-Enable-Controlled Write) Table 8. Late-Write-Cycle State Table STATE CYCLE 1 2 3 Write operation (nonmasked) H Don’t care Valid data Write operation with nonpersistent write-per-bit L Write mask Valid data Write operation with persistent write-per-bit L Don’t care Valid data POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 39 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tc(W) tw(RL) RAS tw(RH) td(RLCH) tt td(CLRH) tt td(CHRL) td(RLCL) td(CHRL) tw(CL) CASx tw(CH) th(RA) Refresh Row tsu(RA) A0 – A8 tsu(SFC) tsu(SFR) th(RSF) th(SFR) th(SFC) DSF th(TRG) tsu(TRG) TRG tsu(WCH) tsu(WMR) tsu(WRH) th(RLW) th(CLW) th(RWM) tsu(WCL) tw(WL) WE tsu(DCL) th(CLD) th(RLD) DQ0 – DQ15 Write Mask† † Load-write-mask-register cycle puts the device into the persistent write-per-bit mode. Figure 31. Load-Write-Mask-Register-Cycle Timing (Early-Write Load) 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tc(W) tw(RL) RAS tw(RH) td(RLCH) tt td(CLRH) td(CHRL) td(RLCL) td(CHRL) tt tw(CL) CASx tw(CH) th(RA) Refresh Row tsu(RA) A0 – A8 th(RSF) tsu(SFR) tsu(SFC) th(SFR) th(SFC) DSF tsu(WRH) TRG tsu(WCH) th(CLW) tsu(TRG) td(GHD) th(RLW) tsu(WMR) th(WLG) th(RWM) tw(WL) WE tsu(DWL) th(WLD) th(RLD) DQ0 – DQ15 Write Mask† † Load-write-mask-register cycle puts the device into the persistent write-per-bit mode. Figure 32. Load-Write-Mask-Register-Cycle Timing (Late-Write Load) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 41 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tc(rdW) tw(RL) td(RLCH) RAS td(CHRL) td(RLCL) CASx tw(RH) td(CLRH) td(CHRL) tw(CL) th(RA) tw(CH) tsu(CA) th(CLCA) th(RLCA) tsu(RA) td(CACH) td(CARH) td(RLCA) A0 – A8 Row Column th(RSF) tsu(SFR) th(SFC) tsu(SFC) th(SFR) DSF tsu(WCH) tsu(rd) th(TRG) tsu(WRH) td(CAWL) tw(TRG) TRG th(WLG) th(RLW) th(CLW) tsu(TRG) td(CLWL) td(DCL) td(CLGH) tsu(WMR) th(RWM) WE tw(WL) 1 ta(CA) td(RLWL) ta(R) tsu(DQR) tsu(DWL) ta(C) th(RDQ) DQ0 – DQ15 th(WLD) td(GHD) td(DGL) Valid Out 2 ta(G) 3 tdis(G) Figure 33. Read-Write-/Read-Modify-Write-Cycle Timing Table 9. Read-Write- / Read-Modify-Write-Cycle State Table STATE CYCLE 1 2 3 Write operation (nonmasked) H Don’t care Valid data Write operation with nonpersistent write-per-bit L Write mask Valid data Write operation with persistent write-per-bit L Don’t care Valid data 42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tw(RH) tw(RL)P RAS td(RLCL) td(CHRL) td(CLRH) tw(CH) tw(CL) tt td(RLCA) CASx td(RLCH) tsu(RA) th(RA) tsu(CA) tc(P) td(CACH) th(CLCA) td(CARH) th(RLCA) Row A0 – A8 Column Column th(SFR) td(CLGH) tsu(SFR) DSF th(TRG) tsu(TRG) TRG tsu(WMR) tsu(rd) th(RHrd) WE ta(C) ta(CA) td(DGL) DQ0 – DQ15 ta(G) ta(R) (see Note B) th(CLQ) ta(CA) (see Note A) ta(CP) (see Note A) Data Out Data In tdis(WL) tdis(RH) tdis(G) Data Out td(DCL) NOTES: A. Access time is ta(CP) or ta(CA) dependent. B. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. C. A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing specifications are not violated and the proper polarity of DSF is selected on the falling edge of RAS and CASx to select the desired write mode (normal, block write, etc.). Figure 34. Enhanced-Page-Mode Read-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 43 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tw(RL)P RAS td(RLCH) tw(CL) td(CHRL) td(RLCA) tsu(CA) CASx tsu(RA) tw(RH) td(CLRH) td(CHRL) tc(P) tw(CH) td(RLCL) th(CLCA) th(RA) td(CACH) th(RLCA) A0 – A8 td(CARH) Row Column tsu(SFR) Column td(RSF) th(SFR) th(SFC) th(SFC) tsu(SFC) tsu(SFC) DSF 1 2 2 tsu(TRG) th(TRG) TRG See Note A tsu(WMR) th(RWM) WE tsu(WCH) tsu(WCH) tsu(WRH) tw(WL) 3 tsu(DWL) (see Note B) tsu(DQR) th(CLD) (see Note B) tsu(DCL) (see Note B) th(WLD) (see Note B) th(RDQ) th(RLD) DQ0 – DQ15 4 5 5 NOTES: A. Referenced to the first falling edge of CASx or the falling edge of WE, whichever occurs later B. A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing specifications. To ensure page-mode cycle time, TRG must remain high throughout the entire page-mode operation if the late write feature is used. If the early write-cycle timing is used, the state of TRG is a don’t care after the minimum period th(TRG) from the falling edge of RAS. Figure 35. Enhanced-Page-Mode Write-Cycle Timing Table 10. Enhanced-Page-Mode Write-Cycle State Table STATE CYCLE 1 2 3 4 5 Write operation (nonmasked) L L Write operation with nonpersistent write-per-bit L L H Don’t care Valid data L Write mask Valid data Write operation with persistent write-per-bit L L L Don’t care Valid data Load-write mask on either the first falling edge of CASx or the H L H Don’t care Write mask falling edge of WE, whichever occurs later.† † Load-write-mask-register cycle puts the device in the persistent write-per-bit mode. Column address at the falling edge of CASx is a don’t care during this cycle. 44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tw(RL)P RAS td(RLCH) td(CHRL) tsu(RA) td(RLCA) tsu(CA) td(CHRL) th(RLCA) Row td(CARH) td(CACH) th(CLCA) Column Column th(SFR) tsu(SFR) th(SFC) th(SFC) tsu(SFC) DSF tw(CH) tw(CL) th(RA) CASx A0 – A8 td(RLCL) tw(RH td(CLRH) tc(RDWP) 1 tsu(SFC) 2 2 tsu(rd) tsu(WCH) td(DCL) td(CLWL) td(CAWL) td(RLWL) th(TRG) td(CLGH) td(CLGH) tsu(TRG) tsu(WRH) tw(TRG) TRG tsu(WCH) tsu(WMR) ta(C) (see Note A) 3 WE tsu(DQR) th(RDQ) DQ0 – DQ15 tw(TRG) tw(WL) th(RWM) ta(CA) (see Note A) th(WLD) td(DCL ) tsu(DWL) 4 Valid Out td(GHD) ta(CP) (see Note A) 5 ta(G) (see Note A) td(DGL) tsu(DWL) th(WLD) 5 td(DGL) Valid Out tdis(G) ta(C) (see Note A) td(GHD) ta(R) (see Note A) NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. B. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not violated. Figure 36. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing Table 11. Enhanced-Page-Mode Read-Modify-Write-Cycle State Table STATE CYCLE 1 2 3 4 5 Write operation (nonmasked) L L H Don’t care Valid data Write operation with nonpersistent write-per-bit L L L Write mask Valid data Write operation with persistent write-per-bit L L L Don’t care Valid data Load write-mask register on either the first falling edge of H L H Don’t care Write mask CASx or the falling edge of WE, whichever occurs later.† † Load-write-mask-register cycle puts the device in the persistent write-per-bit mode. Column address at the falling edge of CASx is a don’t care during this cycle. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 45 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tw(RH) tw(RL)P RAS td(RLCL) td(CHRL) td(CLRH) tw(CH) tw(CL) tt td(RLCA) CASx td(RLCH) tsu(RA) th(RA) tsu(CA) tc(P) td(CACH) th(CLCA) td(CARH) th(RLCA) Row A0 – A8 Column Column th(SFR) td(CLGH) tsu(SFR) DSF tsu(WCL) th(TRG) tsu(TRG) th(CLW) TRG tsu(WMR) tsu(rd) tw(WL) WE See Note A ta(CA) td(DGL) ta(C) ta(R) (see Note B) DQ0 – DQ15 tsu(DCL) Data Out Data In th(CLD) tdis(WL) ta(G) Data In td(DCL) NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. B. A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing specifications are not violated and the proper polarity of DSF is selected on the falling edge of RAS and CASx to select the desired write mode (normal, block write, etc.). Figure 37. Enhanced-Page-Mode Read- / Write-Cycle Timing 46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tc(W) tw(RL) RAS tw(RH) tt td(RLCH) tt td(CHRL) td(CLRH) td(RLCL) tw(CL) td(CHRL) CASx th(RA) tw(CH) tsu(RA) Refresh Row A0 – A8 th(SFC) th(RSF) tsu(SFR) tsu(SFC) th(SFR) DSF tsu(TRG) th(TRG) TRG tsu(WCH) tsu(WRH) tsu(WMR) th(RLW) th(RWM) th(CLW) tsu(WCL) WE tw(WL) tsu(DCL) th(CLD) th(RLD) DQ0 – DQ15 Valid Color Input Figure 38. Load-Color-Register-Cycle Timing (Early-Write Load) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 47 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tc(W) tw(RL) RAS tw(RH) tt td(RLCH) tt td(CLRH) td(RLCL) td(CHRL) td(CHRL) tw(CL) CASx th(RSF) th(RA) tw(CH) Refresh Row tsu(RA) A0 – A8 tsu(SFR) th(SFC) tsu(SFC) th(SFR) DSF tsu(TRG) th(CLW) TRG tsu(WRH) td(GHD) tsu(WCH) th(RLW) tsu(WMR) th(WLG) tw(WL) WE tsu(DWL) th(WLD) th(RLD) DQ0 – DQ15 Valid Color Input Figure 39. Load-Color-Register-Cycle Timing (Late-Write Load) 48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tc(W) tw(RL) RAS td(RLCL) tw(RH) tt td(RLCH) tt td(CLRH) td(CHRL) td(CHRL) tw(CL) CASx tw(CH) td(RLCA) th(RLCA) td(RLCA) td(CARH) td(CACH) tsu(RA) th(RA) t tsu(CA) h(CLCA) Row A0 – A8 th(RSF) Block Address A2 – A8 tsu(SFR) tsu(SFC) th(SFR) th(SFC) DSF th(TRG) tsu(TRG) TRG tsu(WCH) th(RWM) tsu(WRH) tsu(WCL) tsu(WMR) th(CLW) th(RLW) tw(WL) 1 WE th(RLD) tsu(DCL) tsu(DQR) th(CLD) th(RDQ) DQ0 – DQ15 2 3 Figure 40. Block-Write-Cycle Timing (Early Write) Table 12. Block-Write-Cycle State Table STATE CYCLE 1 2 3 Block-write operation (nonmasked) H Don’t care Column mask Block-write operation with nonpersistent write-per-bit L Write mask Column mask Block-write operation with persistent write-per-bit L Don’t care Column mask Write-mask data 0: I/O write disable 1: I/O write enable Column-mask data DQi – DQi + 3 0: column-write disable (i = 0, 4, 8, 12) 1: column-write enable POST OFFICE BOX 1443 Example: DQ0 — column 0 (address A1 = 0, A0 = 0) DQ1 — column 1 (address A1 = 0, A0 = 1) DQ2 — column 2 (address A1 = 1, A0 = 0) DQ3 — column 3 (address A1 = 1, A0 = 1) • HOUSTON, TEXAS 77251–1443 49 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tc(W) tw(RL) RAS tw(RH) tt td(RLCH) tt td(CLRH) td(RLCL) td(CHRL) td(CHRL) tw(CL) CASx td(RLCA) td(CACH) tw(CH) th(RLCA) td(CARH) th(RA) tsu(CA) th(CLCA) tsu(RA) Row A0 – A8 th(RSF) tsu(SFR) Block Address A2 – A8 tsu(SFC) th(SFR) th(SFC) DSF tsu(TRG) th(CLW) tsu(WCH) TRG td(GHD) th(RLW) tsu(WRH) tsu(WMR) th(WLG) th(RWM) WE tw(WL) 1 tsu(DQR) tsu(DWL) th(RDQ) th(WLD) th(RLD) DQ0 – DQ15 3 2 Figure 41. Block-Write-Cycle Timing (Late Write) Table 13. Block-Write-Cycle State Table CYCLE STATE 1 2 3 Block-write operation (nonmasked) H Don’t care Column mask Block-write operation with nonpersistent write-per-bit L Write mask Column mask Block-write operation with persistent write-per-bit L Don’t care Column mask Write-mask data 0: I/O write disable 1: I/O write enable Column-mask data DQi – DQi + 3 0: column-write disable (i = 0, 4, 8, 12) 1: column-write enable 50 POST OFFICE BOX 1443 Example: DQ0 — column 0 (address A1 = 0, A0 = 0) DQ1 — column 1 (address A1 = 0, A0 = 1) DQ2 — column 2 (address A1 = 1, A0 = 0) DQ3 — column 3 (address A1 = 1, A0 = 1) • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tw(RL)P RAS tc(P) td(RLCH) td(RLCL) td(CHRL) CASx tw(RH) td(CLRH) tw(CH) td(CHRL) tw(CL) td(RLCA) tsu(CA) th(RLCA) tsu(RA) Row A0 – A8 td(CACH) th(CLCA) th(RA) th(SFR) tsu(SFR) td(CARH) Block Address A2 – A8 Block Address A2 – A8 th(SFC) tsu(SFC) th(SFC) tsu(SFC) DSF th(TRG) tsu(TRG) TRG See Note A tsu(WMR) tw(WL) th(RWM) WE tsu(WCH) tsu(WCH) tsu(WRH) 1 tsu(DWL) (see Note A) tsu(DQR) th(CLD) (see Note A) th(WLD) (see Note A) th(RDQ) tsu(DCL) (see Note A) th(RLD) DQ0 – DQ15 2 3 3 NOTES: A. Referenced to the first falling edge of CASx or the falling edge of WE, whichever occurs later B. To ensure page-mode cycle time, TRG must remain high throughout the entire page-mode operation if the late-write feature is used. If the early-write cycle timing is used, the state of TRG is a don’t care after the minimum period th(TRG) from the falling edge of RAS. Figure 42. Enhanced-Page-Mode Block-Write-Cycle Timing Table 14. Enhanced-Page-Mode Block-Write-Cycle State Table STATE CYCLE 1 2 3 Block-write operation (nonmasked) H Don’t care Column mask Block-write operation with nonpersistent write-per-bit L Write mask Column mask Block-write operation with persistent write-per-bit L Don’t care Column mask Write-mask data 0: I/O write disable 1: I/O write enable Column-mask data DQi – DQi + 3 0: column-write disable (i = 0, 4, 8, 12) 1: column-write enable POST OFFICE BOX 1443 Example: DQ0 — column 0 (address A1 = 0, A0 = 0) DQ1 — column 1 (address A1 = 0, A0 = 1) DQ2 — column 2 (address A1 = 1, A0 = 0) DQ3 — column 3 (address A1 = 1, A0 = 1) • HOUSTON, TEXAS 77251–1443 51 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tc(rd) tw(RL) RAS tw(RH) tt td(RHCL) td(CHRL) CASx th(RA) tsu(RA) Row A0 – A8 DSF tsu(TRG) th(TRG) TRG WE DQ0 – DQ15 Figure 43. RAS-Only Refresh-Cycle Timing 52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 td(CHRL) SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tc(rd) tw(RH) tw(RL) RAS td(RHCL) tt td(CLRL) td(RLCH) CASx td(CHRL) tsu(RA) th(RA) 1 A0 – A8 tsu(SFR) th(SFR) 2 DSF TRG th(RWM) tsu(WMR) 3 WE DQ0 – DQ15 Figure 44. CBR-Refresh-Cycle Timing Table 15. CBR-Cycle State Table STATE CYCLE 1 2 3 CBR refresh with option reset Don’t care L H CBR refresh with no reset Don’t care H H Stop address H L CBR refresh with stop-point set and no reset POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 53 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION Memory Read Cycle Refresh Cycle tc(rd) tc(rd) tc(rd) tw(RH) tw(RH) tw(RL) Refresh Cycle tw(RL) RAS td(CARH) td(CHRL) td(RLCH) tt tw(CL) CASx td(RLCA) tsu(RA) tsu(RA) th(CLCA) tsu(CA) th(RA) tsu(RA) th(RA) tsu(RA) A0 – A8 Row th(RA) th(RA) 1 Col 1 1 tsu(SFR) th(SFR) tsu(SFR) th(SFR) th(SFR) 2 2 DSF tsu(SFR) 2 th(RHrd) tdis(CH) tsu(TRG) tdis(G) th(TRG) td(GLRH) TRG tsu(WMR) th(RWM) tsu(WMR) th(RWM) tsu(rd) ta(G) WE 3 tsu(WMR) th(RWM) 3 3 ta(C) ta(R) DQ0 – DQ15 Data Out Figure 45. Hidden-Refresh-Cycle Timing Table 16. Hidden-Refresh-Cycle State Table STATE CYCLE CBR refresh with option reset CBR refresh with no reset CBR refresh with stop-point set and no option reset 54 POST OFFICE BOX 1443 1 2 3 Don’t care L H Don’t care H H Stop address H L • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tc(TRD) tw(RL) td(RLCL) RAS tw(RH) td(RLCH) td(CHRL) td(CARH) tw(CL) td(RLCA) CASx th(RA) tsu(RA) tsu(CA) th(CLCA) th(RLCA) Tap Point A0 – A8 Row A0 – A8 tsu(SFR) th(SFR) DSF tsu(TRG) th(TRG) TRG tw(GH) th(RWM) tsu(WMR) td(CASH) WE DQ0 – DQ15 Hi-Z td(CLSH) td(SCTR) tw(SCH) tw(SCL) td(RLSH) SC tw(SCH) tc(SC) ta(SQ) th(SHSQ) th(SHSQ) Old Data SQ ta(SQ) Old Data New Data td(GHQSF) Tap Point Bit A7 QSF td(CLQSF) H td(RLQSF) SE L NOTES: A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register transfer cycle is used to load the data registers in parallel from the memory array. The 256 locations in each data register are written to from the 256 corresponding columns of the selected row. B. Once data is transferred into the data registers, the SAM is in the serial-read mode, that is, the SQ is enabled, allowing data to be shifted out of the registers. Also, the first bit to read from the data register after TRG has gone high must be activated by a positive transition of SC. C. A0 – A7: register tap point; A8: identifies the DRAM row half D. Early-load operation is defined as th(TRG) MIN < th(TRG) < td(RLTH) MIN. Figure 46. Full-Register Transfer-Read Timing, Early-Load Operations POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 55 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tc(TRD) tw(RL) td(RLCL) RAS tw(RH) td(RLCH) td(CHRL) CASx tw(CL) td(RLCA) th(RA) tsu(RA) tsu(CA) th(RLCA) th(CLCA) Tap Point A0 – A8 Row A0 – A8 tsu(SFR) th(SFR) DSF td(CLTH) tsu(TRG) td(THRL) td(THRH) td(CAGH) td(RLTH) TRG tw(GH) th(RWM) tsu(WMR) WE td(SCTR) td(THSC) DQ0 – DQ15 Hi-Z tw(SCH) SC ta(SQ) th(SHSQ) Old Data SQ tc(SC) tw(SCL) th(SHSQ) Old Data Old Data ta(SQ) New Data td(GHQSF) QSF Tap Point Bit A7 td(CLQSF) td(RLQSF) H SE L NOTES: A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register transfer cycle is used to load the data registers in parallel from the memory array. The 256 locations in each data register are written to from the 256 corresponding columns of the selected row. B. Once data is transferred into the data registers, the SAM is in the serial-read mode, that is, the SQ is enabled, allowing data to be shifted out of the registers. Also, the first bit to read from the data register after TRG has gone high must be activated by a positive transition of SC. C. A0 – A7: register tap point; A8: identifies the DRAM row half D. Late load operation is defined as td(THRH) < 0 ns. Figure 47. Full-Register Transfer Read-Timing, Real-Time Load Operation/Late-Load Operation 56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION tc(TRD) tw(RL) tw(RH) td(RLCL) RAS td(CHRL) td(RLCH) td(RLCA) tw(CH) tw(CL) tsu(CA) CASx th(RA) tsu(RA) th(CLCA) A0 – A8 Tap Point A0 – A8 Row See Note A tsu(TRG) th(TRG) TRG th(SFR) tsu(SFR) DSF th(RWM) tsu(WMR) WE DQ0 – DQ15 HI-Z td(MSRL) td(RHMS) tc(SC) tc(SC) tw(SCH) Bit 127 or 255 SC tw(SCL) ta(SQ) th(SHSQ) Bit 126 or Bit 254 SQ Bit 255 or 127 Tap Point M ta(SQ) Bit 127 or Bit 255 Tap Point N ta(SQ) Tap Point M tw(SCL) Bit 127 or Bit 255 Tap Point N ta(SQ) td(SCQSF) td(SCQSF) MSB Old QSF New MSB H SE L NOTE A: A0 – A6: tap point of the given half; A7: don’t care; A8: identifies the DRAM row half Figure 48. Split-Register-Transfer-Read Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 57 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION RAS tsu(TRG) th(TRG) TRG tc(SC) tw(SCH) tc(SC) tw(SCH) tw(SCH) tw(SCL) tw(SCL) SC ta(SQ) th(SHSQ) SQ ta(SQ) ta(SQ) th(SHSQ) Valid Out th(SHSQ) Valid Out Valid Out ta(SE) SE NOTES: A. While the data is being read through the serial-data register, TRG is a don’t care; however, TRG must be held high when RAS goes low. This is to avoid the initiation of a register-data transfer operation. B. The serial data-out cycle is used to read data out of the data registers. Before data can be read via SQ, the device must be put into the read mode by performing a transfer-read cycle. Figure 49. Serial-Read-Cycle Timing (SE = VIL ) 58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION RAS tsu(TRG) th(TRG) TRG tc(SC) tc(SC) tw(SCH) tw(SCH) tw(SCH) tw(SCL) tw(SCL) SC ta(SQ) ta(SQ) th(SHSQ) SQ Valid Out ta(SQ) ta(SE) Valid Out th(SHSQ) Valid Out Valid Out tdis(SE) SE NOTES: A. While the data is being read through the serial-data register, TRG is a don’t care; however, TRG must be held high when RAS goes low. This is to avoid the initiation of a register-data transfer operation. B. The serial data-out cycle is used to read data out of the data registers. Before data can be read via SQ, the device must be put into the read mode by performing a transfer-read cycle. Figure 50. Serial-Read Timing (SE-Controlled Read) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 59 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION RAS CAS ADDR Row Tap1 (low) Row Tap1 (high) Row Tap2 (low) Row Tap2 (high) TRG DSF CASE I SC Tap1 (low) Bit 127 Tap1 (high) Bit 255 Tap2 (low) Bit 127 Bit 127 Tap1 (high) Bit 255 Tap2 (low) Bit 127 Bit 127 Tap1 (high) Bit 255 Tap2 (low) Bit 127 QSF CASE II SC Tap1 (low) QSF CASE III SC Tap1 (low) QSF Full-Register-Transfer Read Split Register to the High Half of the Data Register Split Register to the Low Half of the Data Register Split Register to the High Half of the Data Register NOTES: A. To achieve proper split-register operation, a full-register-transfer read must be performed before the first split-register-transfer cycle. This is necessary to initialize the data register and the starting tap location. First serial access can begin either after the full-register-transfer-read cycle (CASE I), during the first split-register-transfer cycle (CASE II), or even after the first split-register-transfer cycle (CASE III). There is no minimum requirement of SC clock between the full-register transfer-read cycle and the first split-register cycle. B. A split-register transfer into the inactive half is not allowed until td(MSRL) is met. td(MSRL) is the minimum delay time between the rising edge of the serial clock of the last bit (bit 127 or 255) and the falling edge of RAS of the split-register-transfer cycle into the inactive half. After the td(MSRL) requirement is met, the split-register transfer into the inactive half must also satisfy the minimum td(RHMS) requirement. td(RHMS) is the minimum delay time between the rising edge of RAS of the split-register-transfer cycle into the inactive half and the rising edge of the serial clock of the last bit (bit 127 or 255). Figure 51. Split-Register Operating Sequence 60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 MECHANICAL DATA GB (S-CPGA-P68) CERAMIC PIN GRID ARRAY PACKAGE 0.970 (24,63) 0.950 (24,13) 0.536 (13,61) 0.524 (13,31) 0.800 (20,32) TYP J H G F E D C B A 1 2 3 4 5 6 7 8 9 0.088 (2,23) 0.072 (1,83) 0.100 (2,54) 0.194 (4,98) 0.166 (4,16) 0.055 (1,39) 0.045 (1,14) 0.050 (1,27) DIA 4 Places 0.018 (0,46) DIA TYP 4040114-14 / A 2/95 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Index mark may appear on top or bottom depending on package vendor. Pins are located within 0.005 (0,13) radius of true position relative to each other at maximum material condition and within 0.015 (0,38) radius relative to the center of the ceramic. E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit. F. The pins can be gold plated or solder dipped. G. Falls within MIL-STD-1835 CMGA1-PN and CMGA13-PN and JEDEC MO-067AA and MO-066AA, respectively POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 61 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 MECHANICAL DATA HKC (R-CDFP-F64) CERAMIC DUAL FLATPACK WITH TIE BAR 1.620 (41,14) SQ 1.580 (40,13) 1.020 (25,91) 0.980 (24,89) 0.765 (19,43) 0.730 (18,54) 0.026 (0,66) MIN 0.150 (3,81) 0.100 (2,54) 33 0.070 (1,78) 0.055 (1,40) 64 0.445 (11,30) 0.420 (10,67) 1 32 0.320 (8,13) 0.295 (7,49) 0.0098 (0,250) 0.0060 (0,150) 0.185 (4,70) 0.145 (3,68) 0.0079 (0,200) 0.0043 (0,110) 0.0196 (0,500) 0.040 (1,02) 0.030 (0,76) 4073160 / B 10/94 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. All leads not shown for clarity purposes. device symbolization -SS Speed (-70, - 80) SMJ55161 HKC M Temperature Range Package Code F R A XXX LLL Lot Traceability Code Date Code Assembly Site Code Die Revision Code Wafer Fab Code 62 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ55161 262144 BY 16-BIT MULTIPORT VIDEO RAM SGMS056D – MAY 1995 – REVISED OCTOBER 1997 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 63 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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