TI TMS55170

TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
D
D
D
D
D
D
D
D
D
D
D
Organization:
DRAM: 262 144 Words × 16 Bits
SAM: 256 Words × 16 Bits
Single 5.0-V Power Supply (±10%)
Dual-Port Accessibility – Simultaneous and
Asynchronous Access From the DRAM and
Serial-Address-Memory (SAM) Ports
Write-per-Bit Function for Selective Write to
Each I/O of the DRAM Port
Byte-Write Function for Selective Write to
Lower Byte (DQ0 – DQ7) or Upper Byte
(DQ8– DQ15) of the DRAM Port
4 - Column or 8 - Column Block - Write
Function for Fast Area - Fill Operations
Enhanced Page Mode for Faster Access
With Extended-Data-Output (EDO) Option
for Faster System Cycle Time
CAS-Before-RAS (CBR) and Hidden
Refresh Functions
Long Refresh Period – Every 8 ms
(Maximum)
Full - Register- Transfer Function Transfers
Data from the DRAM to the Serial Register
D
D
D
D
D
D
D
D
Split-Register-Transfer Function Transfers
Data from the DRAM to One-Half of the
Serial Register While the Other Half is
Outputing Data to the SAM Port
256 Selectable Serial Register Starting
Points
Programmable Split-Register Stop Point
Up to 55-MHz Uninterrupted Serial-Data
Streams
3-State Serial Outputs for Easy Multiplexing
of Video Data Streams
All Inputs/Outputs and Clocks TTL
Compatible
Compatible With JEDEC Standards
Designed to Work With the Texas
Instruments (TI) Graphics Family
Fabricated Using TI’s Enhanced
Performance Implanted CMOS (EPIC)
Process
performance ranges
ACCESS TIME
ROW ENABLE
tRAC
(MAX)
ACCESS TIME
SERIAL DATA
tSCA
(MIN)
DRAM PAGE
CYCLE TIME
tPC
(MIN)
DRAM EDO
CYCLE TIME
tPC
(MIN)
SERIAL
CYCLE TIME
tSCC
(MIN)
OPERATING CURRENT
SERIAL PORT STANDBY
lCC1
(MAX)
– 60 Speed
60 ns
15 ns
35 ns
30 ns
18 ns
180 mA
– 70 Speed
70 ns
20 ns
40 ns
30 ns
22 ns
165 mA
Table 1. Device Option Table
DEVICE
POWER SUPPLY VOLTAGE
BLOCK-WRITE CAPABILITY
PAGE / EDO OPERATION
55160
5.0 V ± 0.5 V
4 -column
Page
55161
5.0 V ± 0.5 V
4 -column
EDO
55170
5.0 V ± 0.5 V
8 - column
Page
55171
5.0 V ± 0.5 V
8 - column
EDO
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI and EPIC are trademarks of Texas Instruments Incorporated.
Copyright  1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
DGH PACKAGE
(TOP VIEW)
VCC
TRG
VSS
SQ0
DQ0
SQ1
DQ1
VCC
SQ2
DQ2
SQ3
DQ3
VSS
SQ4
DQ4
SQ5
DQ5
VCC
SQ6
DQ6
SQ7
DQ7
VSS
CASL
WE
RAS
A8
A7
A6
A5
A4
VCC
64
63
62
61
60
59
58
57
56
55
1
2
3
4
5
6
7
8
9
10
11
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SC
SE
VSS
SQ15
DQ15
SQ14
DQ14
VCC
SQ13
DQ13
SQ12
DQ12
VSS
SQ11
DQ11
SQ10
DQ10
VCC
SQ9
DQ9
SQ8
DQ8
VSS
DSF
NC / GND
CASU
QSF
A0
A1
A2
A3
VSS
PIN NOMENCLATURE
A0 – A8
RAS
CASL, CASU
DSF
TRG
WE
DQ0 – DQ15
SC
SE
SQ0 – SQ15
QSF
VCC
VSS
NC/GND
2
Address Inputs
Row-Address Strobe
Column-Address Strobe, Byte Select
Special-Function Select
Output Enable, Transfer Select
Write Enable, Write Mask Select
DRAM Data I / O
Serial Clock
Serial Enable
Serial Data Output
Special-Function Output
Power Supply
Ground
No Connect / Ground
(Important: not connected internally to VSS)
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
description
The TMS551xx multiport video RAMs (VRAMs) are high-speed dual-ported memory devices. Each consists of
a dynamic random-access memory (DRAM) organized as 262 144 words of 16 bits each interfaced to a
serial-data register [serial-access memory (SAM)] organized as 256 words of 16 bits each. These devices
support three basic types of operation: random access to and from the DRAM, serial access from the serial
register, and transfer of data from the DRAM to the SAM. Except during transfer operations, these devices can
be accessed simultaneously and asynchronously from the DRAM and SAM ports.
The TMS551xx multiport VRAMs provide several functions designed to provide higher system-level bandwidth
and to simplify design integration on both the DRAM and SAM ports (see Table 2). On the DRAM port, greater
pixel draw rates are achieved by the block-write function. The TMS5516x devices’ 4-column block-write function
allows 16 bits of data (present in an on-chip color-data register) to be written to any combination of four adjacent
column-address locations, up to a total of 64 bits of data per CASx cycle time. Similarly, the TMS5517x devices’
8-column block-write function allows 16 bits of data to be written to any combination of eight adjacent
column-address locations, up to a total of 128 bits of data per CASx cycle time. Also on the DRAM port, the
write-per-bit (or write-mask) function allows masking of any combination of the 16 DQs on any write cycle. The
persistent write-per-bit function uses a mask register that, once loaded, can be used on subsequent write cycles
without reloading. All TMS551xx devices offer byte control. Byte control can be applied in write cycles, read
cycles, block-write cycles, load-write-mask-register cycles, and load-color-register cycles. The TMS551xx
devices offer enhanced-page-mode operation that results in faster access time. The TMS551x1 devices also
offer extended-data-output (EDO) mode. The EDO mode is effective in both the page-mode and the standard
DRAM cycles.
The TMS551xx devices offer a split-register-transfer (DRAM to SAM) function. This feature enables real-time
register load implementation for continuous serial-data streams without critical timing requirements. The serial
register is divided into a high half and a low half. While one half is being read out of the SAM port, the other half
can be loaded from the DRAM. For applications not requiring real-time register load (for example, loads done
during CRT-retrace periods), the full-register-transfer operation is retained to simplify system design.
The SAM port is designed for maximum performance. Data can be accessed from the SAM at serial rates up
to 55 MHz. A separate output, QSF, is included to indicate which half of the serial register is active. Refreshing
the SAM is not required because the data register that comprises the SAM is static.
All inputs, outputs, and clock signals on the TMS551xx devices are compatible with Series 74 TTL. All address
lines and data-in lines are latched on-chip to simplify system design. All data-out lines are unlatched to allow
greater system flexibility.
All TMS551xx employ TI’s state-of-the-art EPIC technology combining very high performance with improved
reliability.
All TMS551xx are offered in a 64-pin small-outline gull-wing-leaded package (DGH suffix) for direct surface
mounting.
The TMS551xx VRAMs and other TI multiport VRAMs are supported by a broad line of graphics processors
and control devices from Texas Instruments.
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3
TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
4-column functional block diagram (TMS5516x)
DSF
Input
Buffer
1 of 4 Sub-Blocks
(see next page)
Refresh
Counter
SpecialFunction
Logic
Input
Buffer
DQ0 –
DQ15
Row
Buffer
1 of 4 Sub-Blocks
(see next page)
16
1 of 4 Sub-Blocks
(see next page)
16
A0 – A8
Column
Buffer
Output
Buffer
SQ0 – SQ15
9
SerialAddress
Counter
SC
SplitRegister
Status
SerialOutput
Buffer
QSF
SE
1 of 4 Sub-Blocks
(see next page)
RAS
CASx
TRG
Timing
Generator
WE
4
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SE
TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
4-column functional block diagram (TMS5516x) (continued)
DSF Input
Buffer
SpecialFunction
Logic
Color
Register
DRAM
Input
Buffer
DQx
DQx+1
DQx+2
DQx+3
MUX
W/B
Unlatch
W/B
Latch
Address
Mask
WritePer-Bit
Control
Refresh
Counter
DRAM
Output
Buffer
Row
Buffer
Column Dec.
RAS
CASx
TRG
WE
Sense AMP
Timing
Generator
A0 – A8
512 × 512
Memory
Array
Row
Decoder
Column
Buffer
Serial-Data
Register
Serial-Data
Pointer
SQx
SQx+1
SQx+2
SQx+3
SerialAddress
Counter
SerialOutput
Buffer
SE
1 of 4 Sub-Blocks
SC
SplitRegister
Status
QSF
SE
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5
TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
8-column functional block diagram (TMS5517x)
DSF
Input
Buffer
SpecialFunction
Logic
Refresh
Counter
1 of 2 Sub-Blocks
(see next page)
Input
Buffer
DQ0 –
DQ15
Row
Buffer
9
16
A0 – A8
Output
Buffer
Column
Buffer
SerialAddress
Counter
1 of 2 Sub-Blocks
(see next page)
SQ0 – SQ15
SC
SplitRegister
Status
16
QSF
SE
SerialOutput
Buffer
SE
RAS
CASx
TRG
Timing
Generator
WE
6
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
8-column functional block diagram (TMS5517x) (continued)
DSF
Input
Buffer
SpecialFunction
Logic
Color
Register
DRAM
Input
Buffer
W/B
Unlatch
MUX
W/B
Latch
Address
Mask
WritePer-Bit
Control
DQx
DQx + 1
DQx + 2
DQx + 3
DQx + 4
DQx + 5
DQx + 6
DQx + 7
DRAM
Output
Buffer
Refresh
Counter
Sense AMP
512 × 512
Memory
Array
RAS
CASx
TRG
WE
Timing
Generator
Row
Buffer
Column DEC
A0 – A8
Row
Decoder
Serial-Data
Register
Serial-Data
Pointer
SQx
SQx + 1
SQx + 2
SQx + 3
SQx + 4
SQx + 5
SQx + 6
SQx + 7
Column
Buffer
SerialAddress
Counter
SC
SplitRegister
Status
Serial
Output
Buffer
QSF
1 of 2 Sub-Blocks
SE
SE
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
Table 2. Function Table
CASx
FALL
RAS FALL
ADDRESS
DQ0 – DQ15 †
FUNCTION
MNEMONIC
CODE
CASx‡
TRG
WE
DSF
DSF
RAS
CASx§
RAS
CASL
CASU
WE
Reserved (do not use)
L
L
L
L
X
X
X
X
X
—
CBR refresh (no reset) and stop-point set ¶
L
X
L
H
X
Stop
Point #
X
X
X
CBRS
CBR refresh (option reset)||
L
X
H
L
X
X
X
X
X
CBR
CBR refresh (no reset)k
L
X
H
H
X
X
X
X
X
CBRN
Tap
Point
X
X
RT
Full-register transfer
H
L
H
L
X
Row
Addr
Split-register transfer
H
L
H
H
X
Row
Addr
Tap
Point
X
X
SRT
DRAM write (nonmasked)
H
H
H
L
L
Row
Addr
Col
Addr
X
Valid
Data
RW
DRAM write (nonpersistent write-per-bit)
H
H
L
L
L
Row
Addr
Col
Addr
Write
Mask
Valid
Data
RWM
DRAM write (persistent write-per-bit)
H
H
L
L
L
Row
Addr
Col
Addr
X
Valid
Data
RWM
DRAM block write (nonmasked)h
H
H
H
L
H
Row
Addr
Block
Addr
X
Col
Mask
BW
DRAM block write (nonpersistent write-per-bit)h
H
H
L
L
H
Row
Addr
Block
Addr
Write
Mask
Col
Mask
BWM
DRAM block write (persistent write-per-bit)h
H
H
L
L
H
Row
Addr
Block
Addr
X
Col
Mask
BWM
Load write-mask register ◊
H
H
H
H
L
Refresh
Addr
X
X
Write
Mask
LMR
Load color register
H
H
H
H
H
Refresh
Addr
X
X
Color
Data
LCR
Legend:
X
= Don’t care
Col Mask
= H: Write to address/column enabled
Write Mask = H: Write to I/O enabled
† DQ0 – DQ15 are latched on either the falling edge of WE or the first falling edge of CASx, whichever occurs later.
‡ Logic L is selected when either or both CASL and CASU are low.
§ The column address, the block address, or the tap point is latched on the first falling edge of CASx depending upon which function is executed.
¶ CBRS cycle should be performed immediately after the power-up initialization for stop-point mode.
# A0 – A3, A8: don’t care; A4 – A7 : stop-point code
|| CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode.
k CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode.
h For 4-column block write (TMS5516x), block address is A2 – A8; for 8-column block write (TMS5517x), block address is A3 – A8.
◊ Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option reset)
cycle.
8
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
Table 3. Pin Description Versus Operational Mode
PIN
DRAM
TRANSFER
A0 – A8
Row, column address
Row address, tap point
RAS
Row-address strobe
Row-address strobe
CASL
CASU
Column-address strobe, DQ output enable
Tap-address strobe
DSF
Block-write enable
Load-write-mask-register enable
Load-color-register enable
CBR (option reset)
Split-register-transfer enable
TRG
DQ output enable
Transfer enable
WE
Write enable, write-per-bit enable
DQx
DRAM data I/O, write mask
SAM
SC
Serial clock
SE
SQ output enable,
QSF output enable
SQx
Serial-data output
QSF
Serial-register status
VCC†
VSS†
Power supply
Ground
NC/GND
Make no external connection or tie to system GND
† For proper device operation, all VCC pins must be connected to a 5.0-V supply and all VSS pins must be tied to ground.
pin definitions
address (A0 –A8)
Eighteen address bits are required to decode one of 262 144 storage cell locations. Nine row-address bits are
set up on pins A0 –A8 and latched onto the chip on the falling edge of RAS. Nine column-address bits are set
up on pins A0 –A8 and latched onto the chip on the first falling edge of CASx. All addresses must be stable on
or before the falling edge of RAS and the first falling edge of CASx.
In 4-column block-write operations (TMS5516x), column-address bits A0– A1 are ignored. Column-address bits
A2– A8 become the block address that selects one of the 128 blocks in the active row. In 8-column block write
operations (TMS5517x), column-address bits A0 – A2 are ignored. Column address bits A3 – A8 become the
block address that selects one of the 64 blocks in the active row.
In full-register operations, column-address bit A8 selects which half of the active row in the DRAM is transferred
to the SAM. Column address bits A0 –A7 select one of 256 tap points (starting positions) for the serial-data
output.
In split-register-transfer operations, column address bit A8 selects the DRAM half row. Column-address bit A7
is ignored. The internal serial-address counter identifies which half of the SAM is in use. If the high half of the
SAM is in use, the low half of the SAM is loaded with the low half of the DRAM half row, and vice versa.
Column-address bits A0 – A6 select one of 127 tap points (starting locations) for the serial output. Locations 127
and 255 are not valid tap points in split-register-transfer operations. In stop-point mode, stop-point locations are
not valid tap points in split-register-transfer operations.
row-address strobe (RAS)
The falling edge of RAS latches the states of the row address, CASL, CASU, DSF, TRG, WE, and the DQs onto
the chip to initiate DRAM and transfer functions. RAS also functions as a DRAM output enable.
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
column-address strobe (CASL, CASU)
The first falling edge of CASx latches the states of the column address and DSF onto the chip to control DRAM
and transfer functions. CASL and CASU provide byte control in DRAM operations. CASL controls the lower byte
(DQ0– DQ7), and CASU controls the upper byte (DQ8 – DQ15). Byte control can be applied in read cycles, write
cycles, block-write cycles, load-write-mask-register cycles, and load-color-register cycles. CASx also functions
as a DRAM output enable.
special-function select (DSF)
DSF is latched on the falling edge of RAS and the falling edge of CASx to determine which functions are invoked
on a particular cycle (see Table 2).
output enable, transfer select (TRG)
TRG selects either DRAM or transfer operation as RAS falls. Holding TRG high on the falling edge of RAS
selects the DRAM operation. Dropping TRG low on the falling edge of RAS selects the transfer operation. TRG
also functions as DRAM output enable.
write enable, write-per-bit select (WE)
WE selects either the write mode or the read mode in a CASx cycle. Dropping WE low selects the write mode.
Holding WE high selects the read mode. Holding WE low on the falling edge of RAS selects the write-per-bit
operation.
DRAM data I/O, write mask, column mask (DQ0 – DQ15)
DQ0– DQ15 function as the DRAM input / output port in DRAM operations. In normal DRAM write cycles, all
16 bits of write data are latched on either the falling edge of WE or the first falling edge of CASx, whichever
occurs later. Similarly, the DQs are latched as write mask in load-mask-register cycles, as color data in
load-color-register cycles, and as column mask in block-write cycles. In non-persistent write-per-bit cycles, the
DQs are latched as the write mask on the falling edge of RAS.
Data out is in the same polarity as data in. The 3-state output buffer provides direct TTL compatibility (no pullup
resistor required) with a fan-out of one Series 74 TTL load. The outputs are in the high-impedance (floating) state
until RAS, CASx, and TRG have all been brought low in read cycles. For the TMS551x0 devices, the outputs
remain valid until CASx is brought high, TRG is brought high, or WE is brought low. For the TMS551x1 devices,
the outputs remain valid until both RAS and CASx are brought high, TRG is brought high, or WE is brought low.
serial clock (SC)
The rising edge of SC increments the internal serial-address counter and accesses serial data at the next SAM
location.
serial enable (SE)
SE functions as the output enable for SQ0 – SQ15 and QSF. SE low enables the serial-data output. SE high
disables the serial-data output. Holding SE high does not disable the serial clock SC. The rising edge of SC
automatically increments the internal serial-address counter regardless of the state of SE.
serial data outputs (SQ0 – SQ15)
SQ0– SQ15 function as the SAM output port. The 3-state output buffer provides direct TTL compatibility (no
pullup resistors) with a fan-out of one Series 74 TTL load. Serial data is accessed from the SAM on the rising
edge of SC. SE low enables the outputs. The outputs are in the high-impedance (floating) state when disabled.
special-function output (QSF)
QSF is an output pin that indicates which half of the SAM is being accessed. QSF is low when the internal
serial-address counter points to the lower (least significant) 128 bits of the SAM. QSF is high when the internal
serial-address counter points to the higher (most significant) 128 bits of SAM. QSF is in the high-impedance
state when SE is high.
10
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
functional operation description
random-access operation
Table 4. DRAM Function Table
CASx
FALL
RAS FALL
ADDRESS
DQ0 – DQ15†
FUNCTION
Reserved (do not use)
MNEMONIC
CODE
RAS
CASx§
RAS
CASL
CASU
WE
X
X
X
X
X
—
X
X
X
CBRS
X
X
X
CBR
CASx‡
TRG
WE
DSF
DSF
L
L
L
L
CBR refresh (no reset) and stop-point set¶
L
X
L
H
X
Stop
Point #
CBR refresh (option reset)||
L
X
H
L
X
X
CBR refresh (no reset)k
L
X
H
H
X
X
X
X
X
CBRN
Col
Addr
X
Valid
Data
RW
DRAM write (nonmasked)
H
H
H
L
L
Row
Addr
DRAM write (nonpersistent write-per-bit)
H
H
L
L
L
Row
Addr
Col
Addr
Write
Mask
Valid
Data
RWM
DRAM write (persistent write-per-bit)
H
H
L
L
L
Row
Addr
Col
Addr
X
Valid
Data
RWM
DRAM block write (nonmasked)h
H
H
H
L
H
Row
Addr
Block
Addr
X
Col
Mask
BW
DRAM block write (nonpersistent write-per-bit)h
H
H
L
L
H
Row
Addr
Block
Addr
Write
Mask
Col
Mask
BWM
DRAM block write (persistent write-per-bit)h
H
H
L
L
H
Row
Addr
Block
Addr
X
Col
Mask
BWM
Load write-mask register ◊
H
H
H
H
L
Refresh
Addr
X
X
Write
Mask
LMR
Load color register
H
H
H
H
H
Refresh
Addr
X
X
Color
Data
LCR
Legend:
X
= Don’t care
Col Mask
= H: Write to address/column enabled
Write Mask = H: Write to I/O enabled
† DQ0 – DQ15 are latched on either the falling edge of WE or the first falling edge of CASx, whichever occurs later.
‡ Logic L is selected when either or both CASL and CASU are low.
§ The column address, the block address, or the tap point is latched on the first falling edge of CASx depending upon which function is executed.
¶ CBRS cycle should be performed immediately after the power-up initialization for stop-point mode.
# A0 – A3, A8: don’t care; A4 – A7 : stop-point code
|| CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode.
k CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode.
h For 4-column block write (TMS5516x), block address is A2 – A8; for 8-column block write (TMS5517x), block address is A3 – A8.
◊ Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option reset)
cycle.
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
refresh
CAS-before-RAS (CBR) refresh
CBR refreshes are accomplished by bringing either or both CASL and CASU low earlier than RAS. The external
row address is ignored, and the refresh row address is generated internally. Three types of CBR refresh cycles
are available. The CBR refresh (option reset) ends the persistent write-per-bit mode and the stop-point mode.
The CBRN (no reset) and CBRS (no reset and stop point set) refreshes do not end the persistent write-per-bit
mode or the stop-point mode. The 512 rows of the DRAM do not necessarily need to be refreshed consecutively
as long as the entire refresh is completed within the required time period, trf(MA). The output buffers remain in
the high-impedance state during the CBR type refresh cycles regardless of the state of TRG.
hidden refresh
A hidden refresh is accomplished by holding either or both CASL and CASU low in the DRAM read cycle and
cycling RAS. The output data of the DRAM read cycle remains valid while the refresh is carried out. Like the
CBR refresh, the refreshed row addresses are generated internally during the hidden refresh.
RAS-only refresh
A RAS-only refresh is accomplished by cycling RAS at every row address. Unless CASx and TRG are low, the
output buffers remain in the high-impedance state to conserve power. Externally generated addresses must be
supplied during RAS-only refresh. Strobing each of the 512 row addresses with RAS causes all bits in each row
to be refreshed.
enhanced page mode (TMS551x0)
Enhanced page mode allows faster memory access by keeping the same row address while selecting random
column addresses. The maximum RAS low time and minimum CASx page cycle time are used to determine
the number of columns that can be accessed.
Unlike conventional page mode, the enhanced page mode allows the TMS551x0 to operate at a higher data
bandwidth. Data retrieval begins as soon as the column address is valid rather than when CASx goes low. A
valid column address can be presented immediately after the row-address hold time has been satisfied, usually
well in advance of the falling edge of CASx. In this case, data is obtained after ta(C) max (access time from CASx
low) if ta(CA) max (access time from column address) has been satisfied.
extended data output ( TMS551x1)
The TMS551x1 features extended data output during DRAM accesses. While RAS and TRG are low, the DRAM
output remains valid even when CASx returns high. The output remains valid until WE is low, TRG is high, or
both CASx and RAS are high (see Figure 1, Figure 2, and Figure 3). The extended data-output mode functions
in all read cycles including DRAM read, page-mode read, and read-modify-write cycles.
RAS
CASx
tdis(RH)†
Valid Output
DQ0 – DQ15
TRG
† See “switching characteristics over recommended ranges of supply voltage and operating free-air temperature” table.
Figure 1. DRAM Read Cycle With RAS-Controlled Output (TMS551x1)
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extended data output (TMS551x1) (continued)
RAS
CASx
tdis(CH)†
DQ0 – DQ15
Valid Output
TRG
† See “switching characteristics over recommended ranges of supply voltage and operating free-air temperature” table.
Figure 2. DRAM Read Cycle With CAS-Controlled Output (TMS551x1)
RAS
CASx
A0 – A8
Row
Column
Column
ta(CP)†
ta(C)†
ta(C)†
ta(CA)†
ta(CA)†
th(CLQ)‡
Valid Output
DQ0 – DQ15
tdis(RH)†
Valid Output
tdis(G)†
TRG
† See “switching characteristics over recommended ranges of supply voltage and operating free-air temperature” table.
‡ See “timing requirements over recommended ranges of supply voltage and operating free-air temperature” table.
Figure 3. DRAM Page-Read Cycle With Extended Data Output (TMS551x1)
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byte operation
Byte operation can be applied in DRAM read cycles, write cycles, block-write cycles, load-write-mask-register
cycles and load-color-register cycles. In byte operation, the column address (A0 –A8) is latched at the first falling
edge of CASx. In read cycles, CASL enables the lower byte (DQ0 –DQ7) and CASU enables the upper byte
(DQ8– DQ15) (see Figure 4).
RAS
CASL
tsu(CA)†
CASU
th(CLCA)†
A0 – A8
Column
Row
ta(C)‡
Lower Byte Output
DQ0 – DQ7
ta(C)‡
Upper Byte
Output
DQ8 – DQ15
ta(G)‡
TRG
† See “switching characteristics over recommended ranges of supply voltage and operating free-air temperature” table.
‡ See “timing requirements over recommended ranges of supply voltage and operating free-air temperature” table.
Figure 4. Example of a Byte-Read Cycle
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byte operation (continued)
In byte-write operation, CASL enables data to be written to the lower byte (DQ0 –DQ7) and CASU enables data
to be written to the upper byte (DQ8 – DQ15). In an early-write cycle, WE is brought low prior to both CASx
signals. Data setup and hold times for DQ0 – DQ15 are referenced to the first falling edge of CASx
(see Figure 5).
RAS
WE
CASL
tsu(CA)†
CASU
th(CLCA)†
A0 – A8
Row
Column
tsu(DCL)†
th(CLD)†
DQ0 – DQ15
Valid Input
† See “switching characteristics over recommended ranges of supply voltage and operating free-air temperature” table.
Figure 5. Example of an Early-Write Cycle
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byte operation (continued)
For late-write or read-modify-write cycles, WE is brought low after either or both CASL and CASU fall. The data
is strobed in with data setup and hold times for DQ0 – DQ15 referenced to WE (see Figure 6).
RAS
CASL
CASU
WE
tsu(DWL)†
th(WLD)†
DQ0 – DQ15
Valid Input
† See “timing requirements over recommended ranges of supply voltage and operating free-air temperature” table.
Figure 6. Example of a Late-Write Cycle
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write-per-bit
The write-per-bit function allows the masking of any combination of the 16 DQs on any write cycle. The
write-per-bit operation is invoked when WE is held low on the falling edge of RAS. If WE is held high on the falling
edge of RAS, the write operation is performed without any masking. There are two write-per-bit modes: the
nonpersistent write-per-bit and the persistent write-per-bit.
nonpersistent write-per-bit
When WE is low on the falling edge of RAS, the write mask is reloaded. A 16-bit binary code (the write-per-bit
mask) is input to the device through the DQ pins and latched on the falling edge of RAS. The write-per-bit mask
selects which of the 16 DQs are to be written and which are not. After RAS has latched the on-chip write-per-bit
mask, input data is driven onto the DQ pins and is latched on either the falling edge of WE or the first falling edge
of CASx, whichever occurs later. CASL enables the lower byte (DQ0 – DQ7) to be written through the mask and
CASU enables the upper byte (DQ8 – DQ15) to be written through the mask. If a write-mask-low (write
mask = 0) is strobed into a particular DQ pin on the falling edge of RAS, data is not written to that DQ. If a
write-mask-high (write mask = 1) is strobed into a particular DQ pin on the falling edge of RAS, data is written
to that DQ (see Figure 7).
RAS
CASL
CASU
WE
tsu(DQR)†
th(WLD)†
th(RDQ)†
tsu(DWL)†
DQ0 – DQ15
Write Mask
Valid Input
† See “timing requirements over recommended ranges of supply voltage and operating free-air temperature” table.
Figure 7. Example of a Nonpersistent Write-Per-Bit (Late-Write) Operation
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persistent write-per-bit
The persistent write-per-bit mode is initiated only by performing a load-write-mask-register (LMR) cycle first.
In the persistent write-per-bit mode, the write-per-bit mask is not overwritten but remains valid over an arbitrary
number of write cycles until another LMR cycle is performed or until power is removed.
The LMR cycle is performed using DRAM write-cycle timing except DSF is held high on the falling edge of RAS
and held low on the first falling edge of CASx. A binary code is input to the write-mask register through the
random I/O pins and latched on either the first falling edge of CASx or the falling edge of WE, whichever occurs
later. Byte-write control can be applied to the write mask during the LMR cycle. The persistent write-per-bit mode
can then be used in exactly the same way as the nonpersistent write-per-bit mode except that the input data
on the falling edge of RAS is ignored. When the device is set to the persistent write-per-bit mode, it remains in
this mode and is reset only by a CBR refresh with option reset cycle (see Figure 8).
Load Write-Mask Register
Persistent Write-Per-Bit
CBR Refresh (option reset)
RAS
CASx
A0 – A8
Refresh
Address
Row
Column
DSF
WE
DQ0 –
DQ15
Write-Mask
Data
Mask Data
Valid
Input
= 1: Write to DQ enabled
= 0: Write to DQ disabled
Figure 8. Example of a Persistent Write-Per-Bit Operation
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4-column block write (TMS5516x)
The 4-column block-write function allows up to 64 bits of data to be written simultaneously to one row of the
memory array. This function is implemented as 4 columns × 4 DQs and repeated in four quadrants. In this
manner, each of the four one-megabit quadrants can have up to four consecutive columns written at a time with
up to four DQs per column (see Figure 9).
DQ15
DQ14
4th Quadrant
DQ13
DQ12
DQ11
DQ10
3rd Quadrant
DQ9
DQ8
One Row of 0 – 511
DQ7
DQ6
2nd Quadrant
DQ5
DQ4
DQ3
DQ2
1st Quadrant
DQ1
DQ0
Four Consecutive Columns of 0 – 511
Figure 9. 4-Column Block-Write Operation
Each one-megabit quadrant has a 4-bit column mask to mask off any or all of the four columns from being written
with data. Nonpersistent write-per-bit or persistent write-per-bit functions can be applied to the block-write
operation to provide write-masking options. Write data (color data) is provided by four bits from the on-chip color
register. Bits 0 – 3 from the 16-bit write-mask register, bits 0 – 3 from the 16-bit column-mask register, and
bits 0 – 3 from the 16-bit color-data register configure the block write for the first quadrant, while bits 4 – 7, 8 – 11,
and 12 – 15 of the corresponding registers control the other quadrants in a similar fashion (see Figure 10).
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4-column block write (continued)
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
12
13
14
15
DQ9
DQ8
One Row of 0 – 511
DQ7
DQ6
8
9
10
11
DQ5
DQ4
DQ3
DQ2
4
5
6
7
DQ1
Column Mask
DQ0
0
1
2
3
3
7
Write Mask
2
1
2
3
4
5
6
7
8
9 10 11
Figure 10. 4-Column Block Write With Masks
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Color Register
20
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1
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4-column block write (continued)
Every four adjacent columns makes a block, which results in 128 blocks along one row. Block 0 comprises
columns 0 – 3, block 1 comprises columns 4 – 7, block 2 comprises columns 8 – 11, etc., as shown in Figure 11.
Block 0
......................
Block 1
Block 127
One Row of 0 – 511
0
1
2
3
4
5
6
7
...........................
511
Columns
Figure 11. 4-Column-Block Column-Organization
During 4-column block-write cycles, only the seven most significant column addresses (A2 – A8) are latched on
the falling edge of CASx to decode one of the 128 blocks. Address bits A0 – A1 are ignored. All one-megabit
quadrants have the same block selected.
A block-write cycle is entered in a manner similar to a DRAM write cycle except DSF is held high on the falling
edge of CASx. As in a DRAM write operation, CASL and CASU enable the corresponding lower and upper
DRAM DQ bytes to be written, respectively. The column-mask data is input through the DQs and is latched on
either the falling edge of WE or the first falling edge of CASx, whichever occurs later. The 16-bit color-data
register must be loaded prior to performing a block write as described below. Refer to the write-per-bit section
for details on the use of the write-mask capability, allowing additional performance options.
Example of block write:
block-write column address
color-data register
write-mask register
column-mask register
= 110000000 (A0 – A8 from left to right)
bit 0
= 1011
= 1110
= 1111
1st
Quad
1011
1111
0000
2nd
Quad
1100
1111
0111
3rd
Quad
bit 15
0111
1011
1010
4th
Quad
Column-address bits A0 and A1 are ignored. Block 0 (columns 0 – 3) is selected for all one-megabit quadrants.
The first quadrant has DQ0 – DQ2 written with bits 0 – 2 from the color-data register to all four columns of
block 0. DQ3 is not written and retains its previous data due to the write-mask bit 3 being a 0.
The second quadrant (DQ4 – DQ7) has all four columns masked off due to the column-mask bits 4 – 7 being 0,
so that no data is written.
The third quadrant (DQ8 – DQ11 ) has its four DQs written with bits 8 – 11 from the color-data register to columns
1 – 3 of its block 0. Column 0 is not written and retains its previous data on all four DQs due to the
column-mask bit 8 being 0.
The fourth quadrant (DQ12 – DQ15) has DQ12, DQ14, and DQ15 written with bits 12, 14, and 15 from the
color-data register to column 0 and column 2 of its block 0. DQ13 retains its previous data on all columns due
to the write mask. Columns 1 and 3 retain their previous data on all DQs due to the column mask. If the previous
data for the quadrant was all 0s, the fourth quadrant would contain the data pattern shown in Figure 12 after
the 4-column block-write operation shown in the example.
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4-column block write (continued)
DQ15 1
DQ14 1
0
1
0
1
0
0
4th Quadrant
DQ13 0
0
DQ12 0
0
0
0
Columns 0
1
2
3
0
0
Figure 12. Example of Fourth Quadrant After 4-Column Block-Write Operation
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8-column block write (TMS5517x)
The 8-column block-write function allows up to 128 bits of data to be written simultaneously to one row of the
memory array. This function is implemented as 8 columns × 8 DQs and repeated in two bytes. In this manner,
each of the two bytes can have up to eight consecutive columns written at a time with up to eight DQs per column
(see Figure 13).
DQ15
DQ14
DQ13
DQ12
Upper Byte
DQ11
DQ10
DQ9
DQ8
One Row of 0 – 511
DQ7
DQ6
DQ5
DQ4
Lower Byte
DQ3
DQ2
DQ1
DQ0
Eight Consecutive Columns of 0 – 511
Figure 13. 8-Column Block-Write Operation
Each byte has an 8-bit column mask to mask off any or all of the eight columns from being written with data.
Nonpersistent write-per-bit or persistent write-per-bit functions can be applied to the block-write operation to
provide write-masking options. Write data (color data) is provided by eight bits from the on-chip color register.
Bits 0 – 7 from the 16-bit write-mask register, bits 0 – 7 from the 16-bit column-mask register, and bits 0 – 7 from
the 16-bit color-data register configure the block write for the lower byte, while bits 8 – 15 control the upper byte
in a similar fashion (see Figure 14).
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8-column block write (TMS5517x) (continued)
Lower Byte
Upper Byte
Column Mask
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
One Row of 0–511
Write Mask
Write Mask
Column Mask
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
9
10
11
12
13
14
15
8
9
10
11
12
13
14
15
7
8
9
10 11 12 13 14 15
Color Register
Figure 14. 8-Column Block Write With Masks
Every eight adjacent columns makes a block resulting in 64 blocks along one row. Block 0 comprises
columns 0 – 7, block 1 comprises columns 8 – 15, block 2 comprises columns 16 – 23, etc., as shown in
Figure 15.
Block 0
Block 63
One Row of 0 – 511
0
1
2
3
4
5
6
7
.............
504
505
506
507 508
509
510
511
Columns
Figure 15. 8-Column-Block Column-Organization
During 8-column block-write cycles, only the six most significant column addresses (A3 – A8) are latched on the
falling edge of CASx to decode one of the 64 blocks. Address bits A0 – A2 are ignored. Both bytes have the same
block selected.
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8-column block write (continued)
A block-write cycle is entered in a manner similar to a DRAM write cycle except DSF is held high on the first
falling edge of CASx. As in a DRAM write operation, CASL and CASU enable the corresponding lower and upper
DRAM DQ bytes to be written, respectively. The column-mask data is input through the DQs and is latched on
either the falling edge of WE or the first falling edge of CASx, whichever occurs later. The 16-bit color-data
register must be loaded prior to performing a block write as described below. Refer to the write-per-bit section
for details on use of the write-mask capability allowing additional performance options.
Example of block write:
block-write column address
=
110000000 (A0 – A8 from left to right)
bit 0
bit 15
color-data register =
10111011
11000111
write-mask register =
11101111
11111011
column-mask register =
11110000
01111010
Lower
Byte
Upper
Byte
Column-address bits A0 – A2 are ignored. Block 0 (columns 0 – 7) is selected for both bytes. The lower byte has
DQ0 – DQ2 and DQ4 – DQ7 written with bits 0 – 2 and 4 – 7 from the color-data register to columns 0 – 3.
Columns 4 – 7 are not written and retain their previous data due to the column-mask bits 4– 7 being 0. DQ3 is
not written and retains its previous data due to the write-mask bit 3 being 0.
The upper byte has DQ8 – DQ12 and DQ14 – DQ15 written with bits 8 – 12 and 14 – 15 from the color-data
register to columns 1 – 4 and 6. Columns 0, 5, and 7 are not written and retain their previous data due to the
column-mask bits 8, 13, and 15 being 0. DQ13 is not written and retains its previous data due to the
write-mask-register bit 13 being 0. If the previous data was all 0s, the upper byte would contain the data pattern
in Figure 16 after the 8-column block-write operation shown in the example.
DQ15 0 1 1 1 1 0 1 0
DQ14 0 1 1 1 1 0 1 0
DQ13 0 0 0 0 0 0 0 0
DQ12 0 0 0 0 0 0 0 0
DQ11 0 0 0 0 0 0 0 0
DQ10
DQ9
DQ8
Upper Byte
0 0 0 0 0 0 0 0
0 1 1 1 1 0 1 0
0 1 1 1 1 0 1 0
Columns 0 1 2 3 4 5 6 7
Figure 16. Example of Upper Byte After 8-Column Block-Write Operation
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load color register
The load-color-register cycle is performed using normal DRAM write-cycle timing except that DSF is held high
on the falling edges of RAS and on the first falling edge of CASx. The color register is loaded from pins
DQ0 – DQ15, which are latched on either the falling edge of WE or the first falling edge of CASx, whichever
occurs later. If only one CASx is low, only the corresponding byte of the color register is loaded. When the color
register is loaded, it retains data until power is lost or until another load-color-register cycle is performed (see
Figure 17 and Figure 18).
Load-Color-Register Cycle
Block-Write Cycle
(no write mask)
Block-Write Cycle
(nonpersistent write-per-bit)
RAS
CASx
A0 – A8
1
2
3
2
3
WE
TRG
DSF
DQ0 – DQ15
6
4
5
6
Legend:
1. Refresh address: A0 – A8 are latched on the falling edge of RAS.
2. Row address: A0 – A8 are latched on the falling edge of RAS.
3. Block address A2 – A8 (TMS5516x) or A3 – A8 (TMS5517x) are latched on the first falling edge of CASx.
4. Color data: DQ0 – DQ15 are latched on the falling edge WE or on the first falling edge of CASx, whichever occurs first.
5. Write-mask data: DQ0 – DQ15 are latched on the falling edge RAS.
6. Column-mask data: DQ0 – DQ15 are latched on the falling edge WE or on the first falling edge of CASx, whichever occurs first.
= don’t care
Figure 17. Example of Block Writes
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load color register (continued)
Load-Mask-Register Cycle
Persistent Write-Per-Bit
Block-Write Cycle
Load-Color-Register Cycle
RAS
CASx
A0 – A8
1
2
1
3
WE
TRG
DSF
DQ0 – DQ15
5
6
4
Legend:
1. Refresh address: A0 – A8 are latched on the falling edge of RAS.
2. Row address: A0 – A8 are latched on the falling edge of RAS.
3. Block address A2 – A8 (TMS5516x) or A3 – A8 (TMS5517x) are latched on the first falling edge of CASx.
4. Color data: DQ0 – DQ15 are latched on the falling edge WE or on the first falling edge of CASx, whichever occurs first.
5. Write-mask data: DQ0 – DQ15 are latched on the falling edge RAS.
6. Column-mask data: DQ0 – DQ15 are latched on the falling edge WE or on the first falling edge of CASx, whichever occurs first.
= don’t care
Figure 18. Example of a Persistent Block Write
DRAM-to-SAM transfer operation
During the DRAM-to-SAM transfer operation, one-half of a row (256 columns) in the DRAM array is selected
to be transferred to the 256-bit serial-data register. The transfer operation is invoked by bringing TRG low and
holding WE high on the falling edge of RAS. The state of DSF, which is latched on the falling edge of RAS,
determines whether the full-register-transfer operation or the split-register-transfer operation is performed.
Table 5. SAM Function Table
CASx
FALL
RAS FALL
FUNCTION
ADDRESS
DQ0 – DQ15
MNEMONIC
CODE
CASx†
TRG
WE
DSF
DSF
RAS
CASx
RAS
CASx
WE
Full-register-transfer read
H
L
H
L
X
Row
Addr
Tap
Point
X
X
RT
Split-register-transfer read
H
L
H
H
X
Row
Addr
Tap
Point
X
X
SRT
† Logic L is selected when either or both CASL and CASU are low.
X = don’t care
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full-register-transfer read
A full-register-transfer operation loads data from a selected half of a row in the DRAM into the SAM. TRG is
brought low and latched at the falling edge of RAS. Nine row-address bits (A0 – A8) are also latched at the falling
edge of RAS to select one of the 512 rows available for the transfer. The nine column-address bits (A0 – A8)
are latched at the first falling edge of CASx, where address bit A8 selects which half of the row is transferred.
Address bits A0 – A7 select one of the SAM’s 256 available tap points from which the serial data is read out (see
Figure 19).
A8 = 0
0
255 256
A8 = 1
511
512 × 512
Memory Array
256-Bit
Data Register
0
255
Figure 19. Full-Register-Transfer Read
A full-register transfer can be performed in three ways: early load, real-time load (or midline load), or late load.
Each of these offers the flexibility of controlling the TRG trailing edge in the full-register-transfer cycle
(see Figure 20).
Early Load
Real-Time Load
Late Load
RAS
CASx
A0 – A8
Row
Tap
Point
Row
Tap
Point
Row
Tap
Point
TRG
WE
SC
Old
Data
Tap
Bit
Old
Data
Old
Data
Tap
Bit
Old
Data
Figure 20. Example of Full-Register-Transfer Read Operations
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Data
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Bit
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SMVS464 – MARCH1996
split-register-transfer read
In split-register-transfer operations, the serial-data register is split into halves (see Figure 21). The low half
contains bits 0 – 127, and the high half contains bits 128 – 255. While one half is being read out of the SAM port,
the other half can be loaded from the memory array.
A8 = 0
0
255 256
A8 = 1
511
512 × 512
Memory Array
256 - Bit
Data Register
0
255
Figure 21. Split-Register-Transfer Read
To invoke a split-register-transfer cycle, DSF is brought high, TRG is brought low, and both are latched at the
falling edge of RAS (see Figure 22). Nine row-address bits (A0 – A8) are also latched at the falling edge of RAS
to select one of the 512 rows available for the transfer. Eight of the nine column-address bits (A0 – A6 and A8)
are latched at the first falling edge of CASx. Column-address bit A8 selects which half of the row is to be
transferred. Column-address bit A7 is ignored, and the split-register transfer is internally controlled to select the
inactive half. Column-address bits A0 – A6 select one of 127 tap points in the specified half of SAM. Locations
127 and 255 are not valid tap points in split-register-transfer operations. In stop-point mode, stop-point locations
are not valid tap points in split-register-transfer operations.
Full XFER
RAS
Split XFER
Split XFER
A8 = 1
A8 = 1
A8 = 0
0
511
A
B
A7 = 0† 511
0
A
B
C
Split XFER
A8 = 0
A7 = 1† 511
0
A
B
C
0 A7 = 0†
D
A
C
E
D
D
E
DRAM
0
SAM
511
B
255
A
0
B
255
C
SQ
† A7 shown is internally controlled.
0
B
255
C
0
D
SQ
SQ
255
SQ
Figure 22. Example of a Split-Register-Transfer Read Operation
A full-register transfer must precede the first split-register transfer to ensure proper operation. After the
full-register transfer cycle, the first split-register transfer can follow immediately without any minimum SC clock
requirement.
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
split-register-transfer read (continued)
QSF indicates which half of the register is being accessed during serial-access operation. When QSF is low,
the serial-address pointer is accessing the lower (least significant) 128 bits of SAM. When QSF is high, the
pointer is accessing the higher (most significant) 128 bits of SAM. QSF changes state upon completing a
full-register-transfer read cycle. The tap point loaded during the current transfer cycle determines the state of
QSF. QSF also changes state when a boundary between two register halves is reached.
Full-Register-Transfer Read
With Tap Point N
Split-RegisterTransfer Read
RAS
CASx
TRG
DSF
SC
Tap
Point N
td(CLQSF)
td(GHQSF)
QSF
NOTE A: See “timing requirements over recommended ranges of supply voltage and operating free-air temperature” table.
Figure 23. Example of a Split-Register-Transfer Read After a Full-Register-Transfer Read
Split-RegisterTransfer Read
With Tap Point N
Split-RegisterTransfer Read
RAS
CASx
TRG
DSF
td(MSRL)
td(RHMS)
SC
127
or 255
Tap
Point N
td(SCQSF)
QSF
NOTE A: See “timing requirements over recommended ranges of supply voltage and operating free-air temperature” table.
Figure 24. Example of Successive Split-Register-Transfer Read Operations
30
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262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
serial-read operation
The serial-read operation can be performed through the SAM port simultaneously and asynchronously with
DRAM operations except during transfer operations. Serial data is accessed from the SAM at the rising edge
of serial clock SC. SE low enables the outputs. SE high disables the outputs. Holding SE high does not disable
SC. The rising edge of SC automatically increments the internal serial-address counter regardless of the state
of SE. In full-register-transfer operations, the counter proceeds sequentially to the most significant bit (bit 255),
and then wraps around to the least significant bit (bit 0), as shown in Figure 25.
0
1
2
Tap
254
255
Figure 25. Serial-Pointer Direction for Serial Read
In split-register-transfer operations, serial data can be read out from the active half of SAM by clocking SC
starting at the tap point loaded by the preceding split-register-transfer cycle. The serial pointer then proceeds
sequentially to the most significant bit of the half, bit 127 or bit 255. If there is a split-register-transfer read to
the inactive half during this period, the serial pointer points next to the tap point location loaded by that
split-register-transfer (see Figure 26).
0
Tap
126
127
128
Tap
254
255
Figure 26. Serial Pointer for Split-Register Read – Case I
If there is no split-register transfer to the inactive half during this period, the serial pointer points to the next bit,
bit 128 or bit 0, respectively (see Figure 27).
0
Tap
126
127
128
Tap
254
255
Figure 27. Serial Pointer for Split-Register Read – Case II
split-register programmable stop point
The TMS551xx offers programmable stop-point mode for split-register-transfer read operation. This mode can
be used to improve 2-D drawing performance in a nonscanline data format.
In split-register-transfer read operations, the stop point is defined as a register location at which the serial output
stops coming from one half of the SAM and switches to the opposite half of the SAM. While in stop-point mode,
the SAM is divided into partitions whose length is programmed on row addresses A4– A7 in a CBR set (CBRS)
cycle. The last serial-address location of each partition is the stop point (see Figure 28).
127
0
128
255
Partition
Length
Stop
Points
Figure 28. Example of SAM With Partitions
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
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split-register programmable stop point (continued)
Stop-point mode is not active until the CBRS cycle is initiated. The CBRS operation is performed by holding
CASx low, WE low, and DSF high on the falling edge of RAS. The falling edge of RAS also latches row addresses
A4– A7, which are used to define the SAM’s partition length. The other row-address inputs are don’t cares.
Stop-point mode should be initiated immediately after the power-up initialization (see Table 6).
Table 6. Programming Code for Stop-Point Mode
MAXIMUM
PARTITION
LENGTH
A8
A7
A6
A5
A4
A0 – A3
NUMBER OF
PARTITIONS
16
X
L
L
L
L
X
16
15, 31, 47, 63, 79, 95, 111, 127, 143, 159, 175,
191, 207, 223, 239, 255
32
X
L
L
L
H
X
8
31, 63, 95, 127, 159, 191, 223, 255
64
X
L
L
H
H
X
4
63, 127, 191, 255
128
(default)
X
L
H
H
H
X
2
127, 255
ADDRESS AT RAS IN CBRS CYCLE
STOP POINT LOCATIONS
STOP-POINT
In stop-point mode, the tap point loaded during the split-register-transfer read cycle determines in which SAM
partition the serial output begins and at which stop point the serial output stops coming from one half of SAM
and switches to the opposite half of SAM (see Figure 29).
RAS
Full
Read XFER
Split
Read XFER
Split
Read XFER
Split
Read XFER
Tap = H1
Tap = L1
Tap = H2
Tap = L2
H1
191
63
L1
H2
255
SC
0
L1
SAM Low Half
63
L2
127
128
H1
SAM High Half
191
H2
255
Figure 29. Example of Split-Register Operation With Programmable Stop Points
32
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262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
256-/512-bit compatibility of split-register programmable stop point
The stop-point mode is designed to be compatible with both 256-bit SAM and 512-bit SAM devices. After the
CBRS cycle is initiated, the stop-point mode becomes active. In the stop-point mode, and only in the stop-point
mode, the column-address bits AY7 and AY8 are swapped internally to assure compatibility (see Figure 29).
This address-bit swap applies to the column address, and it is effective for all DRAM and transfer cycles. For
example, during the split-register-transfer cycle with stop point, column-address bit AY8 is a don’t care and AY7
decodes the DRAM row half for the split-register-transfer. During stop-point mode, a CBR ( option reset ) cycle
is not recommended because this ends the stop-point mode and restores address bits AY7 and AY8 to their
normal functions. Consistent use of CBR cycles ensures that the TMS551xx remains in nomal mode.
NON STOP-POINT MODE
AY8 = 0
AY8 = 1
AY7 = 0 AY7 = 1 AY7 = 0 AY7 = 1
0
STOP-POINT MODE
AY8 = 0
AY8 = 1
AY7 = 0 AY7 = 1 AY7 = 0 AY7 = 1
512 × 512
Memory Array
512 × 512
Memory Array
256 - Bit
Data Register
256 - Bit
Data Register
255
0
255
Figure 30. DRAM-to-SAM Mapping, Nonstop-Point Versus Stop Point
IMPORTANT: For proper device operation, a stop-point-mode (CBRS) cycle should be initiated immediately
after the power-up initialization cycles are performed.
power up
To achieve proper device operation, an initial pause of 200 µs is required after power up followed by a minimum
of eight RAS cycles or eight CBR cycles to initialize the DRAM port. A full-register-transfer read cycle and two
SC cycles are required to initialize the SAM port.
After initialization, the internal state of the TMS551xx is as follows:
STATE AFTER INITIALIZATION
QSF
Write mode
Write-mask register
Color register
Serial-register tap point
SAM port
Defined by the transfer cycle during initialization
Nonpersistent mode
Undefined
Undefined
Defined by the transfer cycle during initialization
Output mode
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
TMS551xx
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Voltage range on any pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
TMS551xx
VCC
VSS
Supply voltage
VIH
VIL
High-level input voltage
MIN
NOM
MAX
4.5
5.0
5.5
Supply voltage
0
Low-level input voltage (see Note 2)
UNIT
V
V
2.4
6.5
V
–1.0
0.8
V
TA
Operating free-air temperature
0
70
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
34
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SMVS464 – MARCH1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TEST
CONDITIONS†
PARAMETER
VOH
VOL
High-level output voltage
SAM
PORT
’551xx-60
MIN
IOH = – 1 mA
IOL = 2 mA
Low-level output voltage
’551xx-70
MAX
2.4
II
Input current (leakage)
VCC = 5.5 V,
VI = 0 V to 5.8 V,
All other pins at 0 V to VCC
IO
Output current (leakage)
VCC = 5.5 V,
VO = 0 V to VCC, See Note 3
ICC1
ICC1A
Operating current ‡
Operating current‡
ICC2
ICC2A
Standby current
Standby current‡
ICC3
ICC3A
RAS only refresh current
RAS only refresh current‡
MIN
MAX
2.4
UNIT
V
0.4
0.4
V
± 10
± 10
µA
± 10
± 10
µA
See Note 4
Standby
180
165
mA
tc(SC) = MIN
All clocks = VCC
Active
225
205
mA
5
5
mA
tc(SC) = MIN
See Note 4
Active
Standby
Standby
tc(SC) = MIN,
See Note 4
Active
ICC4
Page mode current
c rrent‡
Page-mode
tc(P)
MIN,
(P) = MIN
See Note 5
Standby
ICC4A
P
Page-mode
d currentt ‡
tc(SC)
MIN,
(SC) = MIN
See Note 5
Active
ICC5
ICC5A
CBR current
CBR current‡
See Note 4
70
65
mA
180
165
mA
mA
225
205
’551x0
135
115
’551x1
140
140
’551x0
175
155
’551x1
185
185
180
165
mA
225
205
mA
200
180
mA
250
225
mA
Standby
tc(SC) = MIN,
See Note 4
Active
ICC6
Data-transfer current
See Note 4
Standby
‡
ICC6A Data-transfer current
tc(SC) = MIN
Active
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
NOTES: 3. SE is disabled for SQ output leakage tests.
4. Measured with one address change while RAS = VIL; tc(rd ), tc( W ), tc(TRD) = MIN
5. Measured with one address change while CASx = VIH
mA
mA
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 6)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, address inputs
6
pF
Ci(RC)
Input capacitance, address strobe inputs
7
pF
Ci(W)
Input capacitance, write enable input
7
pF
Ci(SC)
Input capacitance, serial clock
7
pF
Ci(SE)
Input capacitance, serial enable
7
pF
Ci(DSF)
Input capacitance, special function
7
pF
Ci(TRG)
Input capacitance, transfer register input
7
pF
Co(O)
Output capacitance, SQ and DQ
7
pF
Co(QSF)
Output capacitance, QSF
9
pF
NOTE 6: VCC = 5 V ± 0.5 V, and the bias on pins under test is 0 V.
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switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 7)
PARAMETER
TEST
CONDITIONS †
ALT.
SYMBOL
’551xx-60
’551xx-70
MIN
MIN
MAX
MAX
UNIT
ta(C)
ta(CA)
Access time, DQx from CASx low
td(RLCL) = MAX
td(RLCL) = MAX
tCAC
tAA
17
20
ns
Access time, DQx from column address
30
35
ns
ta(CP)
ta(G)
Access time, DQx from CASx high
td(RLCL) = MAX
tCPA
tOEA
35
40
ns
15
20
ns
ta(R)
ta(SE)
Access time, DQx from RAS low
tRAC
tSEA
60
70
ns
Access time, SQx from SE low
td(RLCL) = MAX
CL = 30 pF
12
15
ns
ta(SQ)
Access time, SQx from SC high
CL = 30 pF
tSCA
15
20
ns
tdis(CH)
Disable time, random output from CASx high
(see Note 8)
CL = 50 pF
tOFF
3
15
3
20
ns
tdis(G)
Disable time, random output from TRG high
(see Note 8)
CL = 50 pF
tOEZ
3
15
3
20
ns
tdis(RH)
Disable time, random output from RAS high
(see Note 8)
CL = 50 pF
3
15
3
20
ns
tdis(SE)
Disable time, serial output from SE high (see Note 8)
CL = 30 pF
tSEZ
3
10
3
20
ns
tdis(WL)
Disable time, random output from WE low
(see Note 8)
CL = 30 pF
tWEZ
0
15
0
20
ns
Access time, DQx from TRG low
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
NOTES: 7. Switching times for RAM-port output are measured with a load equivalent to 1 TTL load and 50 pF. Data out reference level:
VOH / VOL = 2 V/0.8 V. Switching times for SAM-port output are measured with a load equivalent to 1 TTL load and 30 pF. Serial-data
out reference level: VOH / VOL = 2 V/0.8 V.
8. tdis(CH), tdis(RH), tdis(G), tdis( WL ), and tdis(SE) are specified when the output is no longer driven.
36
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262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature†
ALT.
SYMBOL
tc(P)
(P)
Cycle time,
time page-mode
page mode read,
read write
tc(rd)
tc(rdW)
Cycle time, read
tc(RDWP)
tc(SC)
Cycle time, page-mode read-modify-write
tc(TRD)
tc(W)
Cycle time, transfer read
tw(CH)
Pulse duration, CASx high
’551x0
’551x1
Cycle time, read-modify-write
Cycle time, serial clock (see Note 9)
Cycle time, write
’551x0
tPC
tPC
35
tRC
tRMW
tPRMW
tSCC
MAX
UNIT
30
30
ns
110
130
ns
150
175
ns
80
90
ns
18
22
ns
tRC
tWC
tCPN
110
130
ns
110
130
ns
tCAS
tCAS
10
10 000
10
10 000
ns
17
10 000
20
10 000
ns
tTP
tRP
20
20
40
50
60
tw(GH)
tw(RH)
Pulse duration, TRG high
tw(RL)
tw(RL)P
Pulse duration, RAS low (see Note 11)
tRAS
Pulse duration, RAS low (page mode)
tw(SCH)
tw(SCL)
Pulse duration, SC high
tRASP
tSC
Pulse duration, SC low
tSCP
tw(TRG)
tw(WL)
Pulse duration, TRG low
tsu(CA)
tsu(DCL)
tsu(DQR)
’551xx - 70
MIN
ns
P l d
Pulse
duration,
ti
CAS
CASx low
l
(see
(
Note
N t 10)
Pulse duration, RAS high
MAX
40
tw(CL)
(CL)
’551x1
’551xx -60
MIN
10
10
10 000
60 100 000
5
70
ns
ns
ns
10 000
ns
70 100 000
ns
8
ns
5
8
ns
15
20
ns
10
10
ns
Setup time, column address before CASx low
tWP
tASC
0
0
ns
Setup time, data valid before CASx low, early write
tDSC
0
0
ns
tMS
0
0
ns
tDSW
tASR
0
0
ns
0
0
ns
tRCS
tFSC
0
0
ns
0
0
ns
tFSR
tTHS
0
0
ns
0
0
ns
tCWL
tWCS
tWSR
15
15
ns
0
0
ns
0
0
ns
tRWL
tRCH
15
15
ns
0
0
ns
Pulse duration, WE low
Setup time, write mask valid before RAS low,
non-persistent write-per-bit
tsu(DWL)
tsu(RA)
Setup time, data valid before WE low, late write
tsu(rd)
tsu(SFC)
Setup time, WE high before first CASx low, read
tsu(SFR)
tsu(TRG)
Setup time, DSF before RAS low
tsu(WCH)
tsu(WCL)
Setup time, WE low before both CASx high, write
tsu(WMR)
tsu(WRH)
Setup time, WE low before RAS low, write-per-bit
th(CHrd)
th(CLCA)
Hold time, WE high after both CASx high, read (see Note 12)
Setup time, row address before RAS low
Setup time, DSF before first CASx low
Setup time, TRG before RAS low
Setup time, WE low before first CASx low, early write
Setup time, WE low before RAS high, write
Hold time, column address after first CASx low
tCAH
10
10
ns
th(CLD)
Hold time, data valid after first CASx low, early write
tDH
15
15
ns
th(CLQ)
Hold time, DQ output after CASx low (TMS551x1)
tDHC
4
5
ns
† Timing measurements are referenced to VIL max and VIH min.
NOTES: 9. Cycle time assumes tt = 3 ns.
10. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the user’s transition times, this can require
additional CASx low time [tw(CL)].
11. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user’s transition times, this can require
additional RAS low time [tw(RL)].
12. Either th(RHrd) or th(CHrd) must be satisfied for a read cycle.
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)†
ALT.
SYMBOL
th(CLW)
th(RA)
Hold time, WE low after first CASx low, early write
th(RDQ)
th(RHrd)
Hold time, write mask valid after RAS low, non-persistent write-per-bit
th(RLCA)
th(RLD)
Hold time, column address valid after RAS low (see Note 13)
th(RLW)
th(RSF)
Hold time, WE low after RAS low, write
th(RWM)
th(SFC)
Hold time, WE low after RAS low, write-per-bit
th(SFR)
th(SHSQ)
Hold time, DSF after RAS low
th(TRG)
th(WLD)
Hold time, TRG after RAS low
th(WLG)
td(CACH)
Hold time, TRG high after WE low (see Note 14)
Hold time, row address after RAS low
Hold time, WE high after RAS high, read (see Note 12)
Hold time, data valid after RAS low (see Note 13)
Hold time, DSF after RAS low
Hold time, DSF after first CASx low
’551xx - 70
MIN
MIN
MAX
MAX
UNIT
tWCH
tRAH
10
15
ns
10
10
ns
tMH
10
10
ns
tRRH
tAR
0
0
ns
30
30
ns
tDHR
tWCR
35
35
ns
30
35
ns
tFHR
tRWH
30
35
ns
10
10
ns
tCFH
tRFH
10
10
ns
10
10
ns
tSOH
tTHH
4
5
ns
10
10
ns
tDH
15
15
ns
tOEH
tCAL
10
10
ns
Delay time, column address valid to CASx high
30
45
ns
td(CAGH)
Delay time, column address to TRG high in real-time-load and late-load
full-register transfer
tATH
20
20
ns
td(CARH)
Delay time, column address valid to RAS high
tRAL
30
35
ns
td(CASH)
Delay time, column address to first SC high after TRG high, early-load
full-register transfer
tASD
25
25
ns
td(CAWL)
Delay time, column address valid to WE low, read-modify-write
tAWD
50
60
ns
td(CHRL)
td(CLGH)
Delay time, both CASx high to RAS low
tCRP
0
0
ns
17
20
ns
td(CLQSF)
td(CLRH)
td(CLRL)
Hold time, SQ after SC high
’551xx -60
Hold time, data valid after WE low, late write
Delay time, CASx low to TRG high, read
Delay time, first CASx low to QSF switching, full-register transfer
(see Note 15)
Delay time, CASx low to RAS high
tCQD
30
30
ns
17
20
ns
Delay time, first CASx low to RAS low, CBR refresh
tRSH
tCSR
0
0
ns
td(CLSH)
Delay time, first CASx low to first SC high after TRG high, early-load
full-register transfer
tCSD
20
20
ns
td(CLTH)
Delay time, first CASx low to TRG high, real-time-load and late-load
full-register transfer
tCTH
15
15
ns
tCWD
tCLZ
37
45
ns
3
2
ns
tDZC
tDZO
0
0
ns
0
0
ns
td(CLWL)
td(CLZ)
Delay time, CASx low to WE low, read-modify-write (see Note 16)
td(DCL)
td(DGL)
Delay time, data to CASx low
Delay time, first CASx low to DQ in the low-impedance state
Delay time, data to TRG low
td(GHD)
Delay time, TRG high before data applied at DQ
tOED
10
15
ns
† Timing measurements are referenced to VIL max and VIH min.
NOTES: 12. Either th(RHrd) or th(CHrd) must be satisfied for a read cycle.
13. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
14. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle.
15. TRG must disable the output buffers prior to applying data to the DQ pins.
16. Switching times for QSF output are measured with a load equivalent to 1 TTL load and 30 pF, and output reference level is
VOH / VOL = 2 V/0.8 V.
38
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)†
ALT.
SYMBOL
’551xx -60
’551xx - 70
MIN
MIN
MAX
MAX
UNIT
td(GHQSF)
Delay time, TRG high to QSF switching, full-register transfer
(see Note 16)
tTQD
td(GLRH)
Delay time, TRG low to RAS high
tROH
10
15
ns
td(GLZ)
Delay time, TRG low to DQ in the low-impedance state
tOELZ
3
3
ns
td(MSRL)
Delay time, last SC high at boundary (127 or 255) to RAS low,
split-register transfer
15
20
ns
td(RHCL)
Delay time, RAS high to first CASx low, CBR refresh
0
0
ns
td(RHMS)
Delay time, RAS high to last SC high at boundary (127 or 255),
split-register-transfer
15
20
ns
td(RLCA)
Delay time, RAS low to column address valid
tRPC
’551x0
td(RLCH)
(
)
25
30
30
15
35
ns
tRAD
tCSH
15
60
70
ns
ns
53
60
ns
10
10
td(RLCL)
Delay time, RAS low to first CASx low (see Note 17)
tCSH
tCHR
tRCD
td(RLQSF)
Delay time, RAS low to QSF switching, full-register transfer
(see Note 16)
tRQD
td(RLSH)
Delay time, RAS low to first SC high after TRG high,
early-load full-register transfer
tRSD
65
70
ns
tRTH
tRWD
50
55
ns
Delay time, RAS low to WE low, read-modify-write
80
95
ns
Delay time, last SC high at boundary (127 or 255) to QSF switching,
split-register transfer (see Note 16)
tSQD
’551x1
Delay
y time, RAS low to CASx high
g
CBR
td(RLTH)
td(RLWL)
td(SCQSF)
Delay time, RAS low to TRG high (see Note 18)
td(SCTR)
td(THRH)
Delay time, SC high to TRG high, full-register transfer
td(THRL)
td(THSC)
Delay time, TRG high to RAS low (see Note 18)
Delay time, TRG high to RAS high (see Note 18)
Delay time, TRG high to SC high (see Note 18)
tTSL
tTRD
tTRP
tTSD
20
43
20
65
20
ns
50
ns
70
ns
25
ns
5
5
ns
– 10
– 10
ns
40
50
ns
20
25
ns
trf(MA)
Refresh time interval, memory
tREF
8
8
ms
tt
Transition time
tT
3
50
3
50
ns
† Timing measurements are referenced to VIL max and VIH min.
NOTES: 16. Switching times for QSF output are measured with a load equivalent to 1 TTL load and 30 pF, and output reference level is
VOH / VOL = 2 V/0.8 V.
17. The maximum value is specified only to assure RAS access time.
18. Real-time-load and late-load full-register transfer
POST OFFICE BOX 1443
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39
TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
PARAMETER MEASUREMENT INFORMATION
tc(rd)
tw(RL)
td(RLCH)
RAS
tw(RH)
tt
td(CLRH)
td(RLCL)
tw(CL)
td(CHRL)
CASx
tw(CH)
td(CACH)
td(RLCA)
td(CARH)
th(RA)
th(RLCA)
tsu(RA)
th(CLCA)
tsu(CA)
Row
A0 – A8
tsu(SFR)
Column
th(SFR)
DSF
td(CLGH)
tsu(TRG)
td(GLRH)
tw(TRG)
th(TRG)
TRG
th(RHrd)
tsu(rd)
th(CHrd)
WE
tdis(CH)†
ta(G)
td(DGL)
DQ0 – DQ15
tdis(G)
Data In
Data Out
td(GLZ)
td(CLZ)
ta(C)
ta(CA)
ta(R)
† For TMS551x0, CASx high disables the output regardless of the state of RAS. For TMS551x1, both RAS and CASx must be high to disable the
output.
Figure 31. Read-Cycle Timing With CASx-Controlled Output
40
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
PARAMETER MEASUREMENT INFORMATION
tc(rd)
tw(RL)
td(RLCH)
RAS
tw(RH)
tt
td(CLRH)
td(RLCL)
tw(CL)
td(CHRL)
CASx
tw(CH)
td(RLCA)
td(CARH)
th(RA)
th(RLCA)
td(CACH)
tsu(RA)
th(CLCA)
tsu(CA)
Row
A0 – A8
Column
th(SFR)
tsu(SFR)
DSF
td(CLGH)
td(GLRH)
tsu(TRG)
th(TRG)
tw(TRG)
TRG
tsu(rd)
th(RHrd)
th(CHrd)
WE
tdis(G)
td(DGL)
DQ0 – DQ15
ta(G)
Data In
tdis(RH)†
Data Out
td(GLZ)
td(CLZ)
ta(C)
ta(CA)
ta(R)
† For TMS551x0, RAS high does not disable the output. For TMS551x1, both RAS and CASx must be high to disable the output.
Figure 32. Read-Cycle Timing With RAS-Controlled Output
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41
TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
PARAMETER MEASUREMENT INFORMATION
tc(W)
tw(RL)
RAS
td(RLCH)
tt
tw(RH)
td(CLRH)
tt
td(CHRL)
td(RLCL)
td(CHRL)
tw(CL)
CASx
tw(CH)
th(RLCA)
th(RA)
td(CACH)
tsu(CA)
th(CLCA)
td(RLCA)
td(CARH)
tsu(RA)
Row
A0 – A8
Column
tsu(SFC)
tsu(SFR)
th(RSF)
th(SFR)
th(SFC)
DSF
th(TRG)
tsu(TRG)
TRG
tsu(WCH)
tsu(WMR)
tsu(WRH)
th(RLW)
th(CLW)
tsu(WCL)
tw(WL)
th(RWM)
1
WE
tsu(DQR)
th(CLD)†
tsu(DCL)†
th(RDQ)
DQ0 – DQ15
th(RLD)
2
3
† In early-write operations, DQ0 – DQ15 are all latched on the first falling edge of CASx. Thus, tsu(DCL) and th(CLD) are referenced only to the first
falling edge of CASx.
Figure 33. Early-Write-Cycle Timing
Table 7. Early-Write-Cycle State Table
STATE
CYCLE
1
2
3
Write operation (nonmasked)
H
Don’t care
Valid data
Write operation with nonpersistent write-per-bit
L
Write mask
Valid data
Write operation with persistent write-per-bit
L
Don’t care
Valid data
42
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
PARAMETER MEASUREMENT INFORMATION
tc(W)
tw(RL)
RAS
tw(RH)
td(RLCH)
tt
td(CLRH)
td(CHRL)
td(RLCL)
td(CHRL)
tt
tw(CL)
CASx
td(RLCA)
th(RLCA)
tw(CH)
tsu(CA)
th(CLCA)
td(CACH)
th(RA)
tsu(RA)
td(CARH)
Row
A0 – A8
Column
th(RSF)
tsu(SFC)
tsu(SFR)
th(SFR)
th(SFC)
DSF
tsu(rd)
TRG
tsu(WRH)
tsu(WCH)
tsu(TRG)
th(CLW)
td(GHD)
th(RLW)
tsu(WMR)
th(WLG)
th(RWM)
WE
tw(WL)
1
tsu(DWL)
tsu(DQR)
th(WLD)
th(RDQ)
th(RLD)
2
DQ0 – DQ15
3
Figure 34. Late-Write-Cycle Timing (Output-Enable-Controlled Write)
Table 8. Late-Write-Cycle State Table
STATE
CYCLE
1
2
3
Write operation (nonmasked)
H
Don’t care
Valid data
Write operation with nonpersistent write-per-bit
L
Write mask
Valid data
Write operation with persistent write-per-bit
L
Don’t care
Valid data
POST OFFICE BOX 1443
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43
TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
PARAMETER MEASUREMENT INFORMATION
tc(rdW)
tw(RL)
td(RLCH)
RAS
td(CHRL)
td(RLCL)
tsu(CA)
tsu(RA)
tw(CH)
th(CLCA)
th(RLCA)
td(CACH)
td(RLCA)
A0 – A8
td(CHRL)
tw(CL)
th(RA)
CASx
tw(RH)
td(CLRH)
td(CARH)
Row
Column
th(RSF)
tsu(SFR)
th(SFC)
tsu(SFC)
th(SFR)
DSF
tsu(WCH)
tsu(rd)
th(TRG)
tsu(WRH)
td(CAWL)
tw(TRG)
TRG
th(WLG)
th(RLW)
th(CLW)
tsu(TRG)
td(CLWL)
td(DCL)
tsu(WMR)
th(RWM)
WE
td(CLGH)
td(RLWL)
ta(R)
th(WLD)
td(DGL)
tsu(DQR)
th(RDQ)
DQ0 – DQ15
tw(WL)
ta(CA)
1
td(GHD)
ta(C)
tsu(DWL)
Valid
Out
2
ta(G)
3
tdis(G)
Figure 35. Read-Modify-Write-Cycle Timing
Table 9. Read-Modify-Write-Cycle State Table
STATE
CYCLE
1
2
3
Write operation (nonmasked)
H
Don’t care
Valid data
Write operation with nonpersistent write-per-bit
L
Write mask
Valid data
Write operation with persistent write-per-bit
L
Don’t care
Valid data
44
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
PARAMETER MEASUREMENT INFORMATION
tc(W)
tw(RL)
RAS
tw(RH)
td(RLCH)
td(RLCL)
tt
tt
td(CLRH)
td(CHRL)
td(CHRL)
tw(CL)
CASx
tw(CH)
th(CLCA)
th(RLCA)
td(RLCA)
tsu(RA)
td(CARH)
td(CACH)
th(RA)
tsu(CA)
Row
A0 – A8
th(RSF)
Block Address†
tsu(SFR)
tsu(SFC)
th(SFR)
th(SFC)
DSF
th(TRG)
tsu(TRG)
TRG
tsu(WCH)
th(RWM)
tsu(WRH)
tsu(WCL)
tsu(WMR)
th(CLW)
th(RLW)
tw(WL)
1
WE
th(RLD)
tsu(DCL)‡
tsu(DQR)
th(CLD)‡
th(RDQ)
DQ0 – DQ15
2
3
† For 4-column block write (TMS5516x), block address is A2 – A8; for 8-column block write (TMS5517x), block address is A3 – A8.
‡ In early-write operations, DQ0 – DQ15 are all latched on the first falling edge of CASx. Thus, tsu(DCL) and th(CLD) are referenced only to the first
falling edge of CASx.
Figure 36. Block-Write-Cycle Timing (Early Write)
Table 10. Block-Write-Cycle State Table
STATE
CYCLE
1
2
3
Block-write operation (nonmasked)
H
Don’t care
Column mask
Block-write operation with nonpersistent write-per-bit
L
Write mask
Column mask
Block-write operation with persistent write-per-bit
L
Don’t care
Column mask
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45
TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
PARAMETER MEASUREMENT INFORMATION
tc(W)
tw(RL)
RAS
tw(RH)
tt
td(RLCH)
tt
td(CLRH)
td(RLCL)
td(CHRL)
td(CHRL)
tw(CL)
CASx
tw(CH)
td(RLCA)
td(CACH)
th(RLCA)
td(CARH)
th(RA)
tsu(CA)
tsu(RA)
th(CLCA)
Row
A0 – A8
th(RSF)
tsu(SFR)
Block Address†
tsu(SFC)
th(SFR)
th(SFC)
DSF
tsu(TRG)
th(CLW)
tsu(WCH)
TRG
td(GHD)
th(RLW)
tsu(WRH)
tsu(WMR)
th(WLG)
th(RWM)
WE
tw(WL)
1
tsu(DQR)
tsu(DWL)‡
th(RDQ)
th(WLD)‡
th(RLD)
DQ0 – DQ15
3
2
† For 4-column block write (TMS5516x), block address is A2 – A8; for 8-column block write (TMS5517x), block address is A3 – A8.
‡ In late-write operations, DQ0 – DQ15 are all latched on the first falling edge of WE. Thus tsu(DWL) and th(WLD) are referenced only to the first falling
edge of WE.
Figure 37. Block-Write-Cycle Timing (Late Write)
Table 11. Block-Write-Cycle State Table
CYCLE
STATE
1
2
3
Block-write operation (nonmasked)
H
Don’t care
Column mask
Block-write operation with nonpersistent write-per-bit
L
Write mask
Column mask
Block-write operation with persistent write-per-bit
L
Don’t care
Column mask
46
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
PARAMETER MEASUREMENT INFORMATION
tc(W)
tw(RL)
RAS
tw(RH)
td(RLCH)
td(CLRH)
tt
tt
td(CHRL)
td(RLCL)
td(CHRL)
tw(CL)
CASx
tw(CH)
th(RA)
Refresh Row
tsu(RA)
A0 – A8
tsu(SFR)
th(RSF)
tsu(SFC)
th(SFC)
th(SFR)
DSF
th(TRG)
tsu(TRG)
TRG
tsu(WCH)
tsu(WMR)
tsu(WRH)
th(RLW)
th(CLW)
th(RWM)
WE
tsu(WCL)
tw(WL)
tsu(DCL)†
th(CLD)†
th(RLD)
DQ0 – DQ15
Write Mask
† In early-write operations, DQ0 – DQ15 are all latched on the first falling edge of CASx. Thus, tsu(DCL) and th(CLD) are referenced only to the first
falling edge of CASx.
Figure 38. Load-Write-Mask-Register-Cycle Timing (Early-Write Load)
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47
TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
PARAMETER MEASUREMENT INFORMATION
tc(W)
tw(RL)
RAS
tw(RH)
td(RLCH)
tt
td(CLRH)
td(CHRL)
td(RLCL)
td(CHRL)
tt
tw(CL)
CASx
tw(CH)
th(RA)
Refresh Row
tsu(RA)
A0 – A8
th(RSF)
tsu(SFR)
tsu(SFC)
th(SFR)
th(SFC)
DSF
tsu(WRH)
TRG
tsu(WCH)
tsu(TRG)
th(CLW)
td(GHD)
th(RLW)
tsu(WMR)
th(WLG)
th(RWM)
tw(WL)
WE
tsu(DWL)
th(WLD)
th(RLD)
Write Mask
DQ0 – DQ15
Figure 39. Load-Write-Mask-Register-Cycle Timing (Late-Write Load)
48
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
PARAMETER MEASUREMENT INFORMATION
tc(W)
tw(RL)
RAS
tw(RH)
tt
td(RLCH)
tt
td(CHRL)
td(CLRH)
td(RLCL)
tw(CL)
td(CHRL)
CASx
th(RA)
tw(CH)
tsu(RA)
Refresh Row
A0 – A8
th(SFC)
th(RSF)
tsu(SFR)
tsu(SFC)
th(SFR)
DSF
tsu(TRG)
th(TRG)
TRG
tsu(WCH)
tsu(WRH)
tsu(WMR)
th(RLW)
th(RWM)
th(CLW)
tsu(WCL)
WE
tw(WL)
tsu(DCL)†
th(CLD)†
th(RLD)
DQ0 –
DQ15
Valid Color Input
† In early-write operations, DQ0 – DQ15 are all latched on the first falling edge of CASx. Thus, tsu(DCL) and th(CLD) are referenced only to the first
falling edge of CASx.
Figure 40. Load-Color-Register-Cycle Timing (Early-Write Load)
POST OFFICE BOX 1443
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49
TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH1996
PARAMETER MEASUREMENT INFORMATION
tc(W)
tw(RL)
RAS
tw(RH)
tt
td(RLCH)
tt
td(CLRH)
td(RLCL)
td(CHRL)
td(CHRL)
tw(CL)
CASx
th(RSF)
th(RA)
tw(CH)
Refresh Row
tsu(RA)
A0 – A8
th(SFC)
tsu(SFR)
tsu(SFC)
th(SFR)
DSF
tsu(TRG)
th(CLW)
TRG
tsu(WRH)
tsu(WCH)
td(GHD)
th(RLW)
tsu(WMR)
th(WLG)
tw(WL)
WE
tsu(DWL)
th(WLD)
th(RLD)
DQ0 –
DQ15
Valid Color Input
Figure 41. Load-Color-Register-Cycle Timing (Late-Write Load)
50
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tw(RH)
tw(RL)P
RAS
td(RLCL)
td(CHRL)
CASx
td(CLRH)
tw(CH)
tw(CL)
tt
td(RLCA)
td(RLCH)
tsu(RA)
tsu(CA)
tc(P)
td(CACH)
th(CLCA)
th(RA)
td(CARH)
th(RLCA)
Row
A0 – A8
Column
Column
th(SFR)
td(CLGH)
tsu(SFR)
DSF
th(TRG)
tsu(TRG)
TRG
tsu(WMR)
th(RHrd)
tsu(rd)
WE
ta(C)
ta(CA)
td(DGL)
ta(CA)
ta(G)
ta(R)
DQ0 –
DQ15
ta(CP)
Data Out
Data In
tdis(G)
Data Out
tdis(CH)
td(DCL)
NOTE A: A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated and the proper state of DSF is latched on the falling edge of RAS and CASx to select the desired write
mode (normal, block write, etc.).
Figure 42. Enhanced-Page-Mode Read-Cycle Timing (TMS551x0)
POST OFFICE BOX 1443
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51
TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tw(RH)
tw(RL)P
RAS
td(RLCL)
td(CHRL)
CASx
td(CLRH)
tw(CH)
tw(CL)
tt
td(RLCA)
td(RLCH)
tsu(RA)
tsu(CA)
tc(P)
td(CACH)
th(CLCA)
th(RA)
td(CARH)
th(RLCA)
Row
A0 – A8
Column
Column
th(SFR)
td(CLGH)
tsu(SFR)
DSF
th(TRG)
tsu(TRG)
TRG
tsu(WMR)
th(RHrd)
tsu(rd)
WE
ta(C)
th(CLQ)
ta(CA)
td(DGL)
ta(R)
DQ0 –
DQ15
ta(CA)
ta(G)
ta(CP)
Data Out
Data In
tdis(WL)
tdis(RH)
tdis(G)
Data Out
td(DCL)
NOTE A: A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write- and read-modify-write timing
specifications are not violated and the proper state of DSF is latched on the falling edge of RAS and CASx to select the desired write
mode (normal, block write, etc.).
Figure 43. Extended-Data-Output Read-Cycle Timing (TMS551x1)
52
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tw(RL)P
RAS
td(RLCH)
tc(P)
td(RLCL)
tw(CH)
td(CHRL)
tsu(RA)
tw(CL)
td(CHRL)
td(RLCA)
tsu(CA)
CASx
tw(RH)
td(CLRH)
th(RA)
td(CACH)
th(CLCA)
td(CARH)
th(RLCA)
A0 –
A8
Row
Column
Column
tsu(SFR)
th(RSF)
th(SFC)
th(SFC)
th(SFR)
tsu(SFC)
tsu(SFC)
DSF
1
2
2
tsu(TRG)
th(TRG)
TRG
See Note A
tsu(WMR)
th(RWM)
WE
tsu(WCH)
tsu(WCH)
tsu(WRH)
tw(WL)
3
tsu(DWL)†
tsu(DQR)
th(CLD)†
tsu(DCL)†
th(WLD)†
th(RDQ)
th(RLD)
DQ0 –
DQ15
4
5
5
† DQ0 – DQ15 are latched on either the falling edge of WE or the first falling edge of CASx, whichever occurs later. In early-write operations, tsu(DWL)
and th(WLD) are not applicable; tsu(DCL) and th(CLD) are referenced only to the first falling edge of CASx. In late-write operations, tsu(DCL) and
th(CLD) are not applicable.
NOTE A: A read cycle or a read-modify-write cycle can be mixed with write cycles as long as read- and read-modify-write timing specifications
are not violated.
Figure 44. Enhanced-Page-Mode Write-Cycle Timing
Table 12. Enhanced-Page-Mode Write-Cycle State Table
STATE
CYCLE
1
2
3
4
5
Write operation (nonmasked)
L
L
H
Don’t care
Valid data
Write operation with nonpersistent write-per-bit
L
L
L
Write mask
Valid data
Write operation with persistent write-per-bit
L
L
L
Don’t care
Valid data
Load-write-mask register on either the first falling edge of
WE or the falling edge of CASx, whichever occurs later.
H
L
H
Don’t care
Write mask
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262144 BY 16-BIT MULTIPORT VIDEO RAMS
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PARAMETER MEASUREMENT INFORMATION
tw(RL)P
RAS
td(RLCH)
td(CHRL)
td(RLCL)
td(RLCA)
td(CARH)
tsu(CA)
th(CLCA)
tsu(RA)
td(CACH)
th(RLCA)
A0 – A8
Row
td(CHRL)
tw(CH)
tw(CL)
th(RA)
CASx
Column
Column
th(SFR)
tsu(SFR)
tsu(SFC)
th(SFC)
th(SFC)
tsu(SFC)
DSF
tw(RH)
td(CLRH)
tc(RDWP)
1
2
2
tsu(rd)
tsu(WCH)
tsu(WCH)
td(DCL)
td(CLWL)
td(CAWL)
td(RLWL)
th(TRG)
td(CLGH)
td(CLGH)
tsu(TRG)
tsu(WRH)
tw(TRG)
TRG
tw(TRG)
tsu(WMR)
th(RWM)
tw(WL)
3
WE
ta(C)
ta(CA)
tsu(DWL)
th(WLD)
tsu(DQR)
th(WLD)
td(DCL)
DQ0 – DQ15
td(GHD)
tsu(DWL)
th(RDQ)
4
ta(CP)
Valid Out
5
ta(G)
td(DGL)
5
td(DGL)
Valid Out
tdis(G)
td(GHD)
ta(R)
ta(C)
NOTE A: A read cycle or a write cycle can be mixed with read-modify-write cycles as long as the read and write timing specifications are not
violated.
Figure 45. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing
Table 13. Enhanced Page-Mode Read-Modify-Write-Cycle State Table
STATE
CYCLE
1
2
3
Write operation (nonmasked)
L
L
Write operation with nonpersistent write-per-bit
L
L
Write operation with persistent write-per-bit
L
Load-write-mask register on either the first falling edge of
WE or the falling edge of CASx, whichever occurs later.
H
54
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4
5
H
Don’t care
Valid data
L
Write mask
Valid data
L
L
Don’t care
Valid data
L
H
Don’t care
Write mask
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tw(RH)
tw(RL)P
RAS
td(RLCL)
td(CHRL)
CASx
td(CLRH)
tw(CH)
tw(CL)
tt
td(RLCA)
td(RLCH)
tsu(RA)
tc(P)
tsu(CA)
td(CACH)
th(CLCA)
th(RA)
td(CARH)
th(RLCA)
Row
A0 – A8
Column
Column
th(SFR)
td(CLGH)
tsu(SFR)
DSF
tsu(WCL)
th(TRG)
tsu(TRG)
th(CLW)
TRG
tsu(WMR)
tsu(rd)
WE
tw(WL)
ta(C)
ta(CA)
td(DGL)
ta(R)
DQ0 –
DQ15
th(CLD)
ta(G)
tsu(DCL)
tdis(WL)
Data In
Data Out
Data In
td(DCL)
Figure 46. Extended-Data-Output Read-Followed-by-Write-Cycle Timing (TMS551x1)
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SMVS464 – MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tw(RL)P
RAS
td(RLCH)
td(RLCL)
td(CLRH)
tw(CH)
tw(CL)
td(CHRL)
CASx
td(RLCA)
td(CHRL)
th(CLCA)
tsu(CA)
td(CACH)
th(RA)
th(RLCA)
tsu(RA)
Row
A0 – A8
tw(RH)
tc(P)
th(SFR)
tsu(SFR)
td(CARH)
Block Address†
Block Address†
th(SFC)
tsu(SFC)
th(SFC)
tsu(SFC)
DSF
th(TRG)
tsu(TRG)
TRG
See Note A
tsu(WMR)
tw(WL)
th(RWM)
WE
tsu(WCH)
tsu(WCH)
tsu(WRH)
1
tsu(DWL)‡
tsu(DQR)
th(CLD)‡
th(WLD)‡
tsu(DCL)‡
th(RDQ)
th(RLD)
DQ0 –
DQ15
2
3
3
† For 4-column block write (TMS5516x), block address is A2 – A8; for 8-column block write (TMS5517x), block address is A3 – A8.
‡ DQ0 – DQ15 are latched on either the falling edge of WE or the first falling edge of CASx, whichever occurs later. In early-write operations, tsu(DWL)
and th(WLD) are not applicable; tsu(DCL) and th(CLD) are referenced only to the first falling edge of CASx. In late-write operations, tsu(DCL) and
th(CLD) are not applicable.
NOTE A: A read cycle or a read-modify-write cycle can be mixed with write cycles as long as read- and read-modify-write timing specifications
are not violated.
Figure 47. Enhanced-Page-Mode Block-Write-Cycle Timing
Table 14. Enhanced-Page-Mode Block-Write-Cycle State Table
CYCLE
STATE
1
2
3
Block-write operation (nonmasked)
H
Don’t care
Column mask
Block-write operation with nonpersistent write-per-bit
L
Write mask
Column mask
Block-write operation with persistent write-per-bit
L
Don’t care
Column mask
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PARAMETER MEASUREMENT INFORMATION
tc(rd)
tw(RL)
RAS
tw(RH)
tt
td(RHCL)
td(CHRL)
td(CHRL)
CASx
th(RA)
tsu(RA)
Row
A0 – A8
DSF
th(TRG)
tsu(TRG)
TRG
WE
DQ0 –
DQ15
Hi-Z
Figure 48. RAS-Only Refresh-Cycle Timing
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tc(rd)
tw(RH)
tw(RL)
RAS
td(RHCL)
tt
td(CLRL)
td(RLCH)
CASx
td(CHRL)
tsu(RA)
th(RA)
1
A0 – A8
tsu(SFR)
th(SFR)
2
DSF
TRG
tsu(WMR)
th(RWM)
3
WE
Hi-Z
DQ0 – DQ15
Figure 49. CBR-Refresh-Cycle TIming
Table 15. CBR-Cycle State Table
STATE
CYCLE
1
2
3
CBR refresh with option reset
Don’t care
L
H
CBR refresh with no reset (CBRN)
Don’t care
H
H
Stop address
H
L
CBR refresh with stop point set and no reset (CBRS)
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SMVS464 – MARCH 1996
PARAMETER MEASUREMENT INFORMATION
Memory Read Cycle
Refresh Cycle
tc(rd)
tc(rd)
tc(rd)
tw(RH)
tw(RH)
tw(RL)
Refresh Cycle
tw(RL)
RAS
td(CARH)
td(CHRL)
td(RLCH)
tt
tw(CL)
CASx
td(RLCA)
tsu(RA)
tsu(RA)
th(CLCA)
tsu(CA)
th(RA)
tsu(RA)
tsu(RA)
A0 – A8
Row
th(RA)
th(RA)
th(RA)
1
Col
1
1
tsu(SFR)
th(SFR)
tsu(SFR)
th(SFR)
th(SFR)
2
2
DSF
tsu(SFR)
2
th(RHrd)
tdis(CH)
tsu(TRG)
th(TRG)
tdis(G)
td(GLRH)
TRG
tsu(WMR)
th(RWM)
tsu(WMR)
th(RWM)
tsu(rd)
ta(G)
WE
3
tsu(WMR)
th(RWM)
3
3
ta(C)
ta(R)
DQ0 –
DQ15
Data Out
Figure 50. Hidden-Refresh-Cycle Timing
Table 16. Hidden-Refresh-Cycle State Table
STATE
CYCLE
CBR refresh with option reset
CBR refresh with no reset (CBRN)
CBR refresh with stop point set and no option reset (CBRS)
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1
2
3
Don’t care
L
H
Don’t care
H
H
Stop address
H
L
• HOUSTON, TEXAS 77251–1443
59
TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tc(TRD)
tw(RL)
td(RLCL)
RAS
tw(RH)
td(RLCH)
td(CHRL)
td(CARH)
tw(CL)
td(RLCA)
CASx
th(RA)
tsu(RA)
tsu(CA)
th(CLCA)
th(RLCA)
Tap Point
A0 – A8
Row
A0 – A8
tsu(SFR)
See Note C
th(SFR)
DSF
tsu(TRG)
th(TRG)
TRG
tw(GH)
th(RWM)
tsu(WMR)
td(CASH)
WE
DQ0 –
DQ15
See Note A
Hi-Z
td(CLSH)
td(SCTR)
tw(SCH)
tw(SCL)
td(RLSH)
SC
tw(SCH)
tc(SC)
ta(SQ)
th(SHSQ)
th(SHSQ)
Old Data
SQ
ta(SQ)
Old Data
New Data
td(GHQSF)
Tap Point Bit A7
QSF
td(CLQSF)
H
td(RLQSF)
SE
L
NOTES: A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register-transfer cycle. The
memory-to-data-register-transfer cycle is used to load the data registers in parallel from the memory array. The 256 locations in each
data register are written into from the 256 corresponding columns of the selected row.
B. Once data is transferred into the data registers, SAM is in the serial-read mode (that is, SQx is enabled), allowing data to be shifted
out of the registers. Also, the first bit to read from the data register after TRG has gone high must be activated by a positive transition
of SC.
C. A0 – A7: register tap point; A8: identifies the DRAM half of the row
D. Early-load operation is defined as th(TRG) min < th(TRG) < td(RLTH) min.
Figure 51. Full-Register-Transfer Read Timing, Early-Load Operations
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SMVS464 – MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tc(TRD)
tw(RL)
RAS
td(RLCL)
tw(RH)
td(RLCH)
td(CHRL)
CASx
tw(CL)
td(RLCA)
th(RA)
tsu(RA)
tsu(CA)
th(RLCA)
th(CLCA)
Tap Point
A0 – A8
Row
A0 – A8
tsu(SFR)
See Note C
th(SFR)
DSF
td(CLTH)
tsu(TRG)
td(THRL)
td(THRH)
td(CAGH)
td(RLTH)
TRG
See Note D
tw(GH)
th(RWM)
tsu(WMR)
WE
td(SCTR)
td(THSC)
See Note A
DQ0 –
DQ15
Hi-Z
See Note B
tw(SCH)
SC
ta(SQ)
ta(SQ)
th(SHSQ)
Old Data
SQ
tw(SCL)
Old Data
tc(SC)
th(SHSQ)
Old Data
New Data
td(GHQSF)
QSF
Tap Point Bit A7
td(CLQSF)
H
SE
td(RLQSF)
L
NOTES: A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register-transfer cycle. The memory to data
register-transfer cycle is used to load the data registers in parallel from the memory array. The 256 locations in each data register
are written into from the 256 corresponding columns of the selected row.
B. Once data is transferred into the data registers, SAM is in the serial-read mode (i.e., SQ is enabled), allowing data to be shifted out
of the registers. Also, the first bit to read from the data register after TRG has gone high must be activated by a positive transition
of SC.
C. A0 – A7: register tap point; A8: identifies the DRAM half of the row
D. Late-load operation is defined as td(THRH) < 0 ns.
Figure 52. Full-Register-Transfer Read Timing, Real-Time Load Operation/Late-Load Operation
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TMS55160, TMS55161, TMS55170, TMS55171
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SMVS464 – MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tc(TRD)
tw(RH)
tw(RL)
td(RLCL)
RAS
td(CHRL)
td(RLCH)
tw(CH)
td(RLCA)
CASx
tw(CL)
tsu(CA)
th(RA)
th(CLCA)
tsu(RA)
A0 – A8
Tap Point A0 – A8
Row
tsu(TRG)
See Note A
th(TRG)
TRG
th(SFR)
tsu(SFR)
DSF
th(RWM)
tsu(WMR)
WE
DQ0 –
DQ15
Hi-Z
td(MSRL)
td(RHMS)
tc(SC)
tc(SC)
tw(SCH)
SC
Bit 127
or 255
tw(SCL)
ta(SQ)
ta(SQ)
th(SHSQ)
SQ
Bit 126 or
Bit 254
Bit 255
or 127
Tap
Point M
Bit 127 or
Bit 255
Tap
Point N
ta(SQ)
Tap Point M
tw(SCL)
Bit 127 or
Bit 255
Tap
Point N
ta(SQ)
td(SCQSF)
td(SCQSF)
QSF
MSB Old
SE
VIL
NOTE A: A0 – A6: tap point of the given half; A7: don’t care; A8: identifies the DRAM half of the row
Figure 53. Split-Register-Transfer Read Timing
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH 1996
PARAMETER MEASUREMENT INFORMATION
RAS
tsu(TRG)
th(TRG)
TRG
tc(SC)
tw(SCH)
tc(SC)
tw(SCH)
tw(SCH)
tw(SCL)
tw(SCL)
SC
ta(SQ)
ta(SQ)
th(SHSQ)
SQ
ta(SQ)
th(SHSQ)
Valid Out
th(SHSQ)
Valid Out
Valid Out
ta(SE)
SE
NOTE A: While reading data through the serial-data register, TRG is a don’t care, except TRG must be held high when RAS goes low. This is
to avoid the initiation of a register-data transfer operation.
Figure 54. Serial-Read Timing (SE = VIL )
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464 – MARCH 1996
PARAMETER MEASUREMENT INFORMATION
RAS
tsu(TRG)
th(TRG)
TRG
tc(SC)
tc(SC)
tw(SCH)
tw(SCH)
tw(SCL)
tw(SCL)
SC
tw(SCH)
ta(SQ)
ta(SQ)
ta(SQ)
th(SHSQ)
ta(SE)
SQ
Valid Out
Valid Out
th(SHSQ)
Valid Out
Valid Out
tdis(SE)
SE
NOTE A: While reading data through the serial-data register, TRG is a don’t care except TRG must be held high when RAS goes low. This is
to avoid the initiation of a register-data transfer operation.
Figure 55. Serial-Read Timing (SE-Controlled Read)
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PARAMETER MEASUREMENT INFORMATION
RAS
CASx
ADDR
Row Tap1
(low)
Row Tap1
(high)
Row Tap2
(low)
Row Tap2
(high)
TRG
DSF
CASE I
SC
Tap1
(low)
Bit Tap1
127 (high)
Bit
255
Tap2
(low)
Bit
127
Bit Tap1
127 (high)
Bit
255
Tap2
(low)
Bit
127
Bit Tap1
127 (high)
Bit
255
Tap2
(low)
Bit
127
QSF
CASE II
SC
Tap1
(low)
QSF
CASE III
SC
Tap1
(low)
QSF
Full-Register-Transfer Read
Split Register to the
High Half of the
Data Register
Split Register to the
Low Half of the
Data Register
Split Register to the
High Half of the
Data Register
NOTES: A. In order to achieve proper split-register operation, a full-register-transfer read should be performed before the first
split-register-transfer cycle. This is necessary to initialize the data register and the starting tap location. First serial access can then
begin either after the full-register-transfer read cycle (CASE I), during the first split-register-transfer cycle (CASE II), or even after
the first split-register-transfer cycle (CASE III). There is no minimum requirement of SC clock between the full-register-transfer read
cycle and the first split-register cycle.
B. A split-register-transfer into the inactive half is not allowed until td(MSRL) is met. td(MSRL) is the minimum delay time between the rising
edge of the serial clock of the last bit (bit 127 or 255) and the falling edge of RAS of the split-register-transfer cycle into the inactive
half. After the td(MSRL) is met, the split-register-transfer into the inactive half must also satisfy the minimum td(RHMS) requirement.
td(RHMS) is the minimum delay time between the rising edge of RAS of the split-register-transfer cycle into the inactive half and the
rising edge of the serial clock of the last bit (bit 127 or 255).
Figure 56. Split-Register Operating Sequence
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SMVS464 – MARCH 1996
MECHANICAL DATA
DGH (R-PDSO-G64)
PLASTIC SMALL-OUTLINE PACKAGE
0,45
0,25
0,80
64
0,12 M
33
12,12
11,96
14,50
14,00
0,15 NOM
Gage Plane
1
0,25
32
0°– 5°
0,70
0,40
26,42
26,17
Seating Plane
2,38 MAX
0,00 MIN
0,10
4040068 / B 10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Plastic body dimensions do not include mold flash or protrusion. Maximum mold protrusion is 0,125.
device symbolization
TI
-SS
Speed Code (- 60, -70)
TMS551xx
DGH
Package Code
W
B
Y
M
LLLL
P
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
66
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