SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS034C – MAY 1989 – REVISED JUNE 1995 D D D D D D D D D D Organization . . . 262 144 Words × 4 Bits Single 5-V Supply (10% Tolerance) Processed to MIL-STD-833, Class B Performance Ranges: SMJ44C256-80 SMJ44C256-10 SMJ44C256-12 SMJ44C256-15 ACCESS ACCESS ACCESS READ TIME TIME TIME OR ta(R) ta(C) ta(CA) WRITE (tRAC) (tCAC) (tCAA) CYCLE (MAX) (MAX) (MAX) (MIN) 80 ns 20 ns 40 ns 150 ns 100 ns 25 ns 45 ns 190 ns 120 ns 30 ns 55 ns 220 ns 150 ns 40 ns 70 ns 260 ns Enhanced Page-Mode Operation With CAS-Before-RAS (CBR) Refresh Long Refresh Period 512-Cycle Refresh in 8 ms (Max) All Inputs and Clocks are TTL Compatible JD PACKAGE ( TOP VIEW ) DQ1 DQ2 W RAS TF A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Low Power Dissipation Packaging Offered: – 20-Pin 300-Mil Ceramic DIP (JD Suffix) – 20-Lead Ceramic Surface-Mount Package (HJ Suffix) – 20-Pin Ceramic Flat Pack (HK Suffix) – 20-Terminal Leadless Ceramic Surface-Mount Package (FQ Suffix) – 20-Terminal Low-Profile Leadless Ceramic Surface-Mount Package (HL Suffix) – 20-Pin Ceramic Zig Zag In-Line Package (SV Suffix) Operating Free-Air Temperature Range – 55°C to 125°C HJ PACKAGE ( TOP VIEW ) DQ1 DQ2 W RAS TF VSS DQ4 DQ3 CAS G A8 A7 A6 A5 A4 A0 A1 A2 A3 VCC PIN NOMENCLATURE 1 2 3 4 5 26 25 24 23 22 VSS DQ4 DQ3 CAS G 9 10 11 12 13 18 17 16 15 14 A8 A7 A6 A5 A4 HK PACKAGE ( TOP VIEW ) DQ1 DQ2 W RAS TF A0 A1 A2 A3 VCC D 3-State Unlatched Output 1 2 3 4 5 6 7 8 9 10 VSS DQ4 DQ3 CAS G A8 A7 A6 A5 A4 20 19 18 17 16 15 14 13 12 11 A0 – A8 CAS DQ1 – DQ4 G RAS TF VCC VSS W Address Inputs Column Address Strobe Data In / Data Out Data Output Enable Row Address Strobe Test Function 5-V Supply Ground Write Enable FQ / HL PACKAGES ( TOP VIEW ) DQ1 DQ2 W RAS TF A0 A1 A2 A3 VCC 1 2 3 4 5 26 25 24 23 22 VSS DQ4 DQ3 CAS G 9 10 11 12 13 18 17 16 15 14 A8 A7 A6 A5 A4 SV PACKAGE ( TOP VIEW ) G DQ3 VSS DQ2 RAS A0 A2 VCC A5 A7 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 CAS DQ4 DQ1 W TF A1 A3 A4 A6 A8 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS034C – MAY 1989 – REVISED JUNE 1995 description The SMJ44C256 series is a set of high-speed, 1 048 576-bit dynamic random access memories (DRAMs), organized as 262 144 words of four bits each. These devices employ technology for high performance, reliability, and low power. These devices feature maximum RAS access times of 80 ns, 100 ns,120 ns, and 150 ns. Maximum power dissipation is as low as 305 mW operating and 16.5 mW standby on 150-ns devices. ICC peaks are 140 mA typical, and an input voltage undershoot of –1 V can be tolerated, minimizing system noise considerations. All inputs and outputs, including clocks, are compatible with Series 54 /174 TTL. All addresses and data-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility. The SMJ44C256 is offered in 20-pin ceramic dual-in-line packages (JD suffix) and 20/26-terminal ceramic leadless carriers (FQ / HL suffixes), 20/26-pin leaded carrier (HJ suffix), a 20-pin flatpack (HK suffix), and a 20-pin ceramic zig-zag in-line package (SV suffix). They are specified for operation from –55°C to125°C. logic symbol† A0 A1 A2 A3 A4 A5 A6 A7 A8 RAS 6 7 RAM 256K × 4 20D9/21D0 8 9 11 A 12 0 262 143 13 14 15 4 20D17/21D8 C20[ROW] G23/[REFRESH ROW] 24[PWR DWN] C21/[COLUMN] G24 CAS W G DQ1 DQ2 DQ3 DQ4 17 3 16 1 & 23,21D 23C22 24,25EN G25 A,22D ∇ 26 A,Z26 2 18 19 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the JD package. 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS034C – MAY 1989 – REVISED JUNE 1995 functional block diagram RAS CAS W G Timing and Control Row Address Buffers (9) 256K Array A0 A1 A2 A3 A4 A5 A6 A7 A8 Row Decode 256K Array Sense Amplifiers Column Address Buffers (9) Column Decode I/O Buffers 4 of 8 Selection Data In Reg 4 Data Out Reg 4 4 Sense Amplifiers 256K Array Row Decode 256K Array DQ1–DQ4 operation enhanced page mode Page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum number of columns that can be accessed is determined by the maximum RAS low time and the CAS page cycle time used. With minimum CAS page cycle time, all 512 columns specified by column addresses A0 through A8 can be accessed without intervening RAS cycles. Unlike conventional page mode DRAMs, the column-address buffers in this device are activated on the falling edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The column address latches to the first CAS falling edge. This feature allows the SMJ44C256 to operate at a wider data bandwidth than conventional page mode parts, since data retrieval begins as soon as column address is valid rather than when CAS goes low. This performance improvement is referred to as enhanced page mode. Valid column address can be presented immediately after th(RA) (row address hold time) has been satisfied, usually well in advance of the falling edge of CAS. In this case, data is obtained after ta(C) maximum (access time from CAS low), if ta(CA) maximum (access time from column address) has been satisfied. In the event that column addresses for the next page cycle are valid at the time CAS goes high, access time for the next cycle is determined by the later occurrence of ta(C) or ta(CP) (access time from rising edge of CAS). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS034C – MAY 1989 – REVISED JUNE 1995 address (A0 through A8) Eighteen address bits are required to decode 1 of 262 144 storage cell locations. Nine row-address bits are set up on pins A0 through A8 and latched onto the chip by RAS. Nine column-address bits are set up on pins A0 through A8 and latched onto the chip by CAS. All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. In the SMJ44C256, CAS is used as a chip select, activating the output buffer as well as latching the address bits into the column-address buffers. write enable (W) The read or write mode is selected through W. A logic high on the W input selects the read mode and a logic low selects the write mode. The write-enable terminal can be driven from the standard TTL circuits without a pullup resistor. The data input is disabled when the read mode is selected. When W goes low prior to CAS (early-write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with G grounded. data in (DQ1–DQ4) Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge of CAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS and the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-modify-write cycle, CAS is already low, the data is strobed in by W with setup and hold times referenced to this signal. In a delayed-write or read-modify-write cycle, G must be high to bring the output buffers to the high-impedance state prior to applying data to the I/O lines. data out (DQ1–DQ4) The 3-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two Series 54 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS and G are brought low. In a read cycle the output becomes valid after the access time interval ta(C) that begins with the negative transition of CAS as long as ta(R) and ta(CA) are satisfied. The output becomes valid after the access time has elapsed and remains valid while CAS and G are low. CAS or G going high returns it to a high-impedance state. This is accomplished by bringing G high prior to applying data, thus satisfying td(GHD). output enable (G) G controls the impedance of the output buffers. When G is high, the buffers remain in the high-impedance state. Bringing G low during a normal cycle activates the output buffers, putting them in the low-impedance state. It is necessary for both G and CAS to be brought low for the output buffers, to go into the low-impedance state. Once in the low-impedance state, they remain in the low-impedance state until either G or CAS is brought high. refresh A refresh operation must be performed at least once every 8 ms to retain data. This can be achieved by strobing each of the 512 rows (A0 – A8). A normal read or write cycle refreshes all bits in each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output buffer remains in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh. Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh cycle. CBR refresh CBR refresh is utilized by bringing CAS low earlier than RAS [see parameter td(CLRL)R] and holding it low after RAS falls [see parameter td(RLCH)R]. For successive CBR refresh cycles, CAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated internally. The external address is also ignored during the hidden refresh option. 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS034C – MAY 1989 – REVISED JUNE 1995 power up To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization (refresh) cycles is required after power-up to the full VCC level. test function pin During normal device operation the TF pin must either be disconnected or biased at a voltage less than or equal to VCC. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX 4.5 5 5.5 UNIT VCC VSS Supply voltage VIH VIL High-level input voltage 2.4 6.5 V Low-level input voltage (see Note 2) –1 0.8 V TA Operating free-air temperature Supply voltage 0 – 55 V V °C TC Case temperature 125 °C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS034C – MAY 1989 – REVISED JUNE 1995 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage IOH = – 5 mA VOL Low-level output voltage IOL = 4.2 mA II Input current (leakage) IO ’44C256-80 ’44C256-10 ’44C256-12 ’44C256-15 MIN MIN MIN MIN MAX 2.4 MAX 2.4 MAX 2.4 MAX 2.4 UNIT V 0.4 0.4 0.4 0.4 V VCC = 5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC ± 10 ± 10 ± 10 ± 10 µA Output current (leakage) VCC = 5.5 V, CAS high ± 10 ± 10 ± 10 ± 10 µA ICC1 Read- or write-cycle current VCC = 5.5 V, tc(rdW) = minimum 80 70 60 55 mA ICC2 Standby current 3 3 3 3 mA ICC3 Average refresh current (RAS only, or CBR) 75 65 55 50 mA ICC4 Average page current 50 45 35 30 mA VO = 0 to VCC, After 1 memory cycle, RAS and CAS high, VIH = 2.4 V VCC = 5.5 V, tc(rdW) = minimum, RAS cycling, CAS high (RAS only), RAS low after CAS low (CBR) VCC = 5.5 V, RAS low, tc(P) = minimum, CAS cycling capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 3) HL / JD / FQ PARAMETER MIN HJ MAX MIN HK MAX MIN SV MAX MIN MAX UNIT Ci(A) Input capacitance, address inputs 6 7 8 9 pF Ci(RC) Input capacitance, strobe inputs 7 7 8 8 pF Ci(W) Input capacitance, write-enable input 7 7 7 7 pF CO Output capacitance 7 9 10 8 pF NOTE 3: Capacitance is sampled only at initial design and after any major change. Samples are tested at 0 V and 25°C with a 1-MHz signal applied to the pin under test. All other pins are open. 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS034C – MAY 1989 – REVISED JUNE 1995 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figure 1) ALT. SYMBOL PARAMETER ta(C) ta(CA) Access time from CAS low ta(RL) ta(G) Access time from RAS low ’44C256-80 ’44C256-10 ’44C256-12 ’44C256-15 MIN MIN MIN MIN MAX MAX MAX MAX UNIT tCAC tAA 20 25 30 40 ns 40 45 55 70 ns 80 100 120 150 ns Access time from G low tRAC tGAC 20 25 30 40 ns ta(CP) Access time from CAS high column precharge tCPA 40 50 60 75 ns tdis(CH) Output disable time after CAS high (see Note 4) tOFF 20 25 30 35 ns tdis(G) Output disable time after G high (see Note 4) tGOFF 20 25 30 35 ns Access time from column-address NOTE 4: tdis(CH) and tdis(G) are specified when the output is no longer driven. The outputs are disabled by bringing either G or CAS high. timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 5) PARAMETER tc(rd) tc(W) Cycle time, read (see Note 6) ALT. SYMBOL ’44C256-80 MIN MAX ’44C256-10 MIN MAX ’44C256-12 MIN MAX ’44C256-15 MIN MAX UNIT tRC tWC 150 190 220 260 ns 150 190 220 260 ns tc(rdW) Cycle time,read-write / readmodify-write tRWC 225 270 305 355 ns tc(P) Cycle time, page-mode read or write (see Note 7) tPC 50 55 65 80 ns tc(PM) Cycle time, page-mode readmodify-write tPRWC 115 135 150 175 ns tw(CH) Pulse duration, CAS high tCP 10 10 15 25 ns tw(CL) Pulse duration, CAS low (see Note 8) tCAS 20 tw(RH) Pulse duration, RAS high (precharge) tRP 60 tw(RL) Pulse duration, nonpage mode RAS low (see Note 9) tRAS 80 10 000 100 10 000 120 10 000 150 10 000 ns tw(RL)P Pulse duration, page mode RAS low (see Note 9) tRASP 80 100 000 100 100 000 120 100 000 150 100 000 ns tw(WL) Pulse duration, write low tWP 15 15 20 25 ns tsu(CA) Setup time, column address before CAS low tASC 5 5 5 5 ns Cycle time, write 10 000 25 10 000 80 30 10 000 90 40 10 000 100 ns ns NOTES: 5. 6. 7. 8. Timing measurements in this table are referenced to VIL max and VIH min. All cycle times assume tt = 5 ns. To assure tc(P) min, tsu(CA) should be ≥ tw(CH). In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the user’s transition times, this can require additional CAS low time [tw(CL)]. 9. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user’s transition times, this can require additional RAS low time [tw(RL)]. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS034C – MAY 1989 – REVISED JUNE 1995 timing requirements over recommended ranges of supply voltage and operating temperature (continued) (see Note 5) ’44C256-80 ’44C256-10 ’44C256-12 ’44C256-15 MIN MIN MIN MIN PARAMETER ALT. SYMBOL tsu(RA) Setup time, row address before RAS low tASR 0 0 0 0 ns tsu(D) Setup time, data before W low (see Note 10) tDS 0 0 0 0 ns tsu(rd) Setup time, W high before CAS low tRCS 0 0 0 0 ns tsu(WCL) Setup time, W low before CAS low (see Note 11) tWCS 0 0 0 0 ns tCWL tRWL 20 25 30 40 ns Setup time, W low before RAS high 20 25 30 40 ns th(CA) Hold time, column address after CAS low (see Note 10) tCAH 15 20 20 25 ns th(RA) Hold time, row address after RAS low tRAH 15 15 15 15 ns th(RLCA) Hold time, column address after RAS low (see Note 12) tAR 60 70 80 100 ns th(D) Hold time, data after CAS low (see Note 10) tDH 15 20 25 30 ns th(RLD) Hold time, data after RAS low (see Note 12) tDHR 60 70 85 110 ns th(WLGL) Hold time, G high after W low tGH 20 25 30 40 ns th(CHrd) Hold time, W high after CAS high (see Note 13) tRCH 0 0 0 0 ns th(RHrd) Hold time, W high after RAS high (see Note 13) tRRH 10 10 10 10 ns th(CLW) Hold time, W low after CAS low (see Note 11) tWCH 15 20 25 30 ns th(RLW) Hold time, W low after RAS low (see Note 12) tWCR 65 75 90 105 ns 80 100 120 150 ns tsu(WCH) tsu(WRH) Setup time, W low before CAS high MAX MAX MAX MAX UNIT td(RLCH) td(CHRL) Delay time, RAS low to CAS high Delay time, CAS high to RAS low tCSH tCRP 0 0 0 0 ns td(CLRH) Delay time, CAS low to RAS high tRSH 20 25 30 40 ns td(CLWL) Delay time, CAS low to W low (see Note 14) tCWD 60 70 80 90 ns td(RLCL) Delay time, RAS low to CAS low (see Note 15) tRCD 30 60 30 75 30 90 30 110 ns td(RLCA) Delay time, RAS low to column address (see Note 15) tRAD 20 40 20 55 20 65 25 80 ns NOTES: 5. 10. 11. 12. 13. 14. 15. 8 Timing measurements in this table are referenced to VIL max and VIH min. Referenced to the later of CAS or W in write operations. Early-write operation only The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference. Either th(RHrd) or th(CHrd) must be satisfied for a read cycle. Read-modify-write operation only Maximum value specified only to assure access time. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS034C – MAY 1989 – REVISED JUNE 1995 timing requirements over recommended ranges of supply voltage and operating temperature (continued) (see Note 5) ALT. SYMBOL PARAMETER ’44C256-80 MIN ’44C256-10 MAX MIN ’44C256-12 MAX MIN ’44C256-15 MAX MIN MAX UNIT td(CARH) Delay time, column address to RAS high tRAL 40 45 55 70 ns td(CACH) Delay time, column address to CAS high tCAL 40 45 55 70 ns td(RLWL) Delay time, RAS low to W low (see Note 14) tRWD 130 150 170 200 ns td(CAWL) Delay time, column address to W low (see Note 14) tAWD 80 95 105 120 ns td(GHD) Delay time, G high before data at DQ tGDD 20 25 30 40 ns td(GLRH) Delay time, G low to RAS high tGSR 20 25 30 40 ns td(RLCH)R Delay time, RAS low to CAS high (see Note 16) tCHR 20 25 25 30 ns td(CLRL)R Delay time, CAS low to RAS low (see Note 16) tCSR 10 10 10 15 ns td(RHCL)R Delay time, RAS high to CAS low (see Note 16) tRPC 0 0 0 0 ns trf tt Refresh time interval tREF tT Transition time (see Note 17) NOTES: 5. 14. 16. 17. 8 8 8 8 ms ns Timing measurements in this table are referenced to VIL max and VIH min. Read-modify-write operation only CBR refresh only System transition times (rise and fall) are to be a minimum of 3 ns and a maximum of 50 ns. PARAMETER MEASUREMENT INFORMATION 1.31 V 5V RL = 218 Ω Output Under Test R1 = 828 Ω Output Under Test CL = 80 pF (See Note A) CL = 80 pF (See Note A) (a) LOAD CIRCUIT R2 = 295 Ω (b) ALTERNATE LOAD CIRCUIT NOTE A: CL includes probe and fixture capacitance. Figure 1. Load Circuits for Timing Parameters POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS034C – MAY 1989 – REVISED JUNE 1995 PARAMETER MEASUREMENT INFORMATION tc(rd) tc(rd) tw(RL) RAS tw(RH) td(CLRH) td(RLCL) td(CHRL) td(RLCH) tt CAS tw(CL) td(RLCA) tw(CH) tsu(CA) td(CACH) td(CARH) th(RA) tsu(RA) th(RLCA) A0 – A8 Row Column Don’t Care th(RHrd) th(CA) th(CHrd) tsu(rd) W Don’t Care Don’t Care ta(C) ta(CA) tdis(CH) See Note A DQ1 – DQ4 Valid Hi-Z ta(RL) ta(G) tdis(G) td(GLRH) G Don’t Care Don’t Care NOTE B: Output can go from the high-impedance state to an invalid-data state prior to the specified access time. Figure 2. Read-Cycle Timing 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS034C – MAY 1989 – REVISED JUNE 1995 PARAMETER MEASUREMENT INFORMATION tc(W) tw(RL) RAS td(CLRH) tt td(RLCL) tw(RH) td(CHRL) td(RLCH) tw(CL) CAS tsu(CA) tw(CH) tsu(RA) th(RA) td(CACH) td(CARH) th(RLCA) A0 – A8 Row Column Don’t Care td(RLCA) th(CA) tsu(WCH) tsu(WRH) th(RLW) th(CLW) tsu(WCL) W Don’t Care Don’t Care tw(WL) th(RLD) tsu(D) DQ1 – DQ4 th(D) Valid Data G Don’t Care Don’t Care Figure 3. Early-Write-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS034C – MAY 1989 – REVISED JUNE 1995 PARAMETER MEASUREMENT INFORMATION tc(W) tw(RL) RAS td(CLRH) tt td(RLCL) tw(RH) td(CHRL) td(RLCH) tw(CL) CAS th(RLCA) tw(CH) tsu(CA) th(RA) td(CACH) td(CARH) tsu(RA) A0 – A8 Row Column Don’t Care th(CA) tsu(WCH) tsu(WRH) td(RLCA) W Don’t Care Don’t Care tsu(D) tw(WL) th(D) th(RLD) th(RLW) DQ1 – DQ4 Don’t Care Valid Data Don’t Care th(WLGL) td(GHD) Don’t Care G Figure 4. Write-Cycle Timing 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS034C – MAY 1989 – REVISED JUNE 1995 PARAMETER MEASUREMENT INFORMATION tc(rdW) tw(RL) RAS tt tw(CL) tw(RH) td(RLCL) td(CHRL) CAS th(RA) tsu(RA) tw(CH) tsu(CA) td(RLCA) th(CA) A0 – A8 Column Row Don’t Care tsu(WCH) th(RLCA) td(RLWL) tsu(rd) W tsu(WRH) tw(WL) Don’t Care Don’t Care td(CAWL) td(CLWL) tsu(D) ta(C) th(D) ta(CA) See Note A DQ1– DQ4 Don’t Care Valid Out Valid In Don’t Care ta(R) tdis(G) ta(G) td(GHD) G Don’t Care Don’t Care th(WLGL) NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time. Figure 5. Read-Write- / Read-Modify-Write-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 13 SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS034C – MAY 1989 – REVISED JUNE 1995 PARAMETER MEASUREMENT INFORMATION tw(RH) tw(RL)P RAS td(RLCL) td(RLCH) tc(P) td(CLRH) tw(CL) tw(CH) td(CHRL) CAS tsu(RA) tsu(CA) td(CACH) th(RLCA) th(RA) A0 – A8 th(CA) Row Column td(CARH) Don’t Care Column td(RLCA) tsu(rd) th(CHrd) th(RHrd) ta(C) W ta(CA) (see Note A) ta(CA) ta(R) tdis(CH) ta(CP) (see Note C) See Note A See Note A DQ1–DQ4 Valid Out Valid Out ta(G) tdis(G) ta(G) tdis(G) G Don’t Care Don’t Care Don’t Care Don’t Care NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. B. A write-cycle or read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing specifications are not violated. C. Access time is ta(CP)- or ta(CA)-dependent. Figure 6. Enhanced-Page-Mode Read-Cycle Timing 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS034C – MAY 1989 – REVISED JUNE 1995 PARAMETER MEASUREMENT INFORMATION tw(RH) tw(RL)P RAS td(RLCH) td(RLCL) tc(P) tw(CH) td(CLRH) td(CHRL) tw(CL) CAS tsu(RA) tsu(CA) td(CACH) th(CA) th(RA) td(CARH) th(RLCA) A0 – A8 Row Column Column td(RLCA) th(RLW) tsu(WCH) tsu(WCH) tsu(WRH) tw(WL) W Don’t Care tsu(D) (see Note B) tsu(D) (see Note B) DQ1–DQ4 G Don’t Care Don’t Care th(D) (see Note B) th(RLD) th(WLGL) th(D) (see Note B) Valid Data In td(GHD) Don’t Care Valid In th(WLGL) Don’t Care td(GHD) Don’t Care Don’t Care NOTES: A. A read cycle or a read-modify-write cycle can be intermixed with the write cycles as long as the read and read-modify-write timing specifications are not violated. B. Referenced to CAS or W, whichever occurs last. Figure 7. Enhanced-Page-Mode Write-Cycle Timing (see Note A) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 15 SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS034C – MAY 1989 – REVISED JUNE 1995 PARAMETER MEASUREMENT INFORMATION tw(RH) tw(RL)P RAS td(RLCH) td(CLRH) td(RLCL) CAS tw(CL) td(CHRL) tc(PM) tsu(RA) tw(CH) th(RLCA) tsu(CA) th(CA) td(RLCA) A0 – A8 Row Column Column td(CLWL) td(CAWL) th(RA) Don’t Care tsu(WCH) tsu(WRH) tw(WL) td(RLWL) W ta(C) tsu(rd) ta(CP) ta(CA) ta(R) tsu(D) See Note A DQ1–DQ4 See Note A Valid In Valid Out Don’t Care th(WLGL) th(D) Valid Out Don’t Care ta(G) td(GHD) tdis(G) G th(WLGL) NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. B. A read or write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not violated. Figure 8. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing (see Note B) 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS034C – MAY 1989 – REVISED JUNE 1995 PARAMETER MEASUREMENT INFORMATION tc(rd) tw(RL) RAS tw(RH) td(CHRL) tt CAS Don’t Care tsu(RA) A0 – A8 td(RHCL)R Don’t Care th(RA) Row Don’t Care W Don’t Care DQ1–DQ4 Don’t Care G Don’t Care Row Figure 9. RAS-Only Refresh Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 17 SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS034C – MAY 1989 – REVISED JUNE 1995 PARAMETER MEASUREMENT INFORMATION Refresh Cycle Refresh Cycle Memory Cycle tw(RH) tw(RL) tw(RH) tw(RL) RAS td(RLCH)R tw(CL) CAS tsu(RA) th(RA) tsu(CA) th(CA) A0 – A8 Row Don’t Care Col th(RHrd) tsu(rd) Don’t Care W ta(C) ta(CA) tdis(CH) ta(R) DQ1–DQ4 Valid Data ta(G) tdis(G) G Figure 10. Hidden-Refresh-Cycle (Enhanced Page Mode) Timing 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS034C – MAY 1989 – REVISED JUNE 1995 PARAMETER MEASUREMENT INFORMATION tc(rd) tw(RH) tw(RL) RAS td(RHCL)R tt td(CLRL)R CAS td(RLCH)R A0 – A8 Don’t Care Hi-Z DQ1–DQ4 G Don’t Care W Don’t Care Figure 11. Automatic CBR Refresh-Cycle Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 19 SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS034C – MAY 1989 – REVISED JUNE 1995 20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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