SyncMOS Technologies International. Inc.
SM79164
8 - Bit Micro-controller
with 64KB flash & 4KB RAM embedded
Product List
Features
SM79164V16J/Q,16MHz 64KB internal flash MCU
SM79164L20P, 20MHz 64KB internal flash MCU
SM79164L25J/Q, 25MHz 64KB internal flash MCU
SM79164C25P, 25MHz 64KB internal flash MCU
SM79164C35J/Q, 35MHz 64KB internal flash MCU
Description
The SM79164 series product is an 8 - bit single chip micro
controller with 64KB on-chip flash and 4K byte RAM
embedded. It is a derivative of the 8052 micro controller
family. It has 8-channel PWM build-in. User can access
on-chip expanded RAM with easier and faster way by its
‘bank mapping direct addressing mode’ scheme. With its
hardware features and powerful instruction set, it’s
straight forward to make it a versatile and cost effective
controller for those applications which demand up to 32
I/O pins for PDIP package or up to 36 I/O pins for
PLCC/QFP package, or applications which need up to
64K byte flash memory for program data.
To program the on-chip flash memory, a commercial writer
is available to do it in parallel programming method.
Ordering Information
yywwv
SM79164ihhkL
yy: year, ww:month
v: version identifier {, A, B,...}
i:process identifier {V=2.4V~3.0V, L=3.0V ~ 3.6V, C=4.5V
~ 5.5V}
hh: working clock in MHz {20, 25, 35}
k: package type postfix {as below table}
L:PB free identifier
No text is Non- PB free ,”P” is PB free
Postfix
P
J
Q
Package
40L PDIP
44L PLCC
44L QFP
Pin/Pad
Configuration
page 2
page 2
page 2
2.4V ~ 3.0V For V Version
Working voltage: 3.0V ~ 3.6V For L Version
4.5V ~ 5.5V For C Version
General 8052 family compatible
12 clocks per machine cycle
64K byte on chip program flash
4096 byte on-chip data RAM
Three 16 bit Timers/Counters
One Watch Dog Timer
Four 8-bit I/O ports for PDIP package
Four 8-bit I/O ports + one 4-bit I/O ports for PLCC or QFP package
Full duplex serial channel
Bit operation instruction
Industrial Level
8-bit Unsigned Division
8-bit Unsigned Multiply
BCD arithmetic
Direct Addressing
Indirect Addressing
Nested Interrupt
Two priority level interrupt
A serial I/O port
Power save modes: Idle mode and Power down mode
Code protection function
Low EMI (inhibit ALE)
Bank mapping direct addressing mode for access on-chip RAM
8 channel PWM function with P1.0 ~ P1.7
Dimension
page 21
page 22
page 23
Taiwan
6F, No. 10-2 Li - Hsinchu First Road ,
Science-based Industrial Park,
Hsinchu, Taiwan 30078
TEL: 886-3-5671820
886-3-5671880
FAX: 886-3-5671891
886-3-5671894
Web site: http://www.syncmos.com.tw
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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SyncMOS Technologies International. Inc.
SM79164
AD1/P0.1
36
36
P0.7/AD7
#EA
P4.1
AD0/P0.0
VDD
P4.2
T2/PWM0/P1.0
T2EX/PWM1/P1.1
PWM2/P1.2
PWM3/P1.3
PWM4/P1.4
37
35
P2.5/A13
PWM0/T2/P1.0
1
40
VDD
PWM1/T2EX/P1.1
2
39
P0.0/AD0
PWM2/P1.2
3
38
P0.1/AD1
37
P0.2/AD2
36
35
P0.3/AD3
P0.4/AD4
34
P0.5/AD5
33
P0.6/AD6
32
P0.7/AD7
31
#EA
30
ALE
29
#PSEN
PWM3/P1.3
PWM4/P1.4
4
5
6
PWM6/P1.6
7
PWM7/P1.7
RXD/P3.0
9
10
(Top View)
RES
8
SM79164ihhP
40L PDIP
PWM5/P1.5
TXD/P3.1
11
#INT0/P3.2
12
#INT1/P3.3
13
28
P2.7/A15
14
27
P2.6/A14
T1/P3.5
15
26
P2.5/A13
#WR/P3.6
16
25
P2.4/A12
#RD/P3.7
17
24
P2.3/A11
XTAL2
18
23
P2.2/A10
XTAL1
19
22
P2.1/A9
VSS
20
21
P2.0/A8
T0/P3.4
P2.6/A14
P2.5/A13
#PSEN
P2.7/A15
P4.1
ALE
P0.7/AD7
#EA
P0.5/AD5
P0.6/AD6
SM79164
ihhQ
44L QFP
38
39
40
41
19
18
17
16
15
(Top View)
42
14
43
13
44
12
1
A12/P2.4
31
20
2
3
4
5
6
7
8
9
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
P4.0
VSS
XTAL1
XTAL2
P3.7/#RD
P3.6/#WR
10 11
T1/P3.5
29
32
21
T0/P3.4
30
ALE
#PSEN
P2.7/A15
P2.6/A14
33 32 31 30 29 28 27 26 25 24 23
22
#INT1/P3.3
34
A11/P2.3
A9/P2.1
A10/P2.2
P4.0
A8/P2.0
AD2/P0.2
37
P0.5/AD5
P0.6/AD6
33
14
(Top View)
15
16
17
18 19 20 21 22 23 24 25 26 27 28
#WR/P3.6
38
34
35
#INT0/P3.2
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
13
12
AD3/P0.3
P4.3
11
P0.4/AD4
TXD/P3.1
10
39
RXD/P3.0
SM79164
ihhJ
44L PLCC
9
P0.4/AD4
P0.3/AD3
P0.2/AD2
1 44 43 42 41 40
PWM6/P1.6
PWM7/P1.7
RES
3 2
PWM5/P1.5
4
P1.1/T2EX/PWM1
P1.0/T2/PWM0
P4.2
VDD
P0.0/AD0
P0.1/AD1
P1.3/PWM3
P1.2/PWM2
5
8
RXD/P3.0
P4.3
T1/P3.5
6
7
#RD/P3.7
XTAL2
XTAL1
VSS
PWM5/P1.5
PWM6/P1.6
PWM7/P1.7
RES
P1.4/PWM4
Pin Configurations
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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SyncMOS Technologies International. Inc.
SM79164
Block Diagram
Timer 1
Timer 2
Timer 0
Decoder &
Register
Stack
Pointer
4096 bytes
RAM
Buffer
WDT
RES
to pertinent blocks
Reset
Circuit
Vdd
Vss
DPTR
Acc
PC
Incrementer
to whole chip
Power
Circuit
Buffer2
Buffer1
to pertinent blocks
Interrupt
Circuit
Program
Counter
ALU
Register
PSW
XTAL2
XTAL1
#EA
Timing
to whole system
Generator
ALE
FFFFH
#PSEN
Instruction
Register
64K
bytes
Port 0
Latch
Port 1
Latch
Port 2
Latch
Port 3
Latch
Flash
Port 4
Latch
Memory
8
PWM
0000H
Port 0
Driver & Mux
8
Port 1
Driver & Mux
8
Port 2
Driver & Mux
Port 3
Driver & Mux
8
8
Port 4
Driver & Mux
4
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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SyncMOS Technologies International. Inc.
SM79164
Pin Descriptions
40L 44L 44L
PDIP QFP PLCC
Pin# Pin# Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
40
41
42
43
44
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
18
19
20
21
22
23
24
25
26
27
29
30
31
32
33
34
35
36
37
38
17
28
39
6
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
21
22
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
40
41
42
43
44
23
34
1
12
Symbol
P1.0/T2/PWM0
P1.1/T2EX/PWM1
P1.2/PWM2
P1.3/PWM3
P1.4/PWM4
P1.5/PWM5
P1.6/PWM6
P1.7/PWM7
RES
P3.0/RXD
P3.1/TXD
P3.2/#INT0
P3.3/#INT1
P3.4/T0
P3.5/T1
P3.6/#WR
P3.7/#RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
#PSEN
ALE
#EA
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
P4.0
P4.1
P4.2
P4.3
Active I/O
H
L/ L/ -
L
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
o
o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
Names
bit 0 of port 1 & timer 2 clock out , PWM channel 0
bit 1 of port 1 & timer 2 control , PWM channel 1
bit 2 of port 1 & PWM channel 2
bit 3 of port 1 & PWM channel 3
bit 4 of port 1 & PWM channel 4
bit 5 of port 1 & PWM channel 5
bit 6 of port 1 & PWM channel 6
bit 7 of port 1 & PWM channel 7
Reset
bit 0 of port 3 & Receive data
bit 1 of port 3 & Transmit data
bit 2 of port 3 & low true interrupt 0
bit 3 of port 3 & low true interrupt 1
bit 4 of port 3 & Timer 0
bit 5 of port 3 & Timer 1
bit 6 of port 3 & ext. memory write
bit 7 of port 3 & ext. mem. read
Crystal out
Crystal in
Sink Voltage, Ground
bit 0 of port 2 & bit 8 of ext. memory address
bit 1 of port 2 & bit 9 of ext. memory address
bit 2 of port 2 & bit 10 of ext. memory address
bit 3 of port 2 & bit 11 of ext. memory address
bit 4 of port 2 & bit 12 of ext. memory address
bit 5 of port 2 & bit 13 of ext. memory address
bit 6 of port 2 & bit 14 of ext. memory address
bit 7 of port 2 & bit 15 of ext. memory address
program storage enable
address latch enable
external access
bit 7 of port 0 & data/address bit 7 of ext. memory
bit 6 of port 0 & data/address bit 6 of ext. memory
bit 5 of port 0 & data/address bit 5 of ext. memory
bit 4 of port 0 & data/address bit 4 of ext. memory
bit 3 of port 0 & data/address bit 3 of ext. memory
bit 2 of port 0 & data/address bit 2 of ext. memory
bit 1 of port 0 & data/address bit 1 of ext. memory
bit 0 of port 0 & data/address bit 0 of ext. memory
Drive Voltage, +5 Vcc
bit 0 of Port 4
bit 1 of Port 4
bit 2 of Port 4
bit 3 of Port 4
Specifications subject to change without notice,contact your sales representatives for the most recent information.
4/26
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SyncMOS Technologies International. Inc.
SM79164
Special Function Register (SFR)
The address $80 to $FF can be accessed by direct addressing mode only.
Address $80 to $FF is SFR area.
The following table lists the SFRs which are identical to general 8052, as well as SM79164 Extension SFRs.
Special Function Register (SFR) Memory Map
$FF
$F8
$F0
B
$F7
ACC
$EF
$E7
$E8
$E0
$D8
$D0
$C8
$C0
P4
PWMC4
PWMC5
PWMC6
PWMC7
$DF
PSW
PWMC0
PWMC1
PWMC2
PWMC3
RCAP2H
TL2
TH2
$D7
$CF
$C7
$BF
T2CON
T2MOD
RCAP2L
$B8
IP
PWMD4
PWMD5
PWMD6
PWMD7
$B0
P3
PWMD0
PWMD1
PWMD2
PWMD3
$A8
$A0
$98
IE
SCON
$90
P1
$88
TCON
TMOD
TL0
TL1
TH0
TH1
$80
P0
SP
DPL
DPH
(Reserved)
RCON
SCONF
$B7
WDTC
$AF
$A7
$9F
WDTKET
$97
P2
SBUF
P1CON
$8F
DBANK
PCON
$87
Note: The text of SFRs with bold type characters are Extension Special Function Registers for SM79164
Addr
SFR
Reset
85H
RCON
00H
7
6
86H
DBANK
0*000001
97H
WDTKEY
00H
9BH
P1CON
00H
PWME7
PWME6
PWME5
9FH
WDTC
0*0**000
WDTE
Reserve
CLEAR
B3H
PWMD0
00H
PWMD07
PWMD06
PWMD05
PWMD04
PWMD03
PWMD02
PWMD01 PWMD00
B4H
PWMD1
00H
PWMD17
PWMD16
PWMD15
PWMD14
PWMD13
PWMD12
PWMD11
BSE
5
4
BS5
BS4
3
2
1
0
RAMS3
RAMS2
RAMS1
RAMS0
BS3
BS2
BS1
BS0
WDTKEY7 WDTKEY6 WDTKEY5 WDTKEY4 WDTKEY3 WDTKEY2 WDTKEY1 WDTKEY0
PWME4
PWME3
PWME2
PWME1
PWME0
PS2
PS1
PS0
PWMD10
B5H
PWMD2
00H
PWMD27
PWMD26
PWMD25
PWMD24
PWMD23
PWMD22
PWMD21 PWMD20
B6H
PWMD3
00H
PWMD37
PWMD36
PWMD35
PWMD34
PWMD33
PWMD32
PWMD31 PWMD30
BBH
PWMD4
00H
PWMD47
PWMD46
PWMD45
PWMD44
PWMD43
PWMD42
PWMD41 PWMD40
BCH
PWMD5
00H
PWMD57
PWMD56
PWMD55
PWMD54
PWMD53
PWMD52
PWMD51 PWMD50
BDH
PWMD6
00H
PWMD67
PWMD66
PWMD65
PWMD64
PWMD63
PWMD62
PWMD61 PWMD60
BEH
PWMD7
00H
PWMD77
PWMD76
PWMD75
PWMD74
PWMD73
PWMD72
PWMD71 PWMD70
Specifications subject to change without notice,contact your sales representatives for the most recent information.
5/26
Ver 2.1
SM79164 08/2006
SyncMOS Technologies International. Inc.
Addr
SFR
Reset
7
BFH
SCONF
0*****00
WDR
TF2
C8H
T2CON
00H
C9H
T2MOD
******00
6
EXF2
5
4
RCLK
TCLK
SM79164
3
EXEN2
2
TR2
1
0
OME
ALEI
C/T2
CP/RL2
T2OE
DCEN
D3H
PWMC0
*****000
PBS0
PFS01
PFS00
D4H
PWMC1
*****000
PBS1
PFS11
PFS10
D5H
PWMC2
*****000
PBS2
PFS21
PFS20
D6H
PWMC3
*****000
PBS3
PFS31
PSF30
DBH
PWMC4
*****000
PBS4
PFS41
PFS40
DCH
PWMC5
*****000
PBS5
PFS51
PFS50
DDH
PWMC6
*****000
PBS6
PFS61
PFS60
DEH
PWMC7
*****000
PBS7
PFS71
PSF70
D8H
P4
****1111
P4.2
P4.1
P4.0
P4.3
Extension Function Description
1. Memory Structure
The SM79164 is the general 8052 hardware core as a single chip micro controller. Its memory structure follows general
8052 structure.
1.1 Program Memory
The SM79164 has 64K byte on-chip flash memory which used as general program memory. The address range for the 64K
byte is $0000 to $FFFF.
FFFF
64K Program
memory space
0000
Note: The single flash block address structure for doing as well as program ROM flash.
1.2 Data Memory
The SM79164 has 4K bytes on-chip RAM, 256 bytes of it are the same as general 8052 internal memory structure while the
expanded 3840 bytes on-chip RAM can be accessed by external memory addressing method (by instruction MOVX), or by
‘Bank mapping direct addressing mode’ as described in page 8.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
6/26
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SM79164 08/2006
SyncMOS Technologies International. Inc.
SM79164
0EFF
FF Higher 128 bytes (Access by
80 indirect addressing mode only)
7F
SFR (Accessed by direct
addressing mode only)
Lower 128 bytes (Accessed by
Expanded 3840 bytes RAM
(Accessed by direct external
addressing mode, by instruction
MOVX, or by Bank mapping
direct addressing mode)
FF
(OME = 1)
80
direct & indirect addressing mode)
00
0000
On-chip expanded RAM address structure.
1.2.1 Data Memory - Lower 128 byte ($00 to $7F, Bank 0 & Bank 1)
Data Memory $00 to $FF is the same as 8052.
The address $00 to $7F can be accessed by direct and indirect addressing modes.
Address $00 to $1F is register area.
Address $20 to $2F is memory bit area.
Address $30 to $7F is for general memory area.
1.2.2 Data Memory - Higher 128 byte ($80 to $FF, Bank 2 & Bank 3)
The address $80 to $FF can be accessed by indirect addressing mode or by bank mapping direct addressing mode.
Address $80 to $FF is data area.
1.2.3 Data Memory - Expanded 3840 bytes ($0000 to $0EFF, Bank 4 ~ Bank 63)
From external address $0000 to $0EFF is the on-chip expanded RAM area, total 3840 bytes. This area can be accessed
by external direct addressing mode (by instruction MOVX) or by bank mapping direct addressing mode as described
below:
1.3 Bank mapping direct addressing mode:
We provide RAM bank address ‘40H~7FH’ as mapping window which allow user access all the 4KB on-chip RAM through
this RAM bank address.
That means using direct addressing mode can access all the 4KB on-chip RAM. Please see next page for the mapping
mode table.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
7/26
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SyncMOS Technologies International. Inc.
BS5
BS4
BS3
BS2
BS1
BS0
040h ~ 07fh
SM79164
Note
mapping address
0
0
0
0
0
0
000h ~ 03fh
lower 128 byte RAM
0
0
0
0
0
1
040h ~ 07fh
lower 128 byte RAM
0
0
0
0
1
0
080h ~ 0bfh
higher 128 byte RAM
0
0
0
0
1
1
0c0h ~ 0ffh
higher 128 byte RAM
0
0
0
1
0
0
0000h ~ 003fh
on-chip expanded 3840 byte RAM
0
0
0
1
0
1
0040h ~ 007fh
“
0
0
0
1
1
0
0080h ~ 00bfh
“
0
0
0
1
1
1
00c0h ~ 00ffh
“
0
0
1
0
0
0
0100h ~ 013fh
“
0
0
1
0
0
1
0140h ~ 017fh
“
0
0
1
0
1
0
0180h ~ 01bfh
“
0
0
1
0
1
1
01c0h ~ 01ffh
“
0
0
1
1
0
0
0200h ~ 023fh
“
0
0
1
1
0
1
0240h ~ 027fh
“
0
0
1
1
1
0
0280h ~ 02bfh
“
0
0
1
1
1
1
02c0h ~ 02ffh
“
0
1
0
0
0
0
0300h ~ 033fh
“
0
1
0
0
0
1
0340h ~ 037fh
“
0
1
0
0
1
0
0380h ~ 03bfh
“
0
1
0
0
1
1
03c0h ~ 03ffh
“
0
1
0
1
0
0
0400h ~ 043fh
“
0
1
0
1
0
1
0440h ~ 047fh
“
0
1
0
1
1
0
0480h ~ 04bfh
“
0
1
0
1
1
1
04c0h~04ffh
“
1
1
1
0
0
1
0d40h ~ 0d7fh
“
1
1
1
0
1
0
0d80h ~ 0dbfh
“
1
1
1
0
1
1
0dc0h ~ 0dffh
“
1
1
1
1
0
0
0e00h ~ 0e3fh
“
1
1
1
1
0
1
0e40h ~ 0e7fh
“
1
1
1
1
1
0
0e80h ~ 0ebfh
“
1
1
1
1
1
1
0ec0h ~ 0effh
“
Specifications subject to change without notice,contact your sales representatives for the most recent information.
8/26
Ver 2.1
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SyncMOS Technologies International. Inc.
SM79164
With this bank mapping scheme, user can access entire 4k byte on-chip RAM with direct addressing method. That means
using the window area ($040~$07F), user can access any bank (64 byte) data of 4k byte on-chip RAM space which is
selected by BS[5:0] of data bank control register (DBANK, $86).
For example, user write #30h to $101 address:
MOV DBANK, #88H
; set bank mapping $040~$07f to $0100~$013f
MOV A, #30H
; store #30H to A
MOV 41H, A
; write #30H to $0101 address
Data Bank Control Register (DBANK, $86)
bit-7
bit-0
BSE
Unused
BS5
BS4
BS3
BS2
BS1
BS0
Read / Write:
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
Reset value:
0
*
0
0
0
0
0
1
Data bank select enable bit BSE = 1 enables the data bank select function
Data bank select enable bit BSE = 0 disables the data bank select function
BS[5:0] setting will map $040~$07F RAM space to entire 4k byte on-chip RAM space.
Internal RAM Control Register (RCON, $85)
bit-7
bit-0
Unused
Unused
Unused
Unused
RAMS3
RAMS2
RAMS1
RAMS0
Read / Write:
-
-
-
-
R/W
R/W
R/W
R/W
Reset value:
*
*
*
*
0
0
0
0
SM79164 has 3840 byte on-chip RAM which can be accessed by external memory addressing method only. (By
instruction MOVX). The address space of instruction MOVX @Rn is determined by bit 3, bit2, bit1, bit 0
(RAMS3, RAMS2, RAMS1, RAMS0) of RCON. The default setting of RAMS3, RAMS2, RAMS1, RAMS0 bits
is 0000 (page0).
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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SyncMOS Technologies International. Inc.
SM79164
RAMS3
RAMS2
RAMS1
RAMS0
MOVX @Ri i=0,1 mapping to expended RAM address
0
0
0
0
$0000 ~ $00FF
0
0
0
1
$0100 ~ $01FF
0
0
1
0
$0200 ~ $02FF
0
0
1
1
$0300 ~ $03FF
0
1
0
0
$0400 ~ $04FF
0
1
0
1
$0500 ~ $05FF
0
1
1
0
$0600 ~ $06FF
0
1
1
1
$0700 ~ $07FF
1
0
0
0
$0800 ~ $08FF
1
0
0
1
$0900 ~ $09FF
1
0
1
0
$0A00 ~ $0AFF
1
0
1
1
$0B00 ~ $0BFF
1
1
0
0
$0C00 ~ $0CFF
1
1
0
1
$0D00 ~ $0DFF
1
1
1
0
$0E00 ~ $0EFF
The port 0, port2, port3.6 and port3.7 can be used as general purpose I/O pin while port0 is open-drain structure.
System Control Register (SCONF, $BF)
bit-7
bit-0
WDR
Unused
Unused
Unused
Unused
Unused
OME
ALEI
Read / Write:
R/W
-
-
-
-
-
R/W
R/W
Reset value:
0
*
*
*
*
*
0
0
WDR : Watch Dog Timer Reset.
OME : 3840 bytes on-chip RAM enable bit
ALEI : ALE output inhibit bit, to reduce EMI
Setting bit 0 (ALEI) of SCONF can inhibit the clock signal in Fosc/6Hz output to the ALE pin.
The bit 1 (OME) of SCONF can enable or disable the on-chip expanded 3840 byte RAM. The default setting of OME bit is
0 (disable).
The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow.
User should check WDR bit whenever un-predicted reset happened.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
10/26
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SyncMOS Technologies International. Inc.
SM79164
1.4 I/O Pin Configuration
The ports 1, 2 and 3 of standard 8051 have internal pull-up resistor, and port 0 has open-drain outputs. Each I/O pin can be
used independently as an input or an output. For I/O ports to be used as an input pin, the port bit latch must contain a ‘1’
which turns off the output driver FET. Then for port 1, 2 and 3 port pin is pulled high by a weak internal pull-up, and can be
pulled low by an external source. The port 0 has open-drain outputs which means its pull-ups are not active during normal
port operation. Writing ‘1’ to the port 0 bit latch will causing bit floating so that it can be used as a high-impedance input.
The port 4 used as GPIO will has the same function as port 1, 2 and 3.
output
data
pin
port 0
standard 8051
port 1, 2 and 3
standard 8051
output
data
input
data
pin
input
data
2. Port 4 for PLCC or QFP package:
The bit addressable port 4 is available with PLCC or QFP package. The port 4 has only 4 pins and its port address is located
at 0D8H. The function of port 4 is the same as the function of port 1, port 2 and port 3.
Port4 (P4, $D8)
bit-7
bit-0
Unused
Unused
Unused
Unused
P4.3
P4.2
P4.1
P4.0
Read / Write:
-
-
-
-
R/W
R/W
R/W
R/W
Reset value:
*
*
*
*
1
1
1
1
The bit 3, bit 2, bit 1, bit 0 output the setting to pin P4.3, P4.2, P4.1, P4.0 respectively.
3. Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT is
useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead
loop or runaway. The WDT function can help user software recover from abnormal software condition. The WDT is different
from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the
WDT counter. User should check WDR bit of SCONF register whenever un-predicted reset happened.
The purpose of the secure procedure is to prevent the WDTC value from being changed when system runaway.
There is a 250KHz RC oscillator embedded in chip. Set WDTE = “1” will enable the RC oscillator and the frequency is independent to the system frequency.
To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count
with the RC oscillator. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when
SM79164 been reset, either hardware reset or WDT reset.
To reset the WDT is done by setting 1 to the CLEAR bit of WDTC before the counter overflow. This will clear the content of
the 16-bit counter and let the counter re-start to count from the beginning.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
11/26
Ver 2.1
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SyncMOS Technologies International. Inc.
SM79164
3.1 Watch Dog Timer Registers:
Watch Dog Timer Registers - WDT Control Register (WDTC, $9F)
bit-7
bit-0
WDTE
Reserve
CLEAR
Unused
Unused
PS2
PS1
PS0
Read / Write:
R/W
-
R/W
-
-
R/W
R/W
R/W
Reset value:
0
*
0
*
*
0
0
0
WDTE : Watch Dog Timer enable bit
CLEAR : Watch Dog Timer reset bit
PS[2:0] : Overflow period select bits
PS [2:0]
Overflow Period (ms)
000
2.048
001
4.096
010
8.192
011
16.384
100
32.768
101
65.536
110
131.072
111
262.144
Watch Dog Key Register - (WDTKEY, $97H)
bit-7
bit-0
WDT
WDT
WDT
WDT
WDT
WDT
WDT
WDT
KEY7
KEY6
KEY5
KEY4
KEY3
KEY2
KEY1
KEY0
Read / Write:
W
W
W
W
W
W
W
W
Reset value:
0
0
0
0
0
0
0
0
By default, the WDTC is read only. User need to write values 1EH, E1H sequentially to the WDTKEY($97H) register to
enable the WDTC write attribute, That is
MOV WDTKEY, # 1EH
MOV WDTKEY, # E1H
When WDTC is set, user need to write another values E1H, 1EH sequentially to the WDTKEY($97H) register to disable the
WDTC write attribute, That is
MOV WDTKEY, # E1H
MOV WDTKEY, # 1EH
Specifications subject to change without notice,contact your sales representatives for the most recent information.
12/26
Ver 2.1
SM79164 08/2006
SyncMOS Technologies International. Inc.
SM79164
Watch Dog Timer Register - System Control Register (SCONF, $BF)
bit-7
bit-0
WDR
Unused
Unused
Unused
Unused
Unused
OME
ALEI
Read / Write:
R/W
-
-
-
-
-
R/W
R/W
Reset value:
0
*
*
*
*
*
0
0
The bit 7 (WDR) of SCONF is Watch Dog TImer Reset bit. It will be set to 1 when reset signal generated by WDT
overflow. User should check WDR bit whenever un-predicted reset happened
4. Reduce EMI Function
The SM79164 allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This function will
inhibit the clock signal in Fosc/6Hz output to the ALE pin.
5. Pulse Width Modulation (PWM)
The Pulse Width Modulation (PWM) module contains 1 kind of PWM sub module: PWM. PWM also has four 8-bit channels.
5.1 PWM Function Description:
Each PWM channel contains a 8-bit wide PWM data register (PWMDR) to decide number of continuous pulses within a
PWM frame cycle. The value programmed in the register will determine the pulse length of the output. The PWM channel
can be configured as 5-bit or 8-bit resolution. If a channel is configured as 5-bit resolution, only LSB 5 bits are available.
The value of each PWM Data Register (PWMDR) is continuously compared with the content of an internal counter to determine the state of each PWM channel output pin.
5.2 PWM Registers - P1CON[7:0], PWMC[7:0], PWMD[7:0]
PWM Registers - Port1 Configuration Register (P1CON, $9B)
PWME7
PWME6
PWME5
PWME4
PWME3
PWME2
PWME1
PWME0
Read / Write:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value:
0
0
0
0
0
0
0
0
PWM[7:0]E: When the bit set to one, the corresponding PWM pin is active as PWM function. When the bit reset to zero, the
corresponding PWM pin is active as I/O pin. Five bits are cleared upon reset.
PWM Registers - PWM Control Register (PWMC[7:0], $DE ~ $DB, $D6 ~ $D3)
bit-7
bit-0
Unused
Unused
Unused
Unused
Unused
PBS[7:0]
PFS[7:0]1
PFS[7:0]0
Read / Write:
-
-
-
-
-
R/W
R/W
R/W
Reset value:
*
*
*
*
*
0
0
0
Specifications subject to change without notice,contact your sales representatives for the most recent information.
13/26
Ver 2.1
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SyncMOS Technologies International. Inc.
SM79164
PFS[7:0][1:0] : These two bits is 2’s power parameter to form a frequency divider for input clock.
PBS[7:0] : This bit decides channel bit resolution. If PBS[7:0] is set, the channel is 5-bit resolution.
PFS[7:0]1
PFS[7:0]0
Divider
PWM clock, Fosc=12MHz
PWM clock, Fosc=24MHz
0
0
0.5
24MHz (note)
48MHz (note)
0
1
1
12MHz
24MHz
1
0
2
6MHz
12MHz
1
1
4
3KHz
6MHz
note : If X’tal > 24MHz, can not select PFS[1:0] = 00
PWM Registers - PWM Data Register (PWMD[7:0], $BE ~ $BB, $B6 ~ $B3)
bit-7
Read /
Write:
Reset value:
bit-0
PWMD
PWMD
PWMD
PWMD
PWMD
PWMD
PWMD
PWMD
[7:0]7
[7:0]6
[7:0]5
[7:0]4
[7:0]3
[7:0]2
[7:0]1
[7:0]0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
PWM[7:0][7:0] : content of PWM Data Register. If PBS[7:0] is set, only PWM[7:0][4:0] are available.]
Specifications subject to change without notice,contact your sales representatives for the most recent information.
14/26
Ver 2.1
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SyncMOS Technologies International. Inc.
SM79164
Example of PWM timing diagram:
For 5-bit resolution channel, M = content of PWMD[7:0]:
M = $00
32T
M = $01
M = $0F
M = $1F
PWM Clock Frequency = 1/T = Fosc / Divider
The PWM output cycle frame frequency = PWM Clock frequency / 32
For 8-bit resolution channel:
M = $00
256T
M = $01
M = $7F
M = $FF
PWM Clock Frequency = 1/T = Fosc / Divider
The PWM output cycle frame frequency = PWM Clock frequency / 256
Specifications subject to change without notice,contact your sales representatives for the most recent information.
15/26
Ver 2.1
SM79164 08/2006
SyncMOS Technologies International. Inc.
SM79164
Operating Conditions
Symbol
Min.
Typ.
Max.
Operating temperature
-40
25
85
VCC
Supply voltage
2.4
-
5.5
Fosc35
Oscillator Frequency
3.0
-
35
TA
Description
Unit.
o
Remarks
C
Ambient temperature under bias
V
Note1
MHz Note2
Note1:Operating Voltage {V=2.4V ~ 3.0V, L=3.0V ~ 3.6V, C=4.5V ~ 5.5V}
Note2:Working Frequency {V=16MHZ for J/Q package,L=20MHZ for P package,L=25MHZ for J/Q package,C=25MHZ for P package,C=35MHZ for J/Q package}
DC Characteristics
(TA = -40 degree C to 85 degree C, Vcc = 2.4V to 5.5V)
Symbol
Parameter
VIL1
VIL2
VIH1
VIH2
VOL1
VOL2
VOH1
Input Low Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
Output High Voltage
port 0,1,2,3,4,#EA
RES, XTAL1
port 0,1,2,3,4,#EA
RES, XTAL1
port 0, ALE, #PSEN
port 1,2,3,4
port 0
Valid
VOH2
Output High Voltage
port 1,2,3,4,ALE,#PSEN
IIL
ITL
ILI
R RES
C IO
I CC
Logical 0 Input Current
Logical Transition Current
Input Leakage Current
Reset Pulldown Resistance
Pin Capacitance
Power Supply Current
port 1,2,3,4
port 1,2,3,4
port 0, #EA
RES
Min.
-0.5
0
2.0
70%Vcc
Max.
0.8
0.8
Vcc+0.5
Vcc+0.5
0.45
0.45
2.4
90%Vcc
2.4
90%Vcc
50
Vdd
-75
-650
+ 10
300
10
20
6.5
50
Unit
V
V
V
V
V
V
V
V
V
V
uA
uA
uA
Kohm
pF
mA
mA
uA
Test Conditions
IOL=3.2mA
IOL=1.6mA
IOH=-800uA (only for VCC=5V)
IOH=-80uA
IOH=-60uA (only for VCC=5V)
IOH=-10uA
Vin=0.45V
Vin=2.0V
0.45V<Vin<Vcc
Freq=1MHz, Ta=25 C
Active mode, 16MHz
Idle mode, 16MHz
Power down mode
Note1: Under steady state (non-transient) conditions, IOL must be externally
Limited as follows: Maximum IOL per port pin : 10mA
Maximum IOL per 8-bit port : port 0
:26mA
port 1,2,3 :15mA
Maximum total IOL for all output pins : 71mA
If IOL exceeds the condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
Note2 : Minimum VCC for Power-down is 2V.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
16/26
Ver 2.1
SM79164 08/2006
SyncMOS Technologies International. Inc.
SM79164
AC Characteristics
(20/25MHz, operating conditions; CL for Port 0, ALE and PSEN Outputs=100pF; CL for all Other Output=80pF)
Symbol
T LHLL
T AVLL
T LLAX
T LLIV
T LLPL
T PLPH
T PLIV
T PXIX
T PXIZ
T AVIV
T PLAZ
T RLRH
T WLWH
T RLDV
T RHDX
T RHDZ
T LLDV
T AVDV
T LLYL
T AVYL
T QVWH
T QVWX
T WHQX
T RLAZ
T YALH
T CHCL
T CLCX
T CLCH
T CHCX
T, TCLCL
Valid
Cycle
RD/WRT
RD/WRT
RD/WRT
RD
RD
RD
RD
RD
RD
RD
RD
RD
WRT
RD
RD
RD
RD
RD
RD/WRT
RD/WRT
WRT
WRT
WRT
RD
RD/WRT
Parameter
ALE pulse width
Address Valid to ALE low
Address Hold after ALE low
ALE low to Valid Instruction In
ALE low to #PSEN low
#PSEN pulse width
#PSEN low to Valid Instruction In
Instruction Hold after #PSEN
Instruction Float after #PSEN
Address to Valid Instruction In
#PSEN low to Address Float
#RD pulse width
#WR pulse width
#RD low to Valid Data In
Data Hold after #RD
Data Float after #RD
ALE low to Valid Data In
Address to Valid Data In
ALE low to #WR High or #RD low
Address Valid to #WR or #RD low
Data Valid to #WR High
Data Valid to #WR transition
Data hold after #WR
#RD low to Address Float
#WR or #RD high to ALE high
clock fall time
clock low time
clock rise time
clock high time
clock period
fosc=16MHz
Min. Typ. Max
115
43
53
240
53
173
177
0
87
292
10
365
365
302
0
145
590
542
178
197
230
403
38
73
53
63
Variable fosc
Unit
Min.
Typ.
Max
2xT - 10
nS
T - 20
nS
T - 10
nS
4xT - 10 nS
T - 10
nS
3xT - 15
nS
3xT - 10 nS
0
nS
T + 25 nS
5xT - 20 nS
10 nS
6xT - 10
nS
6xT - 10
nS
5xT - 10 nS
0
nS
2xT + 20 nS
8xT - 10 nS
9xT - 20 nS
3xT - 10
3xT + 10 nS
4xT - 20
nS
7xT - 35
nS
T - 25
nS
T + 10
nS
5 nS
72
T -10
T + 10 nS
nS
nS
nS
nS
1/fosc
nS
ICC Active mode test circuit
ICC
Vcc
Remarks
Vcc
VCC
RST
(NC)
Clock Signal
SM79164
PO
EA
8
XTAL2
XTAL1
VSS
Specifications subject to change without notice,contact your sales representatives for the most recent information.
17/26
Ver 2.1
SM79164 08/2006
SyncMOS Technologies International. Inc.
SM79164
Application Reference
Valid for SM79164
X'tal
C1
C2
R
3MHz
30 pF
30 pF
open
6MHz
30 pF
30 pF
open
9MHz
30 pF
30 pF
open
X'tal
C1
C2
R
16MHz
30 pF
30 pF
open
25MHz
15 pF
15 pF
62KΩ
33MHz
5 pF
5 pF
6.8KΩ
XI
12MHz
30 pF
30 pF
open
X'tal
SM79164
SM79164
R
X2
C2
C1
NOTE: Oscillation circuit may differs with different crystal or ceramic
resonator in higher oscillation frequency which was due to each
crystal or ceramic resonator has its own characteristics.
User should check with the crystal or ceramic resonator manufacturer
for appropriate value of external components.
Data Memory Read Cycle Timing
T12
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T1
T2
T3
OSC
ALE
#PSEN
#RD
ADDRESS A15 - A8
PORT2
PORT0
INST in Float
A7 - A0
Float
DATA in
Float
ADDRESS
or Float
Specifications subject to change without notice,contact your sales representatives for the most recent information.
18/26
Ver 2.1
SM79164 08/2006
SyncMOS Technologies International. Inc.
SM79164
Program Memory Read Cycle Timing
T12
T1
T2
T3
T4
T5
T6
T10
T9
T8
T7
T11
T1
T12
T2
OSC
ALE
#PSEN
#RD,#WR
PORT2
ADDRESS A15 - A8
PORT0
Float
A7 - A0
Float
INST in
ADDRESS A15 - A8
Float
A7 - A0
Float
Float
INST in
Data Memory Write Cycle Timing
T12
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T1
T2
T3
OSC
ALE
#PSEN
#WR
ADDRESS A15 - A8
PORT2
PORT0
INST
Float
ADDRESS
or Float
DATA OUT
A7 - A0
Specifications subject to change without notice,contact your sales representatives for the most recent information.
19/26
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SyncMOS Technologies International. Inc.
SM79164
I/O Ports Timing
T6
T7
T10
T9
T8
X1
T1
T12
T11
T3
T2
T4
T6
T5
T7
T8
sampled
inputs P0,P1
sampled
inputs P2,P3
Output by
Mov Px,Src
current data
next data
RxD at Serial Port
Shift Clock
(Mode 0)
sampled
Timing Critical, Requirement of External Clock (Vss=0.0V is assumed)
TCLCL
Vdd-0.5V
70%Vdd
20%Vdd-0.1V
0.45V
TCLCX
TCHCL
TCHCX
TCLCH
Tm.I
External Program Memory Read Cycle
TPLPH
#PSEN
ALE
PORT 0
TLHLL
TLLPL
TAVLL
TLLAX
TPXIZ
TPLAZ
TPXIX
TPLIV
Instruction. IN
A0 - A7
A0 - A7
TAVIV
PORT 2
A8 - A15
A8 - A15
Specifications subject to change without notice,contact your sales representatives for the most recent information.
20/26
Ver 2.1
SM79164 08/2006
SyncMOS Technologies International. Inc.
Tm.II
SM79164
External Data Memory Read Cycle
#PSEN
TYHLH
ALE
TLLDV
TRLRH
TLLYL
#RD
TAVLL
TLLAX
TRHDZ
TRLDV
TRLAZ
TRHDX
A0 - A7
from Ri or DPL
PORT 0
DATA IN
A0 - A7
from PCL
INSTRL
IN
TAVYL
TAVDV
PORT 2
A8 - A15 from PCH
P2.0 - P2.7 or A8 - A15 from DPH
Tm.III External Data Memory Write Cycle
#PSEN
TYHLH
TLHLL
ALE
TLLYL
#WR
TWLWH
TAVLL
TLLAX
TQVWX
TWHQX
TQVWH
PORT 0
A0-A7
from Ri or DPL
DATA OUT
A0-A7
From PCL
INSTRL
IN
TAVYL
PORT 2
A8-A15 from PCH
P2.0-P2.7 or A8-A15 from DPH
Specifications subject to change without notice,contact your sales representatives for the most recent information.
21/26
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SM79164
PDIP 40L (600mil) Package Information：
D im e n s io n in m m
D im e n s io n in M IL
S ym b ol
M in
N om
M ax
M in
N om
M ax
A1
0 .2 5 4
－
－
10
－
－
A2
3 .6 8 3
3 .8 1 0
3 .9 3 7
145
150
155
b
0 .3 5 6
0 .5 0 0
0 .6 6 0
14
20
26
b1
0 .3 5 6
0 .4 5 7
0 .5 0 8
14
18
22
b2
1 .0 1 6
1 .2 7 0
1 .5 2 4
40
50
60
b3
1 .0 1 6
1 .3 2 1
1 .6 2 6
40
52
64
c
0 .2 0 3
0 .2 5 4
0 .4 3 2
8
10
17
c1
0 .2 0 3
0 .2 5 4
0 .3 5 6
8
10
14
D
5 2 .0 7
5 2 .2
5 2 .3 2
2050
2055
2060
E
1 4 .9 9
1 5 .2 4
1 5 .4 9
590
600
610
N o te :
E1
1 3 .6 9
1 3 .8 7
1 3 .9 4
539
546
549
1.
R efer to JE D E C S T D .M S -0 1 1 (A C ).
e
－
2 .5 4 0
－
－
100
－
2.
D im e n sio n D a n d E 1 d o n o t in c lu d e m o ld
eB
1 5 .7 5
1 6 .2 6
1 6 .7 6
620
640
660
L
2 .9 2 1
3 .3 0 2
3 .6 8 3
115
130
145
b o d y siz e d im e n s io n in clu d e m o ld m is m a tc h .
S
1 .7 2 7
1 .9 8 1
2 .2 3 5
68
78
88
D im e n sio n b 3 d o e s n o t in clu d e d am b ar
Q1
1 .6 5 1
1 .7 7 8
1 .9 0 5
65
70
75
θ
0°
－
10°
0°
－
10°
p ro tru s io n . A llo w ab le p ro tru s io n is 0 .2 5 m m
p er s id e. D a n d E 1 a re m a x im u m p la s tic
3.
p ro tru s io n . A llo w ab le d a m b a r p ro tru sio n
s h a ll n o t c a u s e th e le ad w id th to e x c e e d th e
m a x im u m b 3 d im en sio n b y m o re th a n 0 .2 m m .
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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SyncMOS Technologies International. Inc.
SM79164
PLCC 44L Package Information：
UNIT
INCH(REF)
MM(BASE)
A
0.180(MAX)
4.572(MAX)
A1
0.024 ±0.005
0.52 ±0.14
A2
0.105 ±0.005
2.667 ±0.127
0.018 + 0.004
0.457 + 0.102
- 0.002
- 0.051
0.028 + 0.004
0.711 + 0.102
- 0.002
- 0.051
SYMBOL
B
B1
c
0.010(TYP)
0.254(TYP)
D
0.690 ±0.010
17.526 ±0.254
D1
0.653 ±0.003
16.586 ±0.076
D2
0.610 ±0.020
15.494 ±0.508
E
0.690 ±0.010
17.526 ±0.254
E1
0.653 ±0.003
16.586 ±0.076
E2
0.610 ±0.010
15.494 ±0.254
e
0.050(TYP)
1.270(TYP)
y
0.003(MAX)
0.076(MAX)
θ
0~5°
0~5°
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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SyncMOS Technologies International. Inc.
SM79164
Q F P 4 4 L ( 1 0 x 1 0 x 2 .0 m m ) P a c k a g e I n fo r m a t io n ：
Dimension in mm
Dimension in MIL
Symbol
Min
Nom
Max
Min
Nom
Max
A
－
－
2.45
－
－
964
A1
0.05
0.15
0.25
2.1
6.0
9.6
A2
1.90
2.00
2.10
74.8
78.7
82.7
b
0.29
0.32
0.45
11.4
12.6
17.7
b1
0.29
0.30
0.41
11.4
11.8
16.1
c
0.11
0.17
0.23
4.3
6.7
9.1
c1
0.11
0.15
0.19
4.3
5.9
7.5
E
13.00
13.20
13.40
512
520
528
E1
9.90
10.00
10.10
390
394
398
【e】
－
0.800
－
－
31.5
－
L
0.73
0.88
1.03
28.7
34.6
40.6
L1
1.50
1.60
1.70
59.1
63.0
66.9
cause the lead width to exceed the maximum b3
y
－
－
0.076
－
－
3
dimension by more than 0.1 mm.
θ
0°
－
7°
0°
－
7°
Note:
1.
Refer to JEDC STD.MS-022(AB).
2.
Dimension E1 do not include mold protrusion.
Allowable protrusion is 0.25mm per side.E1 are
maximum plastic body size dimension include
mold mismatch .
3.
Dimension
b
does
not
include
dambar
protrusion .Allowable dambar protrusion shall not
Specifications subject to change without notice,contact your sales representatives for the most recent information.
24/26
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SM79164 08/2006
SyncMOS Technologies International. Inc.
SM79164
eMCU writer list
Company
Contact info
Tel:02-22182325
Fax:02-22182435
E-mail:
[email protected]
Programmer Model Number
LabTool - 48 (1 * 1)
LabTool - 848 (1*8)
Caprilion
P.O. Box 461 KaoHsiung, Taiwan,
ROC
Web site:
http://www.market.net.tw/ ~ cap/
Tel:07-3865061
Fax:07-3865421
E-mail:
[email protected]
UNIV2000
Hi-Lo
4F, No. 20, 22, LN, 76,
Rui Guang Rd., Nei Hu, Taipei,
Taiwan, ROC.
Web site:
http://www.hilosystems.com.tw
Tel:02-87923301
Fax:02-87923285
E-mail:
[email protected]
All - 11 (1*1)
Gang - 08 (1*8)
Leap
6th F1-4, Lane 609,
Chunghsin Rd., Sec. 5, Sanchung,
Taipei Hsien, Taiwan, ROC
Web site:
http://www.leap.com.tw
Tel:02-29991860
Fax:02-29990015
E-mail:
[email protected]
ChipStation (1*1)
SU - 2000 (1*8)
Xeltek Electronic Co., Ltd
338 Hongwu Road, Nanjing, China
210002
Web site:
http://www.xeltek-cn.com
Tel:+86-25-4408399, 4543153-206
E-mail:
[email protected],
[email protected]
Superpro/2000 (1*1)
Superpro/680 (1*1)
Superpro/280 (1*1)
Superpro/L+(1*1)
Advantech
7F, No.98, Ming-Chung Rd.,
Shin-Tien City, Taipei, Taiwan,
ROC
Web site:
http://www.aec.com.tw
Specifications subject to change without notice,contact your sales representatives for the most recent information.
25/26
Ver 2.1
SM79164 08/2006