SyncMOS Technologies Inc.
SM5964
July 2002
8 - Bit Micro-controller
64KB ISP flash & 1KB RAM embedded
Product List
Features
SM5964C25, 25 MHz 64KB internal flash MCU
SM5964C40, 40 MHz 64KB internal flash MCU
Working voltage: 4.5V through 5.5V
General 8052 family compatible
12 clocks per machine cycle
Description
64K byte on chip flash memory with In-System
Programming (ISP) capability
The SM5964 series product is an 8 - bit single chip
microcontroller with 64KB flash & 1K byte RAM embedded. It has In-System Programming (ISP) function and
is a derivative of the 8052 microcontroller family. It has
5-channel SPWM build-in. User can access on-chip
expanded RAM with easier and faster way by its ‘bank
mapping direct addressing mode’ scheme. With its
hardware features and powerful instruction set, it’s
straight forward to make it a versatile and cost effective
controller for those applications which demand up to 32
I/O pins for PDIP package or up to 36 I/O pins for
PLCC/QFP package, or applications which need up to
64K byte flash memory either for program or for data or
mixed.
To program the on-chip flash memory, a commercial
writer is available to do it in parallel programming
method. The on-chip flash memory can be programmed
in either parallel or serial interface with its ISP feature.
1024 byte on chip data RAM
Three 16 bit Timers/Counters
One Watch Dog Timer
Four 8-bit I/O ports for PDIP package
Four 8-bit I/O ports + one 4-bit I/O ports
for PLCC or QFP package
Full duplex serial channel
Bit operation instruction
Page free jumps
8-bit Unsigned Division
8-bit Unsigned Multiply
BCD arithmetic
Direct Addressing
Indirect Addressing
Nested Interrupt
Ordering Information
Two priority level interrupt
A serial I/O port
yywwv
SM5964ihhk
Power save modes:
Idle mode and Power down mode
yy: year, ww:week
v: version identifier { , A, B, ...}
i: process identifier
hh: working clock in MHz {25, 40}
k: package type postfix {as below table}
Code protection function
Low EMI (inhibit ALE)
Reset with address $0000 blank initiate ISP service program
ISP service program space configurable in N*512byte
(N=0 to 8) size
Postfix
P
J
Q
Package
40L PDIP
44L PLCC
44L QFP
Pin/Pad
Configuration
page 2
page 2
page 2
Bank mapping direct addressing mode for access on-chip
Dimension
page 24
page 25
page 26
RAM
Five channel Specific PWM (SPWM) build-in with P1.3 ~ P1.7
Taiwan
4F, No. 1 Creation Road 1,
Science-based Industrial Park,
Hsinchu, Taiwan 30077
TEL: 886-3-578-3344
886-3-579-2988
FAX: 886-3-579-2960
886-3-578-0493
Website: http://www.syncmos.com.tw
Specifications subject to change without notice,contact your sales representatives for the most recent information.
1/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
8
RES
9
RXD/P3.0
10
TXD/P3.1
11
#INT0/P3.2
12
#INT1/P3.3
13
T0/P3.4
14
P0.6/AD6
33
32
P0.7/AD7
31
#EA
30
ALE
29
#PSEN
28
P2.7/A15
27
P2.6/A14
P2.5/A13
25
P2.4/A12
17
24
P2.3/A11
XTAL2
18
23
P2.2/A10
XTAL1
19
22
P2.1/A9
VSS
20
21
P2.0/A8
SPWM1/P1.4
SPWM0/P1.3
P1.2
#RD/P3.7
1 44 43 42 41 40
39
8
38
9
37
P0.5/AD5
P0.6/AD6
36
P0.7/AD7
35
34
#EA
P4.1
ALE
5
4
10
11
12
13
SM5964ihh-yyyJ
44L PLCC
33
SPWM4/P1.7
3
RES
RXD/P3.0
4
P4.3
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
T1/P3.5
6
P0.1/AD1
44 43 42 41 40 39 38 37 36 35 34
33
32
31
SM5964ihh-yyyQ
5
7
8
30
29
44L QFP
28
(Top View)
26
27
9
25
10
24
11
23
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
#EA
P4.1
ALE
#PSEN
P2.7/A15
P2.6/A14
P2.5/A13
12 13 14 15 16 17 18 19 20 21 22
P0.4/AD4
#PSEN
P2.7/A15
P2.6FA14
P2.5/A13
P2.4/A12
P2.1/A9
P2.2/A10
P2.3/A11
P2.0/A8
VSS
P4.0
XTAL1
XTAL2
32
14
(Top View)
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
#WR/P3.6
#RD/P3.7
SPWM4/P1.7
RES
RXD/P3.0
P4.3
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
T1/P3.5
3 2
7
6
SPWM2/P1.5
SPWM3/P1.6
SPWM3/P1.6
1
2
P0.2/AD2
P0.3/AD3
16
P0.0/AD0
P0.1/AD1
15
#WR/P3.6
T2EX/P1.1
T2/P1.0
P4.2
VDD
T1/P3.5
26
SPWM2/P1.5
P2.4/A12
SPWM4/P1.7
(Top View)
7
SM5964ihh-yyyP
SPWM3/P1.6
40L PDIP
6
P0.2/AD2
P0.3/AD3
P0.5/AD5
SPWM2/P1.5
P2.3/A11
P0.4/AD4
34
5
P0.0/AD0
P0.3/AD3
35
SPWM1/P1.4
P2.1/A9
P0.2/AD2
36
4
SPWM0/P1.3
P2.2/A10
P0.1/AD1
37
P2.0/A8
38
T2EX/P1.1
T2/P1.0
P4.2
VDD
3
VSS
P4.0
P0.0/AD0
P1.2
SPWM0/P1.3
VDD
39
P1.2
40
2
#RD/P3.7
XTAL2
XTAL1
1
#WR/P3.6
T2/P1.0
T2EX/P1.1
SPWM1/P1.4
Pin Configurations
Specifications subject to change without notice,contact your sales representatives for the most recent information.
2/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
Block Diagram
Timer 1
Timer 2
Decoder &
Register
Stack
Pointer
Timer 0
1024 bytes
RAM
Buffer
WDT
RES
Vdd
Vss
to pertinent blocks
Reset
Circuit
PC
Incrementer
to whole chip
Power
Circuit
Buffer2
to pertinent blocks
Interrupt
Circuit
Buffer1
Program
Counter
ALU
Register
PSW
XTAL2
XTAL1
#EA
DPTR
Acc
Timing
to whole system
Generator
ALE
#PSEN
SPWM
Instruction
Register
ISP
Port 0
Latch
Port 1
Latch
Port 0
Port 1
Driver & Mux
Driver & Mux
8
8
Port 2
Latch
Port 2
Driver & Mux
8
Port 3
Latch
Port 4
Latch
Port 3
Driver & Mux
Port 4
Driver & Mux
8
64K
bytes
Flash
Memory
4
Specifications subject to change without notice,contact your sales representatives for the most recent information.
3/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
Pin Descriptions
40L 44L 44L
PDIP QFP PLCC
Pin# Pin# Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
40
41
42
43
44
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
18
19
20
21
22
23
24
25
26
27
29
30
31
32
33
34
35
36
37
38
17
28
39
6
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
21
22
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
40
41
42
43
44
23
34
1
12
Symbol
T2/P1.0
T2EX/P1.1
P1.2
SPWM0/P1.3
SPWM1/P1.4
SPWM2/P1.5
SPWM3/P1.6
SPWM4/P1.7
RES
RXD/P3.0
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
T1/P3.5
#WR/P3.6
#RD/P3.7
XTAL2
XTAL1
VSS
P2.0/A8
P2. 1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
#PSEN
ALE
#EA
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
P4.0
P4.1
P4.2
P4.3
Active I/O
H
L/ L/ -
L/ L/ -
L
L
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
o
o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
Names
timer 2 clock out & bit 0 of port 1
timer 2 control & bit 1 of port 1
bit 2 of port 1
SPWM Channel 0, bit 3 of port 1
SPWM Channel 1, bit 4 of port 1
SPWM Channel 2, bit 5 of port 1
SPWM Channel 3, bit 6 of port 1
SPWM Channel 4, bit 7 of port 1
Reset
Receive data & bit 0 of port 3
Transmit data & bit 1 of port 3
low true interrupt 0 & bit 2 of port 3
low true interrupt 1 & bit 3 of port 3
Timer 0 & bit 4 of port 3
Timer 1 & bit 5 of port 3
ext. memory write & bit 6 of port 3
ext. memory read & bit 7 of port 3
Crystal out
Crystal in
Sink Voltage, Ground
bit 0 of port 2 & bit 8 of external memory address
bit 1 of port 2 & bit 9 of external memory address
bit 2 of port 2 & bit 10 of external memory address
bit 3 of port 2 & bit 11 of external memory address
bit 4 of port 2 & bit 12 of external memory address
bit 5 of port 2 & bit 13 of external memory address
bit 6 of port 2 & bit 14 of external memory address
bit 7 of port 2 & bit 15 of external memory address
program storage enable
address latch enable
external access
bit 7 of port 0 & data/address bit 7 of external memory
bit 6 of port 0 & data/address bit 6 of external memory
bit 5 of port 0 & data/address bit 5 of external memory
bit 4 of port 0 & data/address bit 4 of external memory
bit 3 of port 0 & data/address bit 3 of external memory
bit 2 of port 0 & data/address bit 2 of external memory
bit 1 of port 0 & data/address bit 1 of external memory
bit 0 of port 0 & data/address bit 0 of external memory
Drive Voltage
bit 0 of Port 4
bit 1 of Port 4
bit 2 of Port 4
bit 3 of Port 4
Specifications subject to change without notice,contact your sales representatives for the most recent information.
4/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
Special Function Register (SFR)
The address $80 to $FF can be accessed by direct addressing mode only.
Address $80 to $FF is SFR area.
The following table list the SFRs which are identical to general 8052 as well as SM5964 Extension SFRs.
$F8
$F0
$E8
$E0
$D8
$D0
B
ISPFAL
ISPFD
ISPC
ACC
$E7
$DF
P4
PSW
$C8
$C0
$B8
T2CON
$B0
P3
$A8
IE
$A0
$98
$90
P2
$88
$80
ISPFAH
$FF
$F7
$EF
T2MOD
RCAP2L
RCAP2H
TL2
IP
SCON
$D7
$CF
$C7
$BF
TH2
SCONF
$B7
SPWMD4
SPWMC
SBUF
SPWMD0
SPWMD1
SPWMD2
$AF
$A7
SPWMD3
P1CON
WDTC
P1
$9F
$97
$8F
$87
WDTKEY
TCON
TMOD
TL0
TL1
P0
SP
DPL
DPH
TH0
TH1
RCON
DBANK
PCON
Note: The text of SFRs with bold type characters are Extension Special Function Registers for SM5964
Addr
85H
SFR
Reset
RCON
******00
7
86H
DBANK 0***0001
9BH
P1CON
00000***
SPWM4E
9FH
WDTC
0*0**000
WDTE
A3H
SPWMC
******00
6
5
4
BSE
SPWM3E
SPWM2E
SPWM1E
3
2
BS3
BS2
1
0
RAMS1
RAMS0
BS1
BS0
SPWM0E
CLEAR
PS2
PS1
PS0
FPDIV1
FPDIV0
A4H SPWMD0
00H
SPWMD0.4 SPWMD0.3 SPWMD0.2 SPWMD0.1 SPWMD0.0 BRM0.2
BRM0.1
BRM0.0
A5H SPWMD1
00H
SPWMD1.4 SPWMD1.3 SPWMD1.2 SPWMD1.1 SPWMD1.0 BRM1.2
BRM1.1
BRM1.0
A6H SPWMD2
00H
SPWMD2.4 SPWMD2.3 SPWMD2.2 SPWMD2.1 SPWMD2.0 BRM2.2
BRM2.1
BRM2.0
A7H SPWMD3
00H
SPWMD3.4 SPWMD3.3 SPWMD3.2 SPWMD3.1 SPWMD3.0 BRM3.2
BRM3.1
BRM3.0
00H
SPWMD4.4 SPWMD4.3 SPWMD4.2 SPWMD4.1 SPWMD4.0 BRM4.2
ACH SPWMD4
BFH
SCONF
0****010
WDR
C9H
T2MOD
******00*
*
D8H
P4
****1111
*
*
*
BRM4.1
BRM4.0
ISPE
OME
ALEI
*
*
T2OE
DCEN
P4.3
P4.2
P4.1
P4.0
Specifications subject to change without notice,contact your sales representatives for the most recent information.
5/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
Addr
SFR
Reset
7
6
5
4
3
2
1
0
F4H
ISPFAH
00H
FA15
FA14
FA13
FA12
FA11
FA10
FA9
FA8
F5H
ISPFAL
00H
FA7
FA6
FA5
FA4
FA3
FA2
FA1
FA0
F6H
ISPFD
00H
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
F7H
ISPC
0*****00
START
F1
F0
Extension Function Description
1. Memory Structure
The SM5964 is the general 8052 hardware core to integrate the ISP function module as a single chip microcontroller. Its
memory structure follows general 8052 structure.
1.1 Program Memory
The SM5964 has 64K byte on-chip flash memory which used as general program memory, on which include up to 4K byte
specific ISP service program memory space. The address range for the 64K byte is $0000 to $FFFF. The address range
for the ISP service program is $F000 to $FFFF. The ISP service program size can be partitioned as N blocks of 512 byte
(N=0 to 8). When N=0 means no ISP service program space available, total 64K byte memory used as program memory.
When N=1 means memory address $FE00 to $FFFF reserved for ISP service program. When N=2 means memory
address $FC00 to FFFF reserved for ISP service program,...etc. Value N can be set and programmed into SM5964 by
writer.
ISP service
program space,
up to 4K
64K Program
memory space
FFFF
FE00
FC00
FA00
F800
F600
F400
F200
F000
N=0
N=1
N=7
N=8
1.2 Data Memory
The SM5964 has 1K bytes on-chip RAM, 256 bytes of it are the same as general 8052 internal memory structure while the
expanded 768 bytes on-chip RAM can be accessed by external memory addressing method (by instruction MOVX.) or by
bank mapping direct addressing mode.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
6/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
02FF
Expanded 768 byte (Accessed
by direct external addressing
mode, by instruction MOVX)
FF
FF Higher 128 byte (Accessed by
80 indirect addressing mode only)
(OME = 1)
SFR (Accessed by direct
addressing mode only)
7F
Lower 128 byte (Accessed by
direct
& indirect addressing mode)
00
80
0000
1.2.1 Data Memory - Lower 128 byte ($00 to $7F, Bank 0 & Bank 1)
Data Memory $00 to $FF is the same as 8052.
The address $00 to $7F can be accessed by direct and indirect addressing modes.
Address $00 to $1F is register area.
Address $20 to $2F is memory bit area.
Address $30 to $7F is for general memory area.
1.2.2 Data Memory - Higher 128 byte ($80 to $FF, Bank 2 & Bank 3)
The address $80 to $FF can be accessed by indirect addressing mode or by bank mapping direct addressing mode.
Address $80 to $FF is data area.
1.2.3 Data Memory - Expanded 768 bytes ($0000 to $02FF, Bank 4 ~ Bank 15)
From external address $0000 to $02FF is the on-chip expanded RAM area, total 768 bytes. This area can be accessed by
external direct addressing mode (by instruction MOVX) or by bank mapping direct addressing mode.
If the address of instruction MOVX @DPTR is larger than $02FF then SM5964 will generate the external memory control
signal automatically. The bit 1 (OME) of special function register $BF (SCONF) can enable or disable this expanded 768
byte RAM. The default setting of OME bit is 1 (enable).
The address space of instruction MOVX @Ri, i=0,1 is determined by bit 1 & bit 0 (RAMS1, RAMS0) of special function register $85 (RCON). The default setting of RAMS1, RAMS0 bits is 00 (page0).
One page of data RAM is 256 byte.
RAMS1, RAMS0=00, Rn of instruction MOVX @Ri, i=0,1 mapping to expanded RAM address $0000 to $00FF (page 0)
RAMS1, RAMS0=01, Rn of instruction MOVX @Ri, i=0,1 mapping to expanded RAM address $0100 to $01FF (page 1)
RAMS1, RAMS0=10, Rn of instruction MOVX @Ri, i=0,1 mapping to expanded RAM address $0200 to $02FF (page 2)
RAMS1, RAMS0=11, Rn of instruction MOVX @Ri, i=0,1 mapping to expanded RAM address $XY00 to $XYFF which high
byte address specified by port 2. (SM5964 will generate the external memory control signal automatically).
Specifications subject to change without notice,contact your sales representatives for the most recent information.
7/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
1.3 Bank mapping direct addressing mode:
We provide RAM bank address ‘40H~7FH’ as mapping window which allow user access all the 1K on-chip RAM through
this RAM bank address.
BS3
BS2
BS1
BS0
040h~07fh mapping address
Note
0
0
0
0
000h~03fh
lower 128 byte RAM
0
0
0
1
040h~07fh
lower 128 byte RAM
0
0
1
0
080h~0bfh
higher 128 byte RAM
0
0
1
1
0c0h~0ffh
higher 128 byte RAM
0
1
0
0
0000h~003fh
on-chip expanded 768 byte RAM
0
1
0
1
0040h~007fh
on-chip expanded 768 byte RAM
0
1
1
0
0080h~00bfh
on-chip expanded 768 byte RAM
0
1
1
1
00c0h~00ffh
on-chip expanded 768 byte RAM
1
0
0
0
0100h~013fh
on-chip expanded 768 byte RAM
1
0
0
1
0140h~017fh
on-chip expanded 768 byte RAM
1
0
1
0
0180h~01bfh
on-chip expanded 768 byte RAM
1
0
1
1
01c0h~01ffh
on-chip expanded 768 byte RAM
1
1
0
0
0200h~023fh
on-chip expanded 768 byte RAM
1
1
0
1
0240h~027fh
on-chip expanded 768 byte RAM
1
1
1
0
0280h~02bfh
on-chip expanded 768 byte RAM
1
1
1
1
02c0h~02ffh
on-chip expanded 768 byte RAM
With this bank mapping scheme, user can access entire 1k byte on-chip RAM with direct addressing method. That means
using the window area ($040~$07F), user can access any bank (64 byte) data of 1k byte on-chip RAM space which is
selected by BS[0:3] of data bank control register (DBANK, $86).
For example, user write #30h to $101 address :
MOV DBANK, #88H
; set bank mapping $040~$07f to $0100~$013f
MOV A, #30H
; store #30H to A
MOV 41H, A
; write #30H to $0101 address
Data Bank Control Register (DBANK, $86)
bit-7
Read :
Write :
Reset value :
bit-0
BSE
Unused
Unused
Unused
BS3
BS2
BS1
BS0
0
*
*
*
0
0
0
1
Specifications subject to change without notice,contact your sales representatives for the most recent information.
8/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
Data bank select enable bit BSE = 1 enables the data bank select function
Data bank select enable bit BSE = 0 disables the data bank select function
BS[3:0] setting will map $040~$07F RAM space to entire 1k byte on-chip RAM space.
Internal RAM Control Register (RCON, $85)
bit-7
Read:
Write:
Reset value:
bit-0
Unused
Unused
Unused
Unused
Unused
Unused
RAMS1
RAMS0
*
*
*
*
*
*
0
0
Note: “R” means reserved
SM5964 has 768 byte on-chip RAM which can be accessed by external memory addressing method only. (By instruction MOVX). The address space of instruction MOVX @Rn is determined by bit 1 and bit 0 (RAMS1, RAMS0) of
RCON. The default setting of RAMS1, RAMS0 bits is 00 (page0).
System Control Register (SCONF, $BF)
bit-7
Read:
Write:
Reset value:
bit-0
WDR
Unused
Unused
Unused
Unused
ISPE
OME
ALEI
0
*
*
*
*
0
1
0
WDR: Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1
ISPE: ISP function enable bit
OME: 768 byte on-chip RAM enable bit
ALEI: ALE output inhibit bit, to reduce EMI
Setting bit 0 (ALEI) of SCONF can inhibit the clock signal in Fosc/6Hz output to the ALE pin.
The bit 1 (OME) of SCONF can enable or disable the on-chip expanded 768 byte RAM. The default setting of OME bit is 1
(enable).
The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow.
User should check WDR bit whenever unpredicted reset happened.
2. Port 4 for PLCC or QFP package :
The bit addressable port 4 is available with PLCC or QFP package. The port 4 has only 4 pins and its port address is
located at 0D8H. The function of port 4 is the same as the function of port 1, port 2 and port 3.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
9/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
Port4 (P4, $D8)
bit-7
Read :
Write :
Reset value :
bit-0
Unused
Unused
Unused
Unused
P4.3
P4.2
P4.1
P4.0
*
*
*
*
1
1
1
1
The bit 3, bit 2, bit 1, bit 0 output the setting to pin P4.3, P4.2, P4.1, P4.0 respectively.
3. In-System Programming (ISP) Function
The SM5964 can generate flash control signal by internal hardware circuit. User utilize flash control register, flash address
register and flash data register to perform the ISP function without removing the SM5964 from the system.
The SM5964 provides internal flash control signals which can do flash program/chip erase/page erase/protect functions.
User need to design and use any kind of interface which SM5964 can input data. User then utilize ISP service program to
perform the flash program/chip erase/page erase/protect functions.
3.1 ISP Service Program
The ISP service program is a user developed firmware program which resides in the ISP service program space. After
user developed the ISP service program, user then determine the size of the ISP service program. User need to program
the ISP service program in the SM5964 for the ISP purpose.
The ISP service program were developed by user so that it should includes any features which relates to the flash memory
programming function as well as communication protocol between SM5964 and host device which output data to the
SM5964. For example, if user utilize UART interface to receive/transmit data between SM5964 and host device, the ISP
service program should include baut rate, checksum or parity check or any error-checking mechanism to avoid data
transmission error.
The ISP service program can be initiated under SM5964 active or idle mode. It can not be initiated under power down
mode.
3.2. Lock Bit (N)
The Lock Bit N has two functions: one is for service program size configuration and the other is to lock the ISP service program space from flash erase function.
The ISP service program space address range $F000 to $FFFF. It can be divided as blocks of N*512 byte. (N=0 to 8).
When N=0 means no ISP function, all of 64K byte flash memory can be used as program memory. When N=1 means ISP
service program occupies 512 byte while the rest of 63.5K byte flash memory can be used as program memory. The maximum ISP service program allowed is 4K byte when N=8. Under such configuration, the usable program memory space is
60K byte.
After N determined, SM5964 will reserve the ISP service program space downward from the top of the program address
$FFFF. The start address of the ISP service program located at $Fx00 while x is an even number, depending on the lock
bit N. Please see page 5 program memory diagram for this ISP service program space structure.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
10/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
The lock bit N function is different from the flash protect function. The flash erase function can erase all of the flash memory
except for the locked ISP service program space. If the flash not been protected, the content of ISP service program still
can be read. If the flash been protected, the overall content of flash program memory space including ISP service program
space can not be read.
3.3 Program the ISP Service Program
After Lock Bit N is set and ISP service program been programmed, the ISP service program memory will be protected
(locked) automatically. The lock bit N has its own program/erase timing. It is different from the flash memory program/erase
timing so the locked ISP service program can not be erased by flash erase function. If user need to erase the locked ISP
service program, he can do it by writer only. User can not change ISP service program when SM5964 was in system.
3.4 Initiate ISP Service Program
To initiate the ISP service program is to load the program counter (PC) with start address of ISP service program and execute it. There are two ways to do so:
(1) Blank reset. Hardware reset with first flash address blank ($0000=#FFH) will load the PC with start address of ISP service program.
(2) Execute jump instruction can load the start address of the ISP service program to PC.
User can initiate general 8052 INT function to initiate the ISP service program. After ISP service program executed, user
need to reset the SM5964, either by hardware reset or by WDT, or jump to the address $0000 to re-start the firmware program.
ISP Registers - ISPFAH, ISPFAL, ISPFD and ISPC
ISP Flash Address-High Register (ISPFAH, $F4)
bit-7
Read:
Write:
Reset value:
bit-0
FA15
FA14
FA13
FA12
FA11
FA10
FA9
FA8
0
0
0
0
0
0
0
0
FA15 ~ FA8: flash address-high for ISP function
ISP Flash Address-Low Register (ISPFAL, $F5)
bit-7
Read:
Write:
Reset value:
bit-0
FA7
FA6
FA5
FA4
FA3
FA2
FA1
FA0
0
0
0
0
0
0
0
0
FA7 ~ FA0: flash address-low for ISP function
The ISPFAH & ISPFAL provide the 16-bit flash memory address for ISP function. The flash memory address should not
include the ISP service program space address. If the flash memory address indicated by ISPFAH & ISPFAL registers
Specifications subject to change without notice,contact your sales representatives for the most recent information.
11/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
overlay with the ISP service program space address, the flash program/page erase of ISP function executed thereafter will
have no effect.
ISP Flash Data Register (ISPFD,$F6)
bit-7
Read:
Write:
Reset value:
bit-0
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
0
0
0
0
0
0
0
0
FD7 ~ FD0: flash data for ISP function
The ISPFD provide the 8-bit data for ISP function.
ISP Flash Control Register (ISPC, $F7)
bit-7
Read:
Write:
Reset value:
bit-0
START
Unused
Unused
Unused
Unused
Unused
F1
F0
0
*
*
*
*
*
0
0
F[1: 0] : ISP function select bit
START : ISP function start bit
= 1 : start ISP function which indicated by bit 1, bit 0 (F1, F0)
= 0 : no operation
The START bit is read-only by default, software must write three specific values 55H, AAH and 55H sequentially to the
ISPFD register to enable the START bit write attribute. That is :
MOV ISPFD, #55H
MOV ISPFD, #AAH
MOV ISPFD, #55H
Any attempt to set START bit will not be allowed without the procedure above.
After START bit set to 1 then the SM5964 hardware circuit will latch address and data bus and hold the program counter until
the START bit reset to 0 when ISP function finished. User does not need to check START bit status by software method.
F[1:0]
ISP function
00
Byte program
01
Chip protect
10
Page erase
11
Chip erase
F[1:0] : ISP function select bit
Specifications subject to change without notice,contact your sales representatives for the most recent information.
12/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
One page of flash memory is 512 byte.
To perform byte program/page erase ISP function, user need to specify flash address at first. When performing page erase
function, SM5964 will erase entire page which flash address indicated by ISPFAH & ISPFAL registers located within the page.
e.g. flash address: $XYMN
page erase function will erase from $XY00 to $X(Y+1)FF (Y:even number), or
page erase function will erase from $X(Y-1) 00 to $XYFF (Y:odd number)
To perform the chip erase ISP function, SM5964 will erase all the flash program memory except the ISP service program
space, also, SM5964 will un-protect the flash memory automatically. To perform chip protect ISP function, the SM5964 flash
memory content will be read #00H.
e.g. ISP service program to do the byte program - to program #22H to the address $1005H
MOV SCONF,#04H
; enable SM5964 ISP function
MOV ISPFAH,#10H
; set flash address-high, 10H
MOV ISPFAL,#05H
; set flash address-low, 05H
MOV ISPFD,#22H
; set flash data to be programmed, data = 22H
MOV ISPC,#80H
; start to program #22H to the flash address $1005H
; after byte program finished, START bit of ISPC will be reset to 0 automatically
; program counter then point to the next instruction
ISP Registers - System Control Register (SCONF,$BF)
bit-7
Read:
Write:
Reset value:
bit-0
WDR
Unused
Unused
Unused
Unused
ISPE
OME
ALEI
0
*
*
*
*
0
1
0
The bit 2 (ISPE) of SCONF is ISP enable bit. User can enable overall SM5964 ISP function by setting ISPE bit to 1, to disable
overall ISP function by set ISPE to 0.
The function of ISPE behaves like a security key. User can disable overall ISP function to prevent software program be erased
accidentally.
4. Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT is
useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead loop
or runaway. The WDT function can help user software recover form abnormal software condition. The WDT is different from
Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the WDT
counter. User should check WDR bit of SCONF register whenever unpredicted reset happened
The WDT has selectable divider input for the time base source clock. To select the divider input, the setting of bit2~bit0
(PS2~PS0) of Watch Dog Timer Control Register (WDTC) should be set accordingly.
To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count
with the selected time base source clock which set by PS2~PS0. It will generate a reset signal when overflows. The WDTE bit
will be cleared to 0 automatically when SM5964 been reset, either hardware reset or WDT reset.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
13/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
To reset the WDT is done by setting 1 to the CLEAR bit of WDTC. This will clear the content of the 16-bit counter and let
the counter re-start to count from the beginning.
4.1 Watch Dog Timer Registers: WDTC and SCONF
Watch Dog Timer Register- WDT Control Register (WDTC, $9F)
bit-7
Read:
Write:
Reset value:
bit-0
WDTE
Unused
CLEAR
Unused
Unused
PS2
PS1
PS0
0
*
0
*
*
0
0
0
WDTE: Watch Dog Timer enable bit
CLEAR: Watch Dog Timer counter clear bit
PS[2:0]: clock source divider bit
PS [2:0]
Divider (OSC in)
Time Period (ms) @40MHZ
000
8
13.1
001
16
26.21
010
32
52.42
011
64
104.8
100
128
209.71
101
256
419.43
110
512
838.86
111
1024
1677.72
Watch Dog Timer Register - System Control Register (SCONF, $BF)
bit-7
Read:
Write:
Reset value:
bit-0
WDR
Unused
Unused
Unused
Unused
ISPE
OME
ALEI
0
*
*
*
*
0
1
0
The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT
overflow. User should check WDR bit whenever unpredicted reset happened
Specifications subject to change without notice,contact your sales representatives for the most recent information.
14/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
5. Reduce EMI Function
The SM5964 allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This function will
inhibit the clock signal in Fosc/6Hz output to the ALE pin.
6. Specific Pulse Width Modulation (SPWM)
The Specific Pulse Width Modulation (SPWM) module has five 8-bit channels, each channel contains a 8-bit wide SPWM
data register (SPWMD) to decide number of continuous pulses within a SPWM frame cycle.
6.1 SPWM Function Description:
Each 8-bit SPWM channel is composed of an 8-bit register which contains a 5-bit SPWM in MSB portion and a 3-bit binary
rate multiplier (BRM) in LSB portion. The value programmed in the 5-bit SPWM portion will determine the pulse length of
the output. The 3-bit BRM portion will generate and insert certain narrow pulses among an 8-SPWM-cycle frame. The
number of pulses generated is equal to the number programmed in the 3-bit BRM portion. The usage of the BRM is to
generate equivalent 8-bit resolution SPWM type DAC with reasonably high repetition rate through 5-bit SPWM clock
speed. The PDIV[1:0] settings of SPWMC ($A3) register are divident of Fosc to be SPWM clock, Fosc/2^(PDIV[1:0]+1).
The SPWM output cycle frame repetition rate (frequency) equals (SPWM clock)/32 which is [Fosc/2^(PDIV[1:0]+1)]/32.
6.2 SPWM Registers - P1CON, SPWMC, SPWMR[4:0]
SPWM Registers - Port1 Configuration Register (P1CON, $9B)
bit-7
Read:
Write:
Reset value:
bit-0
SPWM4E
SPWM3E
SPWM2E
SPWM1E
SPWM0E
Unused
Unused
Unused
0
0
0
0
0
*
*
*
SPWM[4:0]E : When the bit set to one, the corresponding SPWM pin is active as SPWM function. When the bit
reset to zero, the corresponding SPWM pin is active as I/O pin. Five bits are cleared upon reset.
SPWM Registers - SPWM Control Register (SPWMC, $A3)
bit-7
Read:
Write:
Reset value:
bit-0
Unused
Unused
Unused
Unused
Unused
Unused
PDIV1
PDIV0
*
*
*
*
*
*
0
0
PDIV[1:0] : These two bits is 2’s power parameter to form a frequency divider for input clock.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
15/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
PDIV1
PDIV0
Divider
SPWM clock, Fosc=20MHz
SPWM clock, Fosc=24MHz
0
0
2
10MHz
12MHz
0
1
4
5MHz
6MHz
1
0
8
2.5MHz
3MHz
1
1
16
1.25MHz
1.5MHz
SPWM Data Register (SPWMD[4:0], $AC, $A4 ~$A7)
bit-7
Read:
Write:
bit-0
SPWMD
[4:0]4
SPWMD
[4:0]3
SPWMD
[4:0]2
SPWMD
[4:0]1
SPWMD
[4:0]0
BRM
[4:0]2
BRM
[4:0]1
BRM
[4:0]0
0
0
0
0
0
0
0
0
Reset value:
SPWMD[4:0][4:0] : content of SPWM Data Register. It determines duty cycle of SPWM output waveform.
BRM[4:0][2:0] : will insert certain narrow pulses among an 8-SPWM-cycle frame
N = BRM[4:0][2:0]
Number of SPWM cycles inserted in an 8-cycle frame
XX1
1
X1X
2
1XX
4
Example of SPWM timing diagram :
MOV SPWMD0 , #83H
MOV P1CON , #08H
1st cycle frame
2nd cycle frame 3rd cycle frame
32T
16T
; SPWMD0[4:0]=10h (=16T high, 16T low), BRM0[2:0] = 3
; Enable P1.3 as PWM output pin
32T
16T
4th cycle frame 5th cycle frame
32T
16T
32T
16T
6th cycle frame 7th cycle frame
32T
1T
1T
(narrow pulse inserted by BRM0[2:0] setting, here BRM0[2:0]=3)
32T
32T
16T
16T
8th cycle frame
16T
32T
16T
1T
SPWM clock = 1 / T = Fosc / 2^(PDIV+1)
The SPWM output cycle frame frequency = SPWM clock / 32 = [Fosc/2^(PDIV+1)]/32
If user use Fosc=20MHz, PDIV[1:0] of SPWMC=#03H, then
SPWM clock = 20MHz/2^4 = 20MHz/16 = 1.25MHz
SPWM output cycle frame frequency = (20MHz/2^4)/32=39.1KHz
Specifications subject to change without notice,contact your sales representatives for the most recent information.
16/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
Operating Conditions
Symbol
Description
Min.
Typ.
Max.
Unit.
TA
Operating temperature
0
25
70
oC
TS
Storage temperature
-55
25
155
oC
Supply voltage
4.5
5.0
5.5
V
VCC5
Remarks
Ambient temperature under bias
Fosc 16
Oscillator Frequency
3.0
16
16
MHz For 5V application
Fosc 25
Oscillator Frequency
3.0
25
25
MHz For 5V application
Fosc 40
Oscillator Frequency
3.0
40
40
MHz For 5V application
DC Characteristics
(16/25/40 MHZ, typical operating conditions, valid for SM5964series)
Symbol
Parameter
VIL1
VIL2
VIH1
VIH2
VOL1
VOL2
VOH1
Input Low Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
Output High Voltage
port 0,1,2,3,4,#EA
RES, XTAL1
port 0,1,2,3,4,#EA
RES, XTAL1
port 0, ALE, #PSEN
port 1,2,3,4
port 0
Valid
VOH2
Output High Voltage
port 1,2,3,4,ALE,#PSEN
IIL
ITL
ILI
R RES
C IO
I CC
Logical 0 Input Current
Logical Transition Current
Input Leakage Current
Reset Pulldown Resistance
Pin Capacitance
Power Supply Current
port 1,2,3,4
port 1,2,3,4
port 0, #EA
RES
Min.
-0.5
0
2.0
70%Vcc
Max.
1.0
0.8
Vcc+0.5
Vcc+0.5
0.45
0.45
2.4
90%Vcc
2.4
90%Vcc
50
Vdd
ICC Active mode test circuit
ICC
Vcc
Vcc
Test Conditions
Unit
V
V
V
V
V
V
V
V
V
V
uA
-75
uA
-650
+ 10
uA
300 Kohm
10
pF
20 mA
15
mA
10 mA
10 mA
mA
7.5
6
mA
150
uA
Vcc=5V
“
“
“
IOL=3.2mA
IOL=1.6mA
IOH=-800uA
IOH=-80uA
IOH=-60uA
IOH=-10uA
Vin=0.45V
Vin=2.0V
0.45V<Vin<Vcc
Freq=1MHz, Ta=25 C
Active mode, 40MHz
Active mode, 25MHz
Active mode, 16MHz
Idle mode, 40MHz
Idle mode, 25MHz
Idle mode, 16MHz
Power down mode
ICC Idle mode test circuit
ICC
VCC
RST
PO
EA
SM5964
(NC)
Clock Signal
XTAL2
XTAL1
VSS
VCC
RST
8
Vcc
PO
EA
8
SM5964
(NC)
Clock Signal
XTAL2
XTAL1
VSS
Specifications subject to change without notice,contact your sales representatives for the most recent information.
17/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
AC Characteristics
(16/25/40 MHZ, operating conditions; CL for Port 0, ALE and PSEN Outputs=150uF; CL for all Other Output=80pF)
Symbol
T LHLL
T AVLL
T LLAX
T LLIV
T LLPL
T PLPH
T PLIV
T PXIX
T PXIZ
T AVIV
Parameter
ALE pulse width
Address Valid to ALE low
Address Hold after ALE low
ALE low to Valid Instruction In
ALE low to #PSEN low
#PSEN pulse width
#PSEN low to Valid Instruction In
Instruction Hold after #PSEN
Instruction Float after #PSEN
Address to Valid Instruction In
T PLAZ
T RLRH
T WLWH
T RLDV
T RHDX
T RHDZ
T LLDV
T AVDV
T LLYL
T AVYL
T QVWH
T QVWX
T WHQX
T RLAZ
T YALH
T CHCL
T CLCX
T CLCH
T CHCX
T, TCLCL
#PSEN low to Address Float
#RD pulse width
#WR pulse width
#RD low to Valid Data In
Data Hold after #RD
Data Float after #RD
ALE low to Valid Data In
Address to Valid Data In
ALE low to #WR High or #RD low
Address Valid to #WR or #RD low
Data Valid to #WR High
Data Valid to #WR transition
Data hold after #WR
#RD low to Address Float
#WR or #RD high to ALE high
clock fall time
clock low time
clock rise time
clock high time
clock period
Valid
Cycle
RD/WRT
RD/WRT
RD/WRT
RD
RD
RD
RD
RD
RD
RD
RD
RD
WRT
RD
RD
RD
RD
RD
RD/WRT
RD/WRT
WRT
WRT
WRT
RD
RD/WRT
f osc 16
Variable f osc
Unit
Min. Typ. Max
Min.
Typ.
Max
115
2xT - 10
nS
43
T - 20
nS
53
T - 10
nS
240
4xT - 10 nS
53
T - 10
nS
173
3xT - 15
nS
177
3xT - 10 nS
0
0
nS
87
T + 25 nS
292
5xT - 20 nS
10
365
365
10
6xT - 10
6xT - 10
302
0
5xT - 10
0
145
590
542
197 3xT - 10
4xT - 20
7xT - 35
T - 25
T + 10
178
230
403
38
73
53
72
63
2xT + 20
8xT - 10
9xT - 20
3xT + 10
5
T + 10
T -10
1/fosc
Remarks
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Specifications subject to change without notice,contact your sales representatives for the most recent information.
18/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
ISP Test Conditions
(40 MHZ, typical operating conditions, valid for SM5964 serires)
Symbol
MAX
Remark
Chip erase
1500ms
Vcc = 5V
Page erase
10ms
“
Program
400us
“
Protect
30us
“
Application Reference
Valid for SM5964
X'tal
C1
C2
R
3MHz
30 pF
30 pF
open
X'tal
C1
C2
R
16MHz
30 pF
30 pF
open
6MHz
30 pF
30 pF
open
25MHz
15 pF
15 pF
62KΩ
XI
9MHz
30 pF
30 pF
open
12MHz
30 pF
30 pF
open
40MHz
2 pF
2 pF
4.7KΩ
X'tal
SM5964
R
X2
C1
C2
Note : Oscillation circuit may differs with different crystal or ceramic
resonator in higher oscillation frequency which was due to
each crystal or ceramic resonator has its own characteristics.
User should check with the crystal or ceramic resonator
manufacture for appropriate value of external components.
Please see SM5964 application note for details.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
19/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
Data Memory Read Cycle Timing
T12
T1
T3
T2
T6
T5
T4
T8
T7
T9
T10
T11
T12
T1
T3
T2
OSC
1
2
ALE
#PSEN
#RD
5
7
3
PORT2
ADDRESS A15 - A8
3
PORT0
INST in Float
4
8
6
Float
A7 - A0
DATA in
Float
ADDRESS
or Float
Program Memory Read Cycle Timing
T12
T2
T1
T3
T4
T5
T6
T8
T7
T9
T10
T11
T1
T12
T2
OSC
ALE
1
2
5
#PSEN
7
#RD,#WR
3
PORT2
PORT0
ADDRESS A15 - A8
3
Float
A7 - A0
4
6
Float
ADDRESS A15 - A8
8
INST in
Float
A7 - A0
Float
INST in
Flat
Specifications subject to change without notice,contact your sales representatives for the most recent information.
20/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
Data Memory Write Cycle Timing
T1
T12
T2
T4
T3
T5
T6
T8
T7
T9
T10
T11
T12
T1
T3
T2
OSC
1
ALE
#PSEN
#WR
5
6
2
PORT2
ADDRESS A15 - A8
2
PORT0
INST
Float
4
3
ADDRESS
or Float
DATA OUT
A7 - A0
I/O Ports Timing
T6
T7
T8
X1
T9
T10
T11
T12
T1
T2
T3
T4
T5
T6
T7
T8
sampled
inputs P0,P1
sampled
inputs P2,P3
Output by
Mov Px,Src
RxD at Serial Port
Shift Clock
(Mode 0)
current data
next data
sampled
Specifications subject to change without notice,contact your sales representatives for the most recent information.
21/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
Timing Critical, Requirement of External Clock (Vss=0.0V is assumed)
TCLCL
Vdd-0.5V
70%Vdd
20%Vdd-0.1V
0.45V
Tm.I
TCLCX
TCHCL
TCHCX
TCLCH
External Program Memory Read Cycle
TPLPH
#PSEN
ALE
TLHLL
TLLPL
TAVLL
TLLAX
TPXIZ
TPLAZ
Instruction. IN
A0 - A7
PORT 0
TPXIX
TPLIV
A0 - A7
TAVIV
Tm.II
A8 - A15
A8 - A15
PORT 2
External Data Memory Read Cycle
#PSEN
TYHLH
ALE
TLLDV
TRLRH
TLLYL
#RD
PORT 0
TAVLL
TLLAX
TRHDZ
TRLDV
TRLAZ
TRHDX
A0 - A7
from Ri or DPL
DATA IN
A0 - A7
FROM PCL
INSTRL
IN
TAVYL
TAVDV
PORT 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
Specifications subject to change without notice,contact your sales representatives for the most recent information.
22/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
Tm.III External Data Memory Write Cycle
#PSEN
TYHLH
TLHLL
ALE
TLLYL
#WR
TAVLL
TLLAX
PORT 0
TWLWH
TQVWX
TQVWH
A0-A7
from Ri or DPL
TWHQX
DATA OUT
A0-A7
From PCL
INSTRL
IN
TAVYL
PORT 2
A8-A15 from PCH
P2.0-P2.7 or A8-A15 from DPH
Specifications subject to change without notice,contact your sales representatives for the most recent information.
23/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
40L 600mil PDIP Information
E
D
S
E1
A2
A1
C
A
L
e1
B1
eA
B
a
Note:
1.Dimension D Max & include mold flash or tie bar
burrs.
2.Dimension E1 does not include interlead flash.
3.Dimension D & E1 include mold mismatch and are
determined at the mold parting line.
4.Dimension B1 does not include dambar protrusion/
infrusion.
5.Controlling dimension is inch.
6.General appearance spec. should base on final visual
Symbol
A
A1
A2
B
B1
C
D
E
E1
e1
L
a
eA
S
Dimension in inch
minimal/maximal
- / 0.210
0.010 / 0.150 / 0.160
0.016 / 0.022
0.048 / 0.054
0.008 / 0.014
- / 2.070
0.590 / 0.610
0.540 / 0.552
0.090 / 0.110
0.120 / 0.140
0 / 15
0.630 / 0.670
- / 0.090
Dimension in mm
minimal/maximal
- / 5.33
0.25 / 3.81 / 4.06
0.41 / 0.56
1.22 / 1.37
0.20 / 0.36
- / 52.58
14.99 / 15.49
13.72 / 14.02
2.29 / 2.79
3.05 / 3.56
0 / 15
16.00 / 17.02
- / 2.29
Specifications subject to change without notice,contact your sales representatives for the most recent information.
24/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
44L Plastic Chip Carrier (PLCC)
L
6
7
E
HE
GE
y
D
A2
HD
A1
A
C
θ
b1
e
b
Symbol
A
A1
A2
b1
b
C
D
E
e
GD
GE
HD
HE
L
θ
GD
Note:
1.Dimension D & E does not include interlead flash.
2.Dimension b1 does not include dambar protrusion/
intrusion.
3.Controlling dimension:Inch
4.General appearance spec. should base on final visual
inspection spec.
y
Dimension in inch
minimal/maximal
- / 0.185
0.020 / 0.145 / 0.155
0.026 / 0.032
0.016 / 0.022
0.008 / 0.014
0.648 / 0.658
0.648 / 0.658
0.050 BSC
0.590 / 0.630
0.590 / 0.630
0.680 / 0.700
0.680 / 0.700
0.090 / 0.110
- / 0.004
/
Dimension in mm
minimal/maximal
- / 4.70
0.51 / 3.68 / 3.94
0.66 / 0.81
0.41 / 0.56
0.20 / 0.36
16.46 / 16.71
16.46 / 16.71
1.27 BSC
14.99 / 16.00
14.99 / 16.00
17.27 / 17.78
17.27 / 17.78
2.29 / 2.79
- / 0.10
/
Specifications subject to change without notice,contact your sales representatives for the most recent information.
25/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
44L Plastic Quad Flat Package
C
L
L1
S
θ2
e
R1
D2 D1 D
Gage Plane
0.25 mm
b
θ3
A2
R2
A1
E2
E1
E
A
e1
seating plane
e
Note:
Dimension D1 and E1 do not include mold protrusion.
Allowance protrusion is 0.25mm per side.
Dimension D1 and E1 do include mold mismatch
and are determined datum plane.
Dimension b does not include dambar protrusion.
Allowance dambar protrusion shall be 0.08 mm total
in excess of the b dimension at maximum material
condition. Dambar cannot be located on the lower
radius or the lead foot.
C
Symbol
A
A1
A2
b
c
D
D1
D2
E
E1
E2
e
L
L1
R1
R2
S
θ
θ1
θ2
θ3
C
Dimension in Inch
minimal/maximal
- / 0.100
0.006 / 0.014
0.071 / 0.087
0.012 / 0.018
0.004 / 0.009
0.520 BSC
0.394 BSC
0.315
0.520 BSC
0.394 BSC
0.315
0.031 BSC
0.029 / 0.041
0.063
0.005 / 0.005 / 0.012
0.008 / 0° / 7°
0° / 10° REF
7° REF
0.004
Dimension in mm
minimal/maximal
- / 2.55
0.15 / 0.35
1.80 / 2.20
0.30 / 0.45
0.09 / 0.20
13.20 BSC
10.00 BSC
8.00
13.20 BSC
10.00 BSC
8.00
0.80 BSC
0.73 / 1.03
1.60
0.13 / 0.13 / 0.30
0.20 / as left
as left
as left
as left
0.10
Specifications subject to change without notice,contact your sales representatives for the most recent information.
26/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
eMCU writer list
Company
Contact info
Tel:02-22182325
Fax:02-22182435
E-mail:
[email protected]
Programmer Model Number
LabTool - 48 ( 1 * 1 )
LabTool - 848 (1*8)
Caprilion
P.O. Box 461 KaoHsiung, Taiwan,
ROC
Website:
http://www.market.net.tw/ ~ cap/
Tel:07-3865061
Fax:07-3865421
E-mail:
[email protected]
UNIV2000
Hi-Lo
4F, No. 20, 22, LN, 76,
Rui Guang Rd., Nei Hu, Taipei,
Taiwan, ROC.
Website:
http://www.hilosystems.com.tw
Tel:02-87923301
Fax:02-87923285
E-mai:
[email protected]
All - 11 (1*1)
Gang - 08 (1*8)
Leap
6th F1-4, Lane 609,
Chunghsin Rd., Sec. 5, Sanchung,
Taipei Hsien, Taiwan, ROC
Website:
http://www.leap.com.tw
Tel:02-29991860
Fax:02-29990015
E-mail:
[email protected]
ChipStation (1*1)
SU - 2000 (1*8)
Xeltek Electronic Co., Ltd
338 Hongwu Road, Nanjing, China
210002
Website:
http://www.xeltek-cn.com
Tel:+86-25-4408399, 4543153-206
E-mail:
[email protected],
[email protected]
Superpro/2000 (1*1)
Superpro/680 (1*1)
Superpro/280 (1*1)
Superpro/L+(1*1)
Advantech
7F, No.98, Ming-Chung Rd.,
Shin-Tien City, Taipei, Taiwan,
ROC
Website:
http://www.aec.com.tw
Specifications subject to change without notice,contact your sales representatives for the most recent information.
27/28
Ver 1.0
PID 5964 07/02
SyncMOS Technologies Inc.
SM5964
July 2002
Feedback / Inquiry
To
: SyncMOS Technologies, Inc.
Attn : MKT / Customer Service Dept.
Fax : 886-3-5792960
: 886-3-5780493
Tel
From
:
Company
:
Dept, Section
:
: 886-3-5792988
Position Title :
: 886-3-5792926
Inquiry Date
:
Ref No
:
Specifications subject to change without notice,contact your sales representatives for the most recent information.
28/28
Ver 1.0
PID 5964 07/02