ETC SM59264

SyncMOS Technologies Inc.
SM59264
May 2002
8 - Bit Micro-controller
with 128KB flash & 1KB RAM embedded
Product List
Features
SM59264C25, 25 MHz 128KB internal flash MCU
SM59264C40, 40 MHz 128KB internal flash MCU
Description
The SM59264 series product is an 8 - bit single chip micro
controller with 128KB on-chip flash which including 64KB
program flash & 64KB data flash and 1K byte RAM
embedded. It has In-System Programming (ISP) function
and is a derivative of the 8052 micro controller family. It
has 4-channel SPWM build-in. User can access on-chip
expanded RAM with easier and faster way by its ‘bank
mapping direct addressing mode’ scheme. With its hardware features and powerful instruction set, it’s straight forward to make it a versatile and cost effective controller for
those applications which demand up to 32 I/O pins for
PDIP package or up to 36 I/O pins for PLCC/QFP package, or applications which need up to 64K byte flash memory for program and/or for data.
To program the on-chip flash memory, a commercial writer
is available to do it in parallel programming method. The
on-chip flash memory can be programmed in either parallel or serial interface with its ISP feature.
Ordering Information
yywwv
SM59264ihhk
yy: year, ww:week
v: version identifier { , A, B, ...}
i: process identifier
hh: working clock in MHz {25, 40}
k: package type postfix {as below table}
Postfix
P
J
Q
Package
40L PDIP
44L PLCC
44L QFP
Pin/Pad
Configuration
page 2
page 2
page 2
Working voltage:4.5V through 5.5V
General 8052 family compatible
12 clocks per machine cycle
64K byte on chip program flash with In-System
Programming (ISP) capability
64K byte on-chip data flash with ISP capability
1024 byte on-chip RAM
Three 16 bit Timers/Counters
One Watch Dog Timer
Four 8-bit I/O ports for PDIP package
Four 8-bit I/O ports + one 4-bit I/O ports for PLCC or QFP
package
Full duplex serial channel
Bit operation instruction
Page free jumps
8-bit Unsigned Division
8-bit Unsigned Multiply
BCD arithmetic
Direct Addressing
Indirect Addressing
Nested Interrupt
Two priority level interrupt
A serial I/O port
Power save modes: Idle mode and Power down mode
Code protection function
Low EMI (inhibit ALE)
Reset with address $0000 blank initiate ISP service program
ISP service program space configurable in N*512 byte
(N=0 to 8) size
Bank mapping direct addressing mode for access on-chip RAM
4 channel SPWM function
Dimension
page 28
page 29
page 30
Taiwan
4F, No. 1 Creation Road 1,
Science-based Industrial Park,
Hsinchu, Taiwan 30077
TEL: 886-3-578-3344
886-3-579-2988
FAX: 886-3-579-2960
886-3-578-0493
Web site: http://www.syncmos.com.tw
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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SyncMOS Technologies Inc.
SM59264
May 2002
P0.7/AD7
#EA
P4.1
RES
RXD/P3.0
P4.3
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
T1/P3.5
4
35
29
P2.5/A13
T2/P1.0
1
40
VDD
T2EX/P1.1
2
39
P0.0/AD0
SPWM0/P1.2
3
38
P0.1/AD1
37
P0.2/AD2
36
35
P0.3/AD3
P0.4/AD4
34
P0.5/AD5
33
P0.6/AD6
SPWM1/P1.3
4
SPWM3/P1.5
6
P1.6
7
P1.7
8
RES
9
RXD/P3.0
10
SM59264 ihhP
40L PDIP
5
(Top View)
SPWM2/P1.4
32
P0.7/AD7
31
#EA
30
ALE
29
#PSEN
28
P2.7/A15
27
P2.6/A14
TXD/P3.1
11
#INT0/P3.2
12
#INT1/P3.3
13
T0/P3.4
14
T1/P3.5
15
26
P2.5/A13
16
25
P2.4/A12
P2.3/A11
#WR/P3.6
17
24
XTAL2
18
23
P2.2/A10
XTAL1
19
22
P2.1/A9
VSS
20
21
P2.0/A8
#RD/P3.7
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.0/AD0
P4.2
VDD
P1.1/T2EX
P1.0/T2
P1.3/SPWM1
P1.2/SPWM0
SM59264
ihhQ
44L QFP
5
6
7
8
30
29
28
27
26
(Top View)
9
25
10
24
11
23
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
#EA
P4.1
ALE
#PSEN
P2.7/A15
P2.6/A14
P2.5/A13
12 13 14 15 16 17 18 19 20 21 22
P2.4/A12
30
31
P2.3/A11
31
P2.4/A12
P2.3/A11
32
ALE
#PSEN
P2.7/A15
P2.6/A14
32
P2.1/A9
34
P2.2/A10
P2.1/A9
3
36
P1.7
33
14
(Top View)
15
16
17
18 19 20 21 22 23 24 25 26 27 28
P4.0
P1.6
37
P0.5/AD5
P0.6/AD6
44 43 42 41 40 39 38 37 36 35 34
33
P2.2/A10
13
38
1
2
P2.0/A8
12
SPWM3/P1.5
P4.0
11
P0.4/AD4
VSS
SM59264
ihhJ
44L PLCC
10
39
#RD/P3.7
XTAL2
XTAL1
9
P1.4/SPWM2
P0.3/AD3
P0.2/AD2
P1.1/T2EX
P1.0/T2
P4.2
VDD
P0.0/AD0
P0.1/AD1
8
#WR/P3.6
T1/P3.5
1 44 43 42 41 40
P2.0/A8
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
3 2
#RD/P3.7
XTAL2
XTAL1
VSS
RXD/P3.0
P4.3
4
5
7
#WR/P3.6
6
SPWM3/P1.5
P1.6
P1.7
RES
P1.3/SPWM1
P1.2/SPWM0
P1.4/SPWM2
Pin Configurations
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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SyncMOS Technologies Inc.
SM59264
May 2002
Block Diagram
Timer 1
Timer 2
Timer 0
Decoder &
Register
Stack
Pointer
1024 bytes
RAM
Buffer
WDT
RES
Vdd
Vss
to pertinent blocks
Reset
Circuit
DPTR
Acc
PC
Incrementer
to whole chip
Power
Circuit
Buffer2
to pertinent blocks
Interrupt
Circuit
Buffer1
Program
Counter
ALU
Register
PSW
XTAL2
XTAL1
#EA
Timing
to whole system
Generator
ALE
#PSEN
1FFFFH
Instruction
Register
64KB
data flash
Port 0
Latch
Port 1
Latch
Port 2
Latch
Port 3
Latch
4
SPWM
ISP
Port 4
Latch
2
10000H
64KB
program
flash
0000H
Port 0
Driver & Mux
8
Port 1
Driver & Mux
8
Port 2
Driver & Mux
Port 3
Driver & Mux
8
8
Port 4
Driver & Mux
4
Specifications subject to change without notice,contact your sales representatives for the most recent information.
3/32
Ver 1.0 PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
Pin Descriptions
40L 44L 44L
PDIP QFP PLCC
Pin# Pin# Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
40
41
42
43
44
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
18
19
20
21
22
23
24
25
26
27
29
30
31
32
33
34
35
36
37
38
17
28
39
6
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
21
22
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
40
41
42
43
44
23
34
1
12
Symbol
T2/P1.0
T2EX/P1.1
SPWM0/P1.2
SPWM1/P1.3
SPWM2/P1.4
SPWM3/P1.5
P1.6
P1.7
RES
RXD/P3.0
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
T1/P3.5
#WR/P3.6
#RD/P3.7
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
#PSEN
ALE
#EA
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
P4.0
P4.1
P4.2
P4.3
Active I/O
H
L/ L/ -
L
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
o
o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
Names
timer 2 clock out & bit 0 of port 1
timer 2 control & bit 1 of port 1
SPWM channel 0, bit 2 of port 1
SPWM channel 1, bit 3 of port 1
SPWM channel 2, bit 4 of port 1
SPWM channel 3, bit 5 of port 1
bit 6 of port 1
bit 7 of port 1
Reset
Receive data & bit 0 of port 3
Transmit data & bit 1 of port 3
low true interrupt 0 & bit 2 of port 3
low true interrupt 1 & bit 3 of port 3
Timer 0 & bit 4 of port 3
Timer 1 & bit 5 of port 3
ext. memory write & bit 6 of port 3
ext. mem. read & bit 7 of port 3
Crystal out
Crystal in
Sink Voltage, Ground
bit 0 of port 2 & bit 8 of ext. memory address
bit 1 of port 2 & bit 9 of ext. memory address
bit 2 of port 2 & bit 10 of ext. memory address
bit 3 of port 2 & bit 11 of ext. memory address
bit 4 of port 2 & bit 12 of ext. memory address
bit 5 of port 2 & bit 13 of ext. memory address
bit 6 of port 2 & bit 14 of ext. memory address
bit 7 of port 2 & bit 15 of ext. memory address
program storage enable
address latch enable
external access & VPP
bit 7 of port 0 & data/address bit 7 of ext. memory
bit 6 of port 0 & data/address bit 6 of ext. memory
bit 5 of port 0 & data/address bit 5 of ext. memory
bit 4 of port 0 & data/address bit 4 of ext. memory
bit 3 of port 0 & data/address bit 3 of ext. memory
bit 2 of port 0 & data/address bit 2 of ext. memory
bit 1 of port 0 & data/address bit 1 of ext. memory
bit 0 of port 0 & data/address bit 0 of ext. memory
Drive Voltage, +5 Vcc
bit 0 of Port 4
bit 1 of Port 4
bit 2 of Port 4
bit 3 of Port 4
Specifications subject to change without notice,contact your sales representatives for the most recent information.
4/32
Ver 1.0 PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
Special Function Register (SFR)
The address $80 to $FF can be accessed by direct addressing mode only.
Address $80 to $FF is SFR area.
The following table lists the SFRs which are identical to general 8052, as well as SM59264 Extension SFRs.
Special Function Register (SFR) Memory Map
$FF
$F8
$F0
B
ISPFAH
ISPFAL
ISPFD
ISPC
ACC
$EF
$E7
P4
$DF
$E8
$E0
$D8
$D0
$C8
$C0
$F7
PSW
T2CON
$B8
IP
$B0
P3
$A8
$A0
$98
IE
T2MOD
RCAP2L
RCAP2H
$D7
$CF
TH2
SCONF
$C7
$BF
$B7
P2
SCON
TL2
SPWMC
SBUF
SPWMD0
SPWMD1
SPWMD2
P1CON
$90
P1
$88
TCON
TMOD
TL0
TL1
TH0
TH1
$80
P0
SP
DPL
DPH
(Reserved)
RCON
WDTC
$AF
$A7
$9F
WDTKEY
$97
SPWMD3
$8F
DBANK
PCON
$87
Note: The text of SFRs with bold type characters are Extension Special Function Registers for SM59264
Addr
SFR
Reset
7
6
5
4
3
2
1
0
RAMS6
RAMS5
RAMS4
RAMS3
RAMS2
RAMS1
RAMS0
BS3
BS2
BS1
BS0
85H
RCON
00H
RAMS7
86H
DBANK
0***0001
BSE
97H
WDTKEY
********
9BH
P1CON
**0000**
WDTKEY7 WDTKEY6 WDTKEY5 WDTKEY4 WDTKEY3 WDTKEY2 WDTKEY1 WDTKEY0
SPWME3
WDTE
SPWME2
SPWME1
9FH
WDTC
0*0**000
A3H
SPWMC
******00
CLEAR
A4H
SPWMD0
00H
SPWMD04 SPWMD03 SPWMD02 SPWMD01 SPWMD00
A5H
SPWMD1
00H
SPWMD14 SPWMD13 SPWMD12 SPWMD11 SPWMD10
A6H
SPWMD2
00H
SPWMD24 SPWMD23 SPWMD22 SPWMD21 SPWMD20
A7H
SPWMD3
00H
SPWMD34 SPWMD33 SPWMD32 SPWMD31 SPWMD30
BFH
SCONF
0***_0000
WDR
C8H
T2CON
00H
TF2
EXF2
RCLK
TCLK
C9H
T2MOD
******00
*
*
*
*
D8H
P4
****1111
SPWME0
PS2
PS1
PS0
SPFS1
SPFS0
BRM02
BRM01
BRM00
BRM12
BRM11
BRM10
BRM22
BRM21
BRM20
BRM32
BRM31
BRM30
DFEN
ISPE
OME
ALEI
EXEN2
TR2
C/T2
CP/RL2
*
*
T2OE
DCEN
P4.3
P4.2
P4.1
P4.0
Specifications subject to change without notice,contact your sales representatives for the most recent information.
5/32
Ver 1.0 PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
Addr
SFR
Reset
7
6
5
4
3
2
1
0
F4H
ISPFAH
00H
FA15
FA14
FA13
FA12
FA11
FA10
FA9
FA8
F5H
ISPFAL
00H
FA7
FA6
FA5
FA4
FA3
FA2
FA1
FA0
F6H
ISPFD
00H
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
F7H
ISPC
0*0***00
START
ISPF1
ISPF0
FAU0
Extension Function Description
1. Memory Structure
The SM59264 is the general 8052 hardware core to integrate the expanded 768 byte data RAM, 64KB flash program memory with ISP function module and 64KB data flash as a single chip micro controller. Its memory structure follows general 8052
structure plus SM59264 proprietary external RAM structure.
1.1 Program Memory
The SM59264 has 64K byte on-chip flash memory which used as general program memory, on which include up to 4K byte
specific ISP service program memory space. The address range for the 64K byte is $0000 to $FFFF. The address range for
the ISP service program is $F000 to $FFFF. The ISP service program size can be partitioned as N blocks of 512 byte (N=0 to
8). When N=0 means no ISP service program space available, total 64K byte memory used as program memory. When N=1
means memory address $FE00 to $FFFF reserved for ISP service program. When N=2 means memory address $FC00 to
FFFF reserved for ISP service program,...etc. Value N can be set and programmed into SM59264 by writer.
1FFFF
64K data
flash space
The area need to
have 17th address
bit, A16, for doing
ISP functions:
(byte program,
chip erase, page
erase, protect)
10000
FFFF
ISP service
program space
upto 4K
64K Program
memory space
FE00
FC00
FA00
F800
F600
F400
F200
F000
N=0
N=1
N=7
N=8
Specifications subject to change without notice,contact your sales representatives for the most recent information.
6/32
Ver 1.0 PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
Note: The single flash block address structure for doing the ISP function to the on-chip data flash as well as
program ROM flash.
1.2 Data Memory
The SM59264 has 1K bytes on-chip RAM, 256 bytes of it are the same as general 8052 internal memory structure while the
expanded 768 bytes on-chip RAM can be accessed by external memory addressing method (by instruction MOVX), or by
‘Bank mapping direct addressing mode’ as described in page 9. The SM59264 also has 64K bytes data flash embedded in.
The contents of data flash can be erased or programmed by software control and can be read by MOVX instruction. User can
use MOVX instruction to access internal RAM, internal data flash or external memory by setting OME and DFEN. The different setting of OME and DFEN will map to different memory block.
02FF
Expanded 768 bytes RAM
(Accessed by direct external
addressing mode, by instruction
MOVX, or by Bank mapping
direct addressing mode)
FF
FF Higher 128 bytes (Access by
80 indirect addressing mode only)
7F
SFR (Accessed by direct
addressing mode only)
Lower 128 bytes (Accessed by
80
direct & indirect addressing mode)
00
0000
On-chip expanded RAM address structure.
DFEN
OME
address of MOVX below 768
address of MOVX over 768
0
0
external memory
external memory
0
1
internal RAM
external memory
1
0
internal data flash
internal data flash
1
1
internal RAM
internal data flash
Specifications subject to change without notice,contact your sales representatives for the most recent information.
7/32
Ver 1.0 PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
internal data flash
FFFF
DFEN = 1
On-chip data flash
as External RAM
(Can be read by
MOVX instruction)
internal RAM
FF
FF Higher 128 bytes
80
7F Lower 128 bytes
02FF
On-chip Expanded
768 byte RAM
(OME=1)
SFR
00
64K bytes
addressing
space
02FF
On-chip data flash
as External RAM
(OME=0)
(Can be read by
MOVX instruction)
(DFEN = 1)
00
0000
0000
Note: External RAM address structure for reading the on-chip data flash.
1.2.1 Data Memory - Lower 128 byte ($00 to $7F, Bank 0 & Bank 1)
Data Memory $00 to $FF is the same as 8052.
The address $00 to $7F can be accessed by direct and indirect addressing modes.
Address $00 to $1F is register area.
Address $20 to $2F is memory bit area.
Address $30 to $7F is for general memory area.
1.2.2 Data Memory - Higher 128 byte ($80 to $FF, Bank 2 & Bank 3)
The address $80 to $FF can be accessed by indirect addressing mode or by bank mapping direct addressing mode.
Address $80 to $FF is data area.
1.2.3 Data Memory - Expanded 768 bytes ($0000 to $02FF, Bank 4 ~ Bank 15)
From external address $0000 to $02FF is the on-chip expanded RAM area, total 768 bytes. This area can be accessed by
external direct addressing mode (by instruction MOVX) or by bank mapping direct addressing mode as described below:
1.3 Bank mapping direct addressing mode:
We provide RAM bank address ‘40H~7FH’ as mapping window which allow user access all the 1K on-chip RAM through
this RAM bank address.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
8/32
Ver 1.0
PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
BS3
BS2
BS1
BS0
040h~07fh mapping address
Note
0
0
0
0
000h~03fh
lower 128 byte RAM
0
0
0
1
040h~07fh
lower 128 byte RAM
0
0
1
0
080h~0bfh
higher 128 byte RAM
0
0
1
1
0c0h~0ffh
higher 128 byte RAM
0
1
0
0
0000h~003fh
on-chip expanded 768 byte RAM
0
1
0
1
0040h~007fh
“
0
1
1
0
0080h~00bfh
“
0
1
1
1
00c0h~00ffh
“
1
0
0
0
0100h~013fh
“
1
0
0
1
0140h~017fh
“
1
0
1
0
0180h~01bfh
“
1
0
1
1
01c0h~01ffh
“
1
1
0
0
0200h~023fh
“
1
1
0
1
0240h~027fh
“
1
1
1
0
0280h~02bfh
“
1
1
1
1
02c0h~02ffh
“
With this bank mapping scheme, user can access entire 1k byte on-chip RAM with direct addressing method. That
means using the window area ($040~$07F), user can access any bank (64 byte) data of 1k byte on-chip RAM space
which is selected by BS[3:0] of data bank control register (DBANK, $86).
For example, user write #30h to $101 address:
MOV DBANK, #88H
; set bank mapping $040~$07f to $0100~$013f
MOV A, #30H
; store #30H to A
MOV 41H, A
; write #30H to $0101 address
Data Bank Control Register (DBANK, $86)
bit-7
Read:
Write:
Reset value:
bit-0
BSE
Unused
Unused
Unused
BS3
BS2
BS1
BS0
0
*
*
*
0
0
0
1
Data bank select enable bit BSE = 1 enables the data bank select function
Data bank select enable bit BSE = 0 disables the data bank select function
BS[3:0] setting will map $040~$07F RAM space to entire 1k byte on-chip RAM space.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
9/32
Ver 1.0 PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
1.4 Data Flash - ($0000 to $FFFF)
SM59264 has 64K byte on-chip data flash embedded. The 64KB on-chip data flash can be read by direct external
addressing mode (by MOVX instruction) which means user does not need to care about 17th flash address bit (FA16). To
read 64KB on-chip data flash is similar to read 64KB external RAM. However, to write (program) data flash is much different from to read data flash. User need to use SyncMOS proprietary ISP function, such as byte program/chip erase/page
erase/protect, to the data flash. To do ISP function to data flash need to set FAU0 bit of ISPC ($F7) at first. User has to
recognize 64K program ROM flash and 64KB data flash as combined one single 128KB flash area for ISP function. 64K
byte data flash resides on top of the 64K byte program ROM flash. Please see ISP function description on page 14 for
detail.
Read data flash:
Using direct external addressing mode (by instruction MOVX). Reading on-chip data flash will
be the same as reading external RAM with MOVX instruction.
For example,
MOVX A, @DPTR or MOVX A, @Ri
; i=0,1
instruction with 16-bit addressing space.
Write data flash:
Using ISP ‘byte program’ function will have to set the FAU0 bit at first.
Erase data flash:
Including ISP ‘chip erase’ function and ‘page erase’ function. When using ‘chip erase’ function, it
will erase all the 64K byte data flash plus 64K byte program ROM flash except the ISP service
program space if lock bit ‘N’ been configured.
Chip protect flash: Using ISP ‘chip protect’ function will protect the 64K byte data flash plus 64K byte program ROM
flash from read out. Once flash been protected, the content read will be all ‘00’.
For ‘byte program’ and ‘page erase’ flash-address-dependent ISP functions, user need to specify the FAU0 bit (=FA16) of
ISPC ($F7) at first for doing with data flash space. The 64K data flash also can be programmed or erased on writer.
1.4.1 Second Data Pointer Register - RCON ($85) and MOVX @Ri, i=1,2 with read function
Using RCON register with MOVX @Ri, i=0,1 instruction enables SM59264 has second Data Pointer Register (DPTR) with
read function only. The content of RCON register determines high byte address of 64KB data flash while content of MOVX
@Ri instruction determines low byte address. This feature similar to DPH and DPL register of MOVX @ DPTR instruction
but with read function only. Using MOVX @Ri instruction to write data to the data flash will have no effect.
Internal RAM Control Register (RCON, $85)
bit-7
Read:
Write:
bit-0
RAMS7
RAMS6
RAMS5
RAMS4
RAMS3
RAMS2
RAMS1
RAMS0
0
0
0
0
0
0
0
0
Reset value:
RAMS[7:0] setting will map on-chip RAM and/or data flash space by pages which accessed by MOVX @Ri
instruction, i=0,1
The address space of instruction MOVX @Ri is determined by RAMS[7:0] of RCON. The default setting of RAMS[7:0] is
00H (page 0).
Specifications subject to change without notice,contact your sales representatives for the most recent information.
10/32
Ver 1.0
PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
One page of data RAM is 256 bytes.
The port 0, port2, port3.6 and port3.7 can be used as general purpose I/O pin while port0 is open-drain structure.
System Control Register (SCONF, $BF)
bit-7
Read:
Write:
Reset value:
bit-0
WDR
Unused
Unused
Unused
DFEN
ISPE
OME
ALEI
0
*
*
*
0
0
0
0
WDR: Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1, The bit
7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT
overflow. User should check WDR bit whenever un-predicted reset happened.
DFEN: 64K Data Flash enable bit. The default setting of DFEN bit is 0 (disable).
ISPE: ISP enable bit
OME: 768 bytes on-chip RAM enable bit, The bit 1 (OME) of SCONF can enable or disable the on-chip expanded
768 byte RAM. The default setting of OME bit is 0 (disable).
ALEI: ALE output inhibit bit, to reduce EMI, Setting bit 0 (ALEI) of SCONF can inhibit the clock signal in Fosc/6Hz
output to the ALE pin.
1.5 I/O Pin Configuration
The ports 1, 2 and 3 of standard 8051 have internal pull-up resistor, and port 0 has open-drain outputs. Each I/O pin can
be used independently as an input or an output. For I/O ports to be used as an input pin, the port bit latch must contain a
‘1’ which turns off the output driver FET. Then for port 1, 2 and 3 port pin is pulled high by a weak internal pull-up, and can
be pulled low by an external source. The port 0 has open-drain outputs which means its pull-ups are not active during normal port operation. Writing ‘1’ to the port 0 bit latch will causing bit floating so that it can be used as a high-impedance
input.
The port 4 used as GPIO will has the same function as port 1, 2 and 3.
output
data
input
data
pin
port 0
standard 8051
output
data
port 1, 2 and 3
standard 8051
pin
input
data
Specifications subject to change without notice,contact your sales representatives for the most recent information.
11/32
Ver 1.0 PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
2. Port 4 for PLCC or QFP package:
The bit addressable port 4 is available with PLCC or QFP package. The port 4 has only 4 pins and its port address is
located at 0D8H. The function of port 4 is the same as the function of port 1, port 2 and port 3.
Port4 (P4, $D8)
bit-7
Read:
Write:
Reset value:
bit-0
Unused
Unused
Unused
Unused
P4.3
P4.2
P4.1
P4.0
*
*
*
*
1
1
1
1
The bit 3, bit 2, bit 1, bit 0 output the setting to pin P4.3, P4.2, P4.1, P4.0 respectively.
3. In-System Programming (ISP) Function
The SM59264 can generate flash control signal by internal hardware circuit. User utilize flash control register, flash address
register and flash data register to perform the in-system programming (ISP) function without removing the SM59264 from
the system.
The SM59264 provides internal flash control signal which can do flash program/chip erase/page erase/protect functions.
User need to design and use any kind of interface which SM59264 can input data. User then utilize ISP service program to
perform the flash program/chip erase/page erase/protect functions.
3.1 ISP Service Program
The ISP service program is a user developed firmware program which resides in the ISP service program space. After user
developed the ISP service program, user then determine the size of the ISP service program. User need to program the
ISP service program in the SM59264 for the ISP purpose.
The ISP service program were developed by user so that it should includes any features which relates to the flash memory
programming function as well as communication protocol between SM59264 and host device which output data to the
SM59264. For example, if user utilize UART interface to receive/transmit data between SM59264 and host device, the ISP
service program should include baud rate, checksum or parity check or any error-checking mechanism to avoid data transmission error.
The ISP service program can be initiated under SM59264 active or idle mode. It can not be initiated under power down
mode.
3.2 Lock Bit (N)
The Lock Bit N has two functions: one is for service program size configuration and the other is to lock the ISP service program space from flash erase function.
The ISP service program space address range from $F000 to $FFFF. It can be divided as blocks of N*512 byte. (N=0 to 8).
When N=0 means no ISP function, all of 64K byte flash memory can be used as program memory. When N=1 means ISP
service program occupies 512 byte while the rest of 63.5K byte flash memory can be used as program memory. The maximum ISP service program allowed is 4K byte for N=8. Under such configuration, the usable program memory space is 60K
byte.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
12/32
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SM59264
May 2002
After N determined, SM59264 will reserve the ISP service program space downward from the top of the program address
$FFFF. The start address of the ISP service program located at $Fx00 while x is an even number, depending on the lock bit
N. Please see page 7 program memory diagram for this ISP service program space structure.
The lock bit N function is different from the flash protect function. The chip erase function can erase all of the flash memory
space including 64KB program flash & 64KB data flash, except for the locked ISP service program space. If the flash not
been protected, the content of flash program still can be read. If the flash been protected, the overall content of flash program memory space including ISP service program space can not be read.
3.3 Program the ISP Service Program
After Lock Bit N is set and ISP service program been programmed, the ISP service program memory will be protected
(locked) automatically. The lock bit N has its own program/erase timing. It is different from the flash memory program/erase
timing so the locked ISP service program can not be erased by flash erase function. If user need to erase the locked ISP
service program, he can do it by writer only. User can not change ISP service program when SM59264 was in system.
3.4 Initiate ISP Service Program
To initiate the ISP service program is to load the program counter (PC) with start address of ISP service program and execute it. There are three ways to do so:
(1) Blank reset. Hardware reset with first flash address blank ($0000=#FFH) will load the PC with start address of ISP service program.
(2) Execute ‘JUMP’ instruction can load the start address of the ISP service program to PC.
(3) Enter’s ISP service program by hardware setting. User can force SM59264 enter ISP service program by setting P2.6,
P2.7 “low or P4.3 “low” during hardware reset period. In application system design, user should take care of the setting
of P2.6, P2.7 and P4.3 at reset period to prevent SM59264 from entering ISP service program.
Enters ISP service program by hardware setting:
P2.6
P2.7
RST
or
10ms
10ms
10ms
10ms
P4.3
RST
Specifications subject to change without notice,contact your sales representatives for the most recent information.
13/32
Ver 1.0 PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
User can initiate general 8052 UART function to initiate the ISP service program. After ISP service program executed, user
need to reset the SM59264, either by hardware reset or by WDT, or jump to the address $0000 to re-start the firmware program.
3.5 ISP Registers - System Control Register (SCONF, $BF)
bit-7
Read:
Write:
Reset value:
bit-0
WDR
Unused
Unused
Unused
DFEN
ISPE
OME
ALEI
0
0
0
0
0
0
0
0
The bit 2 (ISPE) of SCONF is ISP enable bit. User can enable overall ISP function by setting ISPE bit to 1, setting
ISPE to 0 will disable overall ISP function.
The function of ISPE behaves like a security key. User can disable overall ISP function to prevent software program
be erased accidentally.
3.6 ISP Registers: ISPFAH, ISPFAL, ISPFD and ISPC registers
The ISPFAH & ISPFAL provide the 16-bit flash memory address for ISP function. The flash memory address should not
include the ISP service program space address. If the flash memory address indicated by ISPFAH & ISPFAL registers overlay with the ISP service program space address, the flash program/page erase of ISP function executed thereafter will have
no effect.
When performing byte program ISP function, the content of ISPFD register will be programmed to the flash address which
indicated by ISPFAH and ISPFAL registers.
ISP Registers- Flash Address-High Register (ISPFAH, $F4)
bit-7
Read:
Write:
Reset value:
bit-0
FA15
FA14
FA13
FA12
FA11
FA10
FA9
FA8
0
0
0
0
0
0
0
0
FA15 ~ FA8: flash address-high for ISP function
ISP Registers - Flash Address-Low Register (ISPFAL, $F5)
bit-7
Read:
Write:
Reset value:
bit-0
FA7
FA6
FA5
FA4
FA3
FA2
FA1
FA0
0
0
0
0
0
0
0
0
FA7 ~ FA0: flash address-low for ISP function
The ISPFAH & ISPFAL provide the 16-bit flash memory address for ISP function. The flash memory address should not
include the ISP service program space address. If the flash memory address indicated by ISPFAH & ISPFAL registers overlay with the ISP service program space address, the flash program/page erase of ISP function executed thereafter will have
no effect.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
14/32
Ver 1.0 PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
ISP Registers - Flash Data Register (ISPFD, $F6)
bit-7
Read:
Write :
Reset value :
bit-0
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
0
0
0
0
0
0
0
0
FD7 ~FD0 : flash data for ISP function
The ISPFD provide the 8-bit data for ISP function
ISP Registers - Flash Control Register (ISPC, $F7)
bit-7
Read :
Write :
Reset value :
bit-0
START
Unused
FAU0
Unused
Unused
Unused
ISPF1
ISPF0
0
0
0
0
0
0
0
0
ISPF[1:0] : ISP function select bit
ISPF [1:0]
ISP function
00
Byte program
01
Chip protect
10
Page erase (512Byte)
11
Chip erase
START : ISP function start bit
= 1 : start ISP function which indicated by bit 1, bit 0 (ISPF1, ISPF0)
= 0 : no operation
FAU0 : 64K program Flash or 64K Data Flash select bit
= 1 : selected 64K data flash
= 0 : selected 64K program flash
Note: The START bit is read-only by default, software must write three specific values 55H, AAH and 55H sequentially to
the ISPFD register to enable the START bit write attribute. That is :
MOV ISPFD, #55H
MOV ISPFD, #AAH
MOV ISPFD, #55H
Any attempt to set START bit will not be allowed without the procedure above.
After START bit set to 1 then the SM59264 hardware circuit will latch flash address and data bus and hold the program
counter until the START bit reset to 0 when ISP function finished. The program counter (PC) will point to next instruction
after START bit reset to 0. User does not need to check START bit status by software method.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
15/32
Ver 1.0
PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
To perform byte program/page erase ISP function, user need to specify flash address at first. When performing page
erase function, SM59264 will erase entire page which flash address indicated by ISPFAH & ISPFAL registers located
within the page.
e.g. flash address: $XYMN
page erase function will erase from $XY00 to $X(Y+1)FF (Y: even number), or
page erase function will erase from $X(Y-1)00 to $XYFF (Y: odd number)
To perform the chip erase ISP function, SM59264 will erase all the flash program memory and data flash memory except
the ISP service program space if lock bit N been configured. Also, SM59264 will un-protect the flash memory automatically. To perform chip protect ISP function, all the flash memory will be read #00H.
e.g. ISP service program to do the byte program - to program #22H to the address $1005H
MOV ISPFD, #55H
MOV ISPFD, #AAH
MOV ISPFD, #55H
MOV $BF, #04H
; enable SM59264 ISP function
MOV $F4, #10H
; set flash address-high, 10H
MOV $F5, #05H
; set flash address-low, 05H
MOV $F6, #22H
; set flash data to be programmed, data = 22H
MOV $F7, #80H
; start to program #22H to the flash address $1005H
; after byte program finished, START bit of FCR will be reset to 0 automatically
; program counter then point to the next instruction
4. Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT
is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead
loop or runaway. The WDT function can help user software recover from abnormal software condition. The WDT is different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the WDT counter. User should check WDR bit of SCONF register whenever unpracticed reset happened
The purpose of the secure procedure is to prevent the WDTC value from being changed when system runaway.
There is a 250KHz RC oscillator embedded in chip. Set WDTE = “1” will enable the RC oscillator and the frequency is
independent to the system frequency.
To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to
count with the RC oscillator. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically
when SM59264 been reset, either hardware reset or WDT reset.
To reset the WDT is done by setting 1 to the CLEAR bit of WDTC before the counter overflow. This will clear the content of
the 16-bit counter and let the counter re-start to count from the beginning.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
16/32
Ver 1.0
PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
4.1 Watch Dog Timer Registers:
Watch Dog Timer Registers - WDT Control Register (WDTC, $9F)
bit-7
Read :
Write:
Reset value:
bit-0
WDTE
Unused
CLEAR
Unused
Unused
PS2
PS1
PS0
0
*
0
*
*
0
0
0
WDTE: Watch Dog Timer enable bit
CLEAR: Watch Dog Timer reset bit
PS[2:0]: Overflow period select bits
PS [2:0]
Overflow Period (ms)
000
2.048
001
4.096
010
8.192
011
16.384
100
32.768
101
65.536
110
131.072
111
262.144
Watch Dog Key Register - (WDTKEY, $97H)
bit-7
bit-0
Read:
WDT
WDT
WDT
WDT
WDT
WDT
WDT
WDT
Write :
KEY7
KEY6
KEY5
KEY4
KEY3
KEY2
KEY1
KEY0
*
*
*
*
*
*
*
*
Reset value:
By default, the WDTC is read only. User need to write values 1EH, E1H sequentially to the WDTKEY($97H) register to
enable the WDTC write attribute, That is
MOV WDTKEY, # 1EH
MOV WDTKEY, # E1H
When WDTC is set, user need to write another values E1H, 1EH sequentially to the WDTKEY($97H) register to disable the
WDTC write attribute, That is
MOV WDTKEY, # E1H
MOV WDTKEY, # 1EH
Specifications subject to change without notice,contact your sales representatives for the most recent information.
17/32
Ver 1.0
PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
Watch Dog Timer Register - System Control Register (SCONF, $BF)
bit-7
Read :
Write :
bit-0
WDR
Unused
Unused
Unused
DFEN
ISPE
OME
ALEI
0
*
*
*
0
0
0
0
Reset value :
The bit 7 (WDR) of SCONF is Watch Dog TImer Reset bit. It will be set to 1 when reset signal generated by WDT
overflow. User should check WDR bit whenever un-predicted reset happened
5. Reduce EMI Function
The SM59264 allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This function will
inhibit the clock signal in Fosc/6Hz output to the ALE pin.
6. Specific Pulse Width Modulation (SPWM)
The Specific Pulse Width Modulation (SPWM) module contains 1 kind of PWM sub module: SPWM (Specific PWM).
SPWM has four 8-bit channels.
6.1 SPWM Function Description:
The 8-bit SPWM channel is composed of an 8-bit register which contains a 5-bit SPWM in MSB portion and a 3-bit binary
rate multiplier (BRM) in LSB portion. The value programmed in the 5-bit SPWM portion will determine the pulse length of
the output. The 3-bit BRM portion will generate and insert certain narrow pulses among an 8-SPWM-cycle frame. The
number of pulses generated is equal to the number programmed in the 3-bit BRM portion. The usage of the BRM is to
generate equivalent 8-bit resolution SPWM type DAC with reasonably high repetition rate through 5-bit SPWM clock
speed. The SPFS[1:0] settings of SPWMC ($A3) register are dividend of Fosc to be SPWM clock, Fosc/2^(SPFS[1:0]+1).
The SPWM output cycle frame repetition rate (frequency) equals (SPWM clock)/32 which is [Fosc/2^(SPFS[1:0]+1)]/32.
6.2 SPWM Registers - P1CON, SPWMC, SPWMD[3:0]
SPWM Registers - Port1 Configuration Register (P1CON, $9B)
bit-7
Read:
Write:
Reset value:
bit-0
Unused
Unused
SPWME3
SPWME2
SPWME1
SPWME0
Unused
Unused
*
*
0
0
0
0
*
*
SPWME[3:0]: When the bit set to one, the corresponding SPWM pin is active as SPWM function. When the bit reset to
zero, the corresponding SPWM pin is active as I/O pin. Four bits are cleared upon reset.
SPWM Registers - SPWM Control Register (SPWMC, $A3)
Specifications subject to change without notice,contact your sales representatives for the most recent information.
18/32
Ver 1.0
PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
bit-7
Read:
Write:
bit-0
Unused
Unused
Unused
Unused
Unused
Unused
SPFS1
SPFS0
*
*
*
*
*
*
0
0
Reset value:
SPFS[1:0]: These two bits is 2’s power parameter to form a frequency divider for input clock.
SPFS1
SPFS0
Divider
SPWM clock, Fosc=20MHz
SPWM clock, Fosc=24MHz
0
0
2
10MHz
12MHz
0
1
4
5MHz
6MHz
1
0
8
2.5MHz
3MHz
1
1
16
1.25MHz
1.5MHz
SPWM Registers - SPWM Data Register (SPWMD[3:0], $A7 ~$A4)
bit-7
Read:
Write:
Reset value:
bit-0
SPWMD
[4:0]4
SPWMD
[4:0]3
SPWMD
[4:0]2
SPWMD
[4:0]1
SPWMD
[4:0]0
BRM
[2:0]2
BRM
[2:0]1
BRM
[2:0]0
0
0
0
0
0
0
0
0
SPWMD[4:0]: content of SPWM Data Register. It determines duty cycle of SPWM output waveform.
BRM[2:0]: will insert certain narrow pulses among an 8-SPWM-cycle frame
N = BRM[2:0]
Number of SPWM cycles inserted in an 8-cycle frame
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
Example of SPWM timing diagram:
MOV SPWMD0, #83H
MOV P1CON, #08H
; SPWMD0[4:0]=10h (=16T high, 16T low), BRM[2:0] = 3
; Enable P1.3 as SPWM output pin
Specifications subject to change without notice,contact your sales representatives for the most recent information.
19/32
Ver 1.0 PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
1st cycle frame
2nd cycle frame 3rd cycle frame
32T
16T
32T
16T
4th cycle frame 5th cycle frame
32T
16T
32T
16T
6th cycle frame 7th cycle frame
32T
1T
1T
(narrow pulse inserted by BRM0[2:0] setting, here BRM0[2:0]=3)
32T
32T
16T
16T
8th cycle frame
32T
16T
16T
1T
SPWM clock = 1 / T = Fosc / 2^(SPFS[1:0]+1)
The SPWM output cycle frame frequency = SPWM clock / 32 = [Fosc/2^(SPFS[1:0]+1)]/32
If user use Fosc=20MHz, SPFS[1:0] of SPWMC=#03H, then
SPWM clock = 20MHz/2^4 = 20MHz/16 = 1.25MHz
SPWM output cycle frame frequency = (20MHz/2^4)/32=39.1KHz
Specifications subject to change without notice,contact your sales representatives for the most recent information.
20/32
Ver 1.0 PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
Operating Conditions
Symbol
Description
Min.
Typ.
Max.
Unit.
Remarks
Ambient temperature under bias
TA
Operating temperature
0
25
70
oC
TS
Storage temperature
-55
25
155
oC
VCC5
Supply voltage
4.5
5.0
5.5
V
Fosc 16
Oscillator Frequency
3.0
16
16
MHz For 5V application
Fosc 25
Oscillator Frequency
3.0
25
25
MHz For 5V application
Fosc 40
Oscillator Frequency
3.0
40
40
MHz For 5V application
DC Characteristics
(12MHz, typical operating conditions, valid for SM59264 series)
Symbol
Parameter
VIL1
VIL2
VIH1
VIH2
VOL1
VOL2
VOH1
Input Low Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
Output High Voltage
port 0,1,2,3,4,#EA
RES, XTAL1
port 0,1,2,3,4,#EA
RES, XTAL1
port 0, ALE, #PSEN
port 1,2,3,4
port 0
Valid
VOH2
Output High Voltage
port 1,2,3,4,ALE,#PSEN
IIL
ITL
ILI
R RES
C IO
I CC
Logical 0 Input Current
Logical Transition Current
Input Leakage Current
Reset Pulldown Resistance
Pin Capacitance
Power Supply Current
port 1,2,3,4
port 1,2,3,4
port 0, #EA
RES
Min.
-0.5
0
2.0
70%Vcc
Max.
0.8
0.8
Vcc+0.5
Vcc+0.5
0.45
0.45
2.4
90%Vcc
2.4
90%Vcc
50
Vdd
-75
-650
+ 10
300
10
20
6.5
V
V
V
V
V
V
V
V
V
V
uA
uA
uA
Kohm
pF
mA
mA
150
ICC Active mode test circuit
ICC
Vcc
Vcc
Test Conditions
Unit
Vcc=5V
“
“
“
IOL=3.2mA
IOL=1.6mA
IOH=-800uA
IOH=-80uA
IOH=-60uA
IOH=-10uA
Vin=0.45V
Vin=2.0V
0.45V<Vin<Vcc
Freq=1MHz, Ta=25 C
Active mode, 12MHz
Idle mode, 12MHz
Power down mode
uA
ICC Idle mode test circuit
ICC
VCC
RST
PO
EA
SM59264
(NC)
Clock Signal
XTAL2
XTAL1
VSS
VCC
RST
8
Vcc
PO
EA
8
SM59264
(NC)
Clock Signal
XTAL2
XTAL1
VSS
Specifications subject to change without notice,contact your sales representatives for the most recent information.
21/32
Ver 1.0 PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
AC Characteristics
(16/25/40 MHZ, operating conditions; CL for Port 0, ALE and PSEN Outputs=150PF; CL for all Other Output=80pF)
Symbol
T LHLL
T AVLL
T LLAX
T LLIV
T LLPL
T PLPH
T PLIV
T PXIX
T PXIZ
T AVIV
T PLAZ
T RLRH
T WLWH
T RLDV
T RHDX
T RHDZ
T LLDV
T AVDV
T LLYL
T AVYL
T QVWH
T QVWX
T WHQX
T RLAZ
T YALH
T CHCL
T CLCX
T CLCH
T CHCX
T, TCLCL
Parameter
ALE pulse width
Address Valid to ALE low
Address Hold after ALE low
ALE low to Valid Instruction In
ALE low to #PSEN low
#PSEN pulse width
#PSEN low to Valid Instruction In
Instruction Hold after #PSEN
Instruction Float after #PSEN
Address to Valid Instruction In
#PSEN low to Address Float
#RD pulse width
#WR pulse width
#RD low to Valid Data In
Data Hold after #RD
Data Float after #RD
ALE low to Valid Data In
Address to Valid Data In
ALE low to #WR High or #RD low
Address Valid to #WR or #RD low
Data Valid to #WR High
Data Valid to #WR transition
Data hold after #WR
#RD low to Address Float
#WR or #RD high to ALE high
clock fall time
clock low time
clock rise time
clock high time
clock period
Valid
Cycle
RD/WRT
RD/WRT
RD/WRT
RD
RD
RD
RD
RD
RD
RD
RD
RD
WRT
RD
RD
RD
RD
RD
RD/WRT
RD/WRT
WRT
WRT
WRT
RD
RD/WRT
f osc 16
Min. Typ. Max
115
43
53
240
53
173
177
0
87
292
10
365
365
302
0
145
590
542
178
197
230
403
38
73
53
63
Variable fosc
Unit
Min.
Typ.
Max
2xT - 10
nS
T - 20
nS
T - 10
nS
4xT - 10 nS
T - 10
nS
3xT - 15
nS
3xT - 10 nS
0
nS
T + 25 nS
5xT - 20 nS
10 nS
6xT - 10
nS
6xT - 10
nS
5xT - 10 nS
0
nS
2xT + 20 nS
8xT - 10 nS
9xT - 20 nS
3xT - 10
3xT + 10 nS
4xT - 20
nS
7xT - 35
nS
T - 25
nS
T + 10
nS
5 nS
72
T -10
T + 10 nS
nS
nS
nS
nS
1/fosc
nS
Remarks
Specifications subject to change without notice,contact your sales representatives for the most recent information.
22/32
Ver 1.0 PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
ISP Test Conditions
(40 MHZ, typical operating conditions, valid for SM59264 series)
Symbol
MAX
Remark
Chip erase
3000ms
Vcc = 5V
Page erase
10ms
“
Program
30us
“
Protect
400us
“
Application Reference
Valid for SM59264
X'tal
C1
C2
R
3MHz
30 pF
30 pF
open
6MHz
30 pF
30 pF
open
9MHz
30 pF
30 pF
open
12MHz
30 pF
30 pF
open
X'tal
C1
C2
R
16MHz
30 pF
30 pF
open
25MHz
15 pF
15 pF
62KΩ
33MHz
5 pF
5 pF
6.8KΩ
40MHz
2 pF
2 pF
4.7KΩ
XI
X'tal
SM59264
R
X2
C1
C2
Note: Oscillation circuit may differs with different crystal or ceramic
resonator in higher oscillation frequency which was due to
each crystal or ceramic resonator has its own characteristics.
User should check with the crystal or ceramic resonator
manufacture for appropriate value of external components.
Please see SM59264 application note for details.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
23/32
Ver 1.0 PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
Data Memory Read Cycle Timing
T12
T1
T3
T2
T6
T5
T4
T8
T7
T9
T10
T11
T12
T1
T3
T2
OSC
1
2
ALE
#PSEN
#RD
5
7
3
PORT2
ADDRESS A15 - A8
3
PORT0
INST in Float
4
A7 - A0
8
6
Float
DATA in
Float
ADDRESS
or Float
Program Memory Read Cycle Timing
T12
T2
T1
T3
T4
T5
T6
T8
T7
T9
T10
T11
T12
T1
T2
OSC
ALE
1
2
5
#PSEN
7
#RD,#WR
3
PORT2
PORT0
ADDRESS A15 - A8
3
Float
A7 - A0
4
6
Float
ADDRESS A15 - A8
8
INST in
Float
A7 - A0
Float
INST in
Flat
Specifications subject to change without notice,contact your sales representatives for the most recent information.
24/32
Ver 1.0 PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
Data Memory Write Cycle Timing
T12
T1
T2
T4
T3
T5
T8
T7
T6
T9
T10
T11
T12
T1
T2
T3
OSC
1
ALE
#PSEN
#WR
5
6
2
PORT2
ADDRESS A15 - A8
2
PORT0
INST
Float
4
3
ADDRESS
or Float
DATA OUT
A7 - A0
I/O Ports Timing
T6
T7
T8
X1
T9
T10
T11
T12
T1
T2
T3
T4
T5
T6
T7
T8
sampled
inputs P0,P1
sampled
inputs P2,P3
Output by
Mov Px,Src
RxD at Serial Port
Shift Clock
(Mode 0)
current data
next data
sampled
Specifications subject to change without notice,contact your sales representatives for the most recent information.
25/32
Ver 1.0 PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
Timing Critical, Requirement of External Clock (Vss=0.0V is assumed)
TCLCL
Vdd-0.5V
70%Vdd
20%Vdd-0.1V
0.45V
Tm.I
TCLCX
TCHCL
TCHCX
TCLCH
External Program Memory Read Cycle
TPLPH
#PSEN
ALE
TLHLL
TLLPL
TAVLL
TLLAX
TPXIZ
TPLAZ
TPLIV
Instruction. IN
A0 - A7
PORT 0
TPXIX
A0 - A7
TAVIV
Tm.II
A8 - A15
A8 - A15
PORT 2
External Data Memory Read Cycle
#PSEN
TYHLH
ALE
TLLDV
TRLRH
TLLYL
#RD
PORT 0
TAVLL
TLLAX
TRHDZ
TRLDV
TRLAZ
TRHDX
A0 - A7
from Ri or DPL
DATA IN
A0 - A7
FROM PCL
INSTRL
IN
TAVYL
TAVDV
PORT 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
Specifications subject to change without notice,contact your sales representatives for the most recent information.
26/32
Ver 1.0 PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
Tm.III External Data Memory Write Cycle
#PSEN
TYHLH
TLHLL
ALE
TLLYL
#WR
TAVLL
TLLAX
PORT 0
TWLWH
TQVWX
TWHQX
TQVWH
A0-A7
from Ri or DPL
DATA OUT
A0-A7
From PCL
INSTRL
IN
TAVYL
PORT 2
A8-A15 from PCH
P2.0-P2.7 or A8-A15 from DPH
Specifications subject to change without notice,contact your sales representatives for the most recent information.
27/32
Ver 1.0 PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
40L 600mil PDIP Information
E
D
S
E1
A2
A1
C
A
L
e1
B1
eA
B
a
Note:
1.Dimension D Max & include mold flash or tie bar
burrs.
2.Dimension E1 does not include inter lead flash.
3.Dimension D & E1 include mold mismatch and are
determined at the mold parting line.
4.Dimension B1 does not include dam bar protrusion/
infusion.
5.Controlling dimension is inch.
6.General appearance spec. should base on final visual
inspection spec.
Symbol
A
A1
A2
B
B1
C
D
E
E1
e1
L
a
eA
S
Dimension in inch
minimal/maximal
- / 0.210
0.010 / 0.150 / 0.160
0.016 / 0.022
0.048 / 0.054
0.008 / 0.014
- / 2.070
0.590 / 0.610
0.540 / 0.552
0.090 / 0.110
0.120 / 0.140
0 / 15
0.630 / 0.670
- / 0.090
Dimension in mm
minimal/maximal
- / 5.33
0.25 / 3.81 / 4.06
0.41 / 0.56
1.22 / 1.37
0.20 / 0.36
- / 52.58
14.99 / 15.49
13.72 / 14.02
2.29 / 2.79
3.05 / 3.56
0 / 15
16.00 / 17.02
- / 2.29
Specifications subject to change without notice,contact your sales representatives for the most recent information.
28/32
Ver 1.0
PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
44L Plastic Chip Carrier (PLCC)
L
6
7
E
HE
GE
y
D
A2
HD
A1
A
C
θ
b1
e
b
Symbol
A
A1
A2
b1
b
C
D
E
e
GD
GE
HD
HE
L
θ
GD
Note:
1.Dimension D & E does not include inter lead flash.
2.Dimension b1 does not include dam bar protrusion/
intrusion.
3.Controlling dimension: Inch
4.General appearance spec. should base on final visual
inspection spec.
y
Dimension in inch
minimal/maximal
- / 0.185
0.020 / 0.145 / 0.155
0.026 / 0.032
0.016 / 0.022
0.008 / 0.014
0.648 / 0.658
0.648 / 0.658
0.050 BSC
0.590 / 0.630
0.590 / 0.630
0.680 / 0.700
0.680 / 0.700
0.090 / 0.110
- / 0.004
/
Dimension in mm
minimal/maximal
- / 4.70
0.51 / 3.68 / 3.94
0.66 / 0.81
0.41 / 0.56
0.20 / 0.36
16.46 / 16.71
16.46 / 16.71
1.27 BSC
14.99 / 16.00
14.99 / 16.00
17.27 / 17.78
17.27 / 17.78
2.29 / 2.79
- / 0.10
/
Specifications subject to change without notice,contact your sales representatives for the most recent information.
29/32
Ver 1.0
PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
44L Plastic Quad Flat Package
C
L
L1
S
θ2
e
R1
D2 D1 D
Gage Plane
0.25 mm
b
θ3
A2
R2
A1
E2
E1
E
A
e1
seating plane
C
e
Note:
Dimension D1 and E1 do not include mold protrusion.
Allowance protrusion is 0.25mm per side.
Dimension D1 and E1 do include mold mismatch
and are determined datum plane.
Dimension b does not include dam bar protrusion.
Allowance dam bar protrusion shall be 0.08 mm total
in excess of the b dimension at maximum material
condition. Dam bar cannot be located on the lower
radius or the lead foot.
Symbol
A
A1
A2
b
c
D
D1
D2
E
E1
E2
e
L
L1
R1
R2
S
θ
θ1
θ2
θ3
C
Dimension in Inch
minimal/maximal
- / 0.100
0.006 / 0.014
0.071 / 0.087
0.012 / 0.018
0.004 / 0.009
0.520 BSC
0.394 BSC
0.315
0.520 BSC
0.394 BSC
0.315
0.031 BSC
0.029 / 0.041
0.063
0.005 / 0.005 / 0.012
0.008 / 0° / 7°
0° / 10° REF
7° REF
0.004
Dimension in mm
minimal/maximal
- / 2.55
0.15 / 0.35
1.80 / 2.20
0.30 / 0.45
0.09 / 0.20
13.20 BSC
10.00 BSC
8.00
13.20 BSC
10.00 BSC
8.00
0.80 BSC
0.73 / 1.03
1.60
0.13 / 0.13 / 0.30
0.20 / as left
as left
as left
as left
0.10
Specifications subject to change without notice,contact your sales representatives for the most recent information.
30/32
Ver 1.0
PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
eMCU writer list
Company
Contact info
Tel:02-22182325
Fax:02-22182435
E-mail:
[email protected]
Programmer Model Number
LabTool - 48 (1 * 1)
LabTool - 848 (1*8)
Caprilion
P.O. Box 461 KaoHsiung, Taiwan,
ROC
Web site:
http://www.market.net.tw/ ~ cap/
Tel:07-3865061
Fax:07-3865421
E-mail:
[email protected]
UNIV2000
Hi-Lo
4F, No. 20, 22, LN, 76,
Rui Guang Rd., Nei Hu, Taipei,
Taiwan, ROC.
Web site:
http://www.hilosystems.com.tw
Tel:02-87923301
Fax:02-87923285
E-mail:
[email protected]
All - 11 (1*1)
Gang - 08 (1*8)
Leap
6th F1-4, Lane 609,
Chunghsin Rd., Sec. 5, Sanchung,
Taipei Hsien, Taiwan, ROC
Web site:
http://www.leap.com.tw
Tel:02-29991860
Fax:02-29990015
E-mail:
[email protected]
ChipStation (1*1)
SU - 2000 (1*8)
Xeltek Electronic Co., Ltd
338 Hongwu Road, Nanjing, China
210002
Web site:
http://www.xeltek-cn.com
Tel:+86-25-4408399, 4543153-206
E-mail:
[email protected],
[email protected]
Superpro/2000 (1*1)
Superpro/680 (1*1)
Superpro/280 (1*1)
Superpro/L+(1*1)
Advantech
7F, No.98, Ming-Chung Rd.,
Shin-Tien City, Taipei, Taiwan,
ROC
Web site:
http://www.aec.com.tw
Specifications subject to change without notice,contact your sales representatives for the most recent information.
31/32
Ver 1.0
PID 59264 05/02
SyncMOS Technologies Inc.
SM59264
May 2002
Feedback / Inquiry
To
: SyncMOS Technologies, Inc.
From
:
Company
:
Dept, Section
:
: 886-3-5792988
Position Title
:
: 886-3-5792926
Inquiry Date
:
Ref No
:
Attn : MKT / Customer Service Dept.
Fax : 886-3-5792960
: 886-3-5780493
Tel
Request customer logo as below:
Description:
Specifications subject to change without notice,contact your sales representatives for the most recent information.
32/32
Ver 1.0
PID 59264 05/02