Product Specification PE4230 SPDT High Power UltraCMOS™ RF Switch Product Description The PE4230 UltraCMOS™ RF Switch is designed to cover a broad range of applications from DC through 3000 MHz. This single-supply reflective switch integrates on-board CMOS control logic driven by a simple, single-pin CMOS or TTL compatible control input. Using a nominal +3-volt power supply, a typical input 1 dB compression point of +32 dBm can be achieved. The PE4230 also exhibits input-output isolation of better than 39 dB at 1000 MHz and is offered in a small 8-lead MSOP package. Features • Single 3-volt power supply • Low insertion loss: 0.35 dB at 1000 MHz, 0.55 dB at 2000 MHz • High isolation of 39 dB at 1000 MHz, 30 dB at 2000 MHz • Typical input 1 dB compression point of +32 dBm The PE4230 SPDT High Power UltraCMOS™ RF Switch is manufactured in Peregrine’s patented Ultra Thin Silicon (UTSi®) CMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Diagram • Single-pin CMOS or TTL logic control • Low cost Figure 2. Package Type 8-lead MSOP RFC RF1 RF2 CMOS Control Driver CTRL Table 1. Electrical Specifications @ +25 °C, VDD = 3 V (ZS = ZL = 50 Ω) Parameter Operation Frequency Conditions 1 Insertion Loss Isolation – RFC to RF1/RF2 Isolation – RF1 to RF2 Return Loss Minimum Typical DC Maximum Units 3000 MHz 1000 MHz 0.35 0.45 dB 2000 MHz 1000 MHz 0.65 38 0.55 39 dB dB 2000 MHz 1000 MHz 28 33.5 30 35 dB dB 2000 MHz 1000 MHz 26.5 23.5 28 25.5 dB dB 2000 MHz 14.5 15.4 dB ‘ON’ Switching Time CTRL to 0.1 dB final value, 2 GHz 200 ns ‘OFF’ Switching Time CTRL to 25 dB isolation, 2 GHz 90 ns 15 mVpp 32 dBm 2 Video Feedthrough Input 1 dB Compression 2000 MHz 30 Input IP3 2000 MHz, 17 dBm 50 dBm Notes: 1. Device linearity will begin to degrade below 10 MHz. 2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to High or High to Low in a 50 Ω test set-up, measured with 1ns risetime pulses and 500 MHz bandwidth. Document No. 70-0029-02 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 7 PE4230 Product Specification Table 4. Absolute Maximum Ratings Figure 3. Pin Configuration (Top View) Symbol VDD 1 8 RF1 VDD 2 7 GND GND RFC 3 6 4 5 GND Pin No. Pin Name 1 VDD 2 CTRL Description Nominal +3V supply connection. CMOS or TTL logic level: High = RFC to RF1 signal path 3 GND 4 RFC Low = RFC to RF2 signal path Ground connection. Traces should be physically short and connected to ground plane for best performance. Common RF port for switch.1 1 5 RF2 RF2 port. 6 GND 7 GND 8 RF1 Ground Connection. Traces should be physically short and connected to ground plane for best performance. Ground Connection. Traces should be physically short and connected to ground plane for best performance. RF1 port.1 Note 1: All RF pins must be DC blocked with an external series capacitor or held at 0 VDC. Table 3. DC Electrical Specifications Power supply voltage -0.3 4.0 V -0.3 VDD+ 0.3 V 5.0 V -65 150 °C TOP Operating temperature range -40 85 °C Input power (50Ω) 35 dBm ESD voltage (Human Body Model) 250 V VESD Table 2. Pin Descriptions Units Storage temperature range PIN RF2 Max TST VCTRL 4230 Min Voltage on any input except for the CTRL input VI CTRL Parameter/Conditions Voltage on CTRL input Absolute Maximum Ratings are those values listed in the above table. Exceeding these values may cause permanent device damage. Functional operation should be restricted to the limits in the DC Electrical Specifications table. Exposure to absolute maximum ratings for extended periods may affect device reliability. Table 5. Control Logic Truth Table Control Voltage Signal Path CTRL = CMOS or TTL High RFC to RF1 CTRL = CMOS or TTL Low RFC to RF2 The control logic input pin (CTRL) is typically driven by a 3-volt CMOS logic level signal, and has a threshold of 50% of VDD. For flexibility to support systems that have 5-volt control logic drivers, the control logic input has been designed to handle a 5-volt logic HIGH signal. (A minimal current will be sourced out of the VDD pin when the control logic input voltage level exceeds VDD.) Latch-Up Avoidance Parameter Min Typ Max Units VDD Power Supply Voltage 2.7 3.0 3.3 V Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. 29 35 µA Electrostatic Discharge (ESD) Precautions IDD Power Supply Current (VDD = 3V, VCNTL = 3V) Control Voltage High Control Voltage Low 0.7xVDD V 0.3xVDD ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 7 V When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 4. Document No. 70-0029-02 │ UltraCMOS™ RFIC Solutions PE4230 Product Specification Typical Performance Data @ 25 °C (Unless Otherwise Noted) Figure 4. Insertion Loss – RFC to RF1 T = -40 °C to 85 °C Figure 5. Input 1dB Compression Point 0 40 -40 8C -0.4 1dB Compression Point (dBm) Insertion Loss (dB) 25 8C 85 8C -0.8 -1.2 -1.6 -2 0 500 1000 1500 2000 2500 30 20 10 0 500 3000 1000 1500 Frequency (MHz) 2000 2500 3000 Frequency (MHz) Figure 6. Insertion Loss – RFC to RF2 T = -40 °C to 85 °C Figure 7. Isolation – RFC to RF1 0 0 -40 8C -0.4 -20 85 8C -0.8 Isolation (dB) Insertion Loss (dB) 25 8C -1.2 -1.6 -40 -60 -80 -2 0 500 1000 1500 2000 Frequency (MHz) Document No. 70-0029-02 │ www.psemi.com 2500 3000 -100 0 500 1000 1500 2000 2500 3000 Frequency (MHz) ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 7 PE4230 Product Specification Typical Performance Data @ 25°C Figure 8. Isolation – RFC to RF2 Figure 9. Isolation – RF1 to RF2, RF2 to RF1 0 0 -20 -20 -40 Isolation (dB) Isolation (dB) RF2 -60 -80 -40 RF1 -60 -80 -100 -100 0 500 1000 1500 2000 2500 0 500 Frequency (MHz) 1500 2000 2500 3000 Frequency (MHz) Figure 10. Return Loss – RFC Figure 11. Return Loss – RF1, RF2 0 0 -10 -10 Return Loss (dB) Return Loss (dB) 1000 -20 RF2 -20 RF1 -30 -30 -40 -40 0 500 1000 1500 2000 2500 Frequency (MHz) ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 7 3000 0 500 1000 1500 2000 2500 Frequency (MHz) Document No. 70-0029-02 │ UltraCMOS™ RFIC Solutions PE4230 Product Specification Evaluation Kit The SPDT Switch Evaluation Kit board was designed to ease customer evaluation of the PE4230 SPDT switch. The RF common port is connected through a 50 Ω transmission line to the top left SMA connector, J1. Port 1 and Port 2 are connected through 50 Ω transmission lines to the top two SMA connectors on the right side of the board, J3 and J4. A through transmission line connects SMA connectors J6 and J8. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. Figure 12. Evaluation Board Layouts Peregrine Specification 101/0037 The board is constructed of a two metal layer FR4 material with a total thickness of 0.031”. The bottom layer provides ground for the RF transmission lines. The transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 0.030”, trace gaps of 0.007”, dielectric thickness of 0.028”, metal thickness of 0.0014” and εr of 4.4. J2 provides a means for controlling DC and digital inputs to the device. Starting from the lower left pin, the second pin to the right (J2-3) is connected to the device CNTL input. The fourth pin to the right (J2-7) is connected to the device VDD input. A decoupling capacitor (100 pF) is provided on both CNTL and VDD traces. It is the responsibility of the customer to determine proper supply decoupling for their design application. Removing these components from the evaluation board has not been shown to degrade RF performance. Document No. 70-0029-02 │ www.psemi.com Figure 13. Evaluation Board Schematic Peregrine Specification 102/0035 ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 7 PE4230 Product Specification Figure 14. Package Drawing 8-lead MSOP TOP VIEW 0.65BSC .525BSC 7 8 6 12o REF 5 R 0.90 MIN 2.45±0.10 2X R 0.90 MIN GAGE PLANE 3.00±0.10 0o 0.25 6o 12o REF 0.55 ±0.15 0.51±0.13 -B- 1 0.51±0.13 2 3 4 .25 0.95 BSC A B C -C- 2.95±0.10 0.86±0.08 2.95±0.10 1.10 MAX -A0.10 A 0.33 0.08 +0.07 -0.08 0.10±0.05 3.00±0.10 4.90±0.15 A B C 3.00±0.10 FRONT VIEW SIDE VIEW Table 6. Ordering Information Order Code Part Marking Description Package 4230-21 4230 PE4230-08MSOP-50A 8-lead MSOP 50 units / Tube 4230-22 4230 PE4230-08MSOP-2000C 8-lead MSOP 2000 units / T&R 4230-00 PE4230-EK PE4230-08MSOP-EK Evaluation Kit 1 / Box 4230-51 4230 PE4230G-08MSOP-50A Green 8-lead MSOP 50 units / Tube 4230-52 4230 PE4230G-08MSOP-2000C Green 8-lead MSOP 2000 units / T&R ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 7 Shipping Method Document No. 70-0029-02 │ UltraCMOS™ RFIC Solutions PE4230 Product Specification Sales Offices The Americas North Asia Pacific Peregrine Semiconductor Corp. Peregrine Semiconductor K.K. 9450 Carroll Park Drive San Diego, CA 92121 Tel 858-731-9400 Fax 858-731-9499 5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Europe Peregrine Semiconductor Europe Commercial Products: Bâtiment Maine 13-15 rue des Quatre Vents F- 92380 Garches, France Tel: +33-1-47-41-91-73 Fax : +33-1-47-41-91-73 Space and Defense Products: 180 Rue Jean de Guiramand 13852 Aix-En-Provence cedex 3, France Tel: +33(0) 4 4239 3361 Fax: +33(0) 4 4239 7227 South Asia Pacific Peregrine Semiconductor 28G, Times Square, No. 500 Zhangyang Road, Shanghai, 200122, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Document No. 70-0029-02 │ www.psemi.com The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS is a trademark of Peregrine Semiconductor Corp. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 7