Product Specification PE4246 Absorptive SPST UltraCMOS™ RF Switch: DC - 5000 MHz Product Description The PE4246 RF Switch is designed to cover a broad range of applications from DC to 5000 MHz. It is non-reflective at both RF1 and RF2 ports. This SPST switch integrates a single-pin CMOS control interface, and provides low insertion loss while operating with extremely low bias from a single +3-volt supply. In a typical application, the high isolation PE4246 can replace multiple RF switches of lesser isolation performance. It is offered in a small 3x3 mm DFN package. The PE4246 is manufactured on Peregrine’s UltraCMOS™ process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Diagram Features • Non-reflective 50-ohm RF switch • 50-ohm (0.25 watt) terminations • High isolation: 55 dB at 1000 MHz, 48 dB at 3000 MHz • Low insertion loss: 0.8 dB at 1000 MHz, 0.9 dB at 3000 MHz • High linearity: +33 dBm input 1dB compression point • CMOS/TTL single-pin control • Single +3-volt supply operation • Extremely low bias: 33 µA @ 3 V • Available in a 6-lead DFN package Figure 2. Package Type RF1 6-lead DFN RF2 50 CMOS Control Driver 50 CTRL Table 1. Electrical Specifications @ +25 °C, VDD = 3 V (ZS = ZL = 50 Ω) Parameter Condition 1 Operation Frequency Minimum Typical DC Maximum Units 5000 MHz 30/24 dBm 1.0 1.1 1.3 1.8 dB dB dB dB Operating Power CTRL=1/CTRL=0 Insertion Loss DC-2000 MHz 2000-3000 MHz 3000-4000 MHz 4000-5000 MHz Isolation DC-2000 MHz 2000-3000 MHz 3000-4000 MHz 4000-5000 MHz 49 45 43 40 55 48 46 44 Return Loss DC-5000 MHz 11 20 dB Input 1 dB Compression3 DC-5000 MHz 30 33 dBm Input IP3 DC-5000 MHz 50 0.8 0.9 1.0 1.3 dBm Video Feedthrough2 Switching Time dB dB dB dB 15 2 mVpp µs Notes: 1. Device linearity will begin to degrade below 1 MHz. 2. The DC transient at the output of the switch when the control voltage is switched from Low to High or High to Low in a 50 Ω test set-up, measured with 1ns risetime pulses and 500 MHz bandwidth. 3. Note Absolute Maximum ratings in Table 3. Document No. 70-0090-05 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 8 PE4246 Product Specification Figure 3. Pin Configuration VDD 1 GND 2 Exposed Solder Pad Device Description 6 RF2 5 GND 4 CTRL The PE4246 high-isolation SPST RF Switch is designed to support a variety of applications where high isolation performance is demanded and a non-reflective input and output is desired. This switch is able to replace multiple lesser performing switches in a very small 3x3 mm DFN footprint. (bottom side) 3 RF1 Table 4. DC Electrical Specifications Table 2. Pin Descriptions Pin No. Pin Name 1 VDD 2 GND Ground connection. 3 3 RF1 RF port. 2 4 CTRL CMOS or TTL logic level: High = RF1 to RF2 signal path Low = RF1 isolated from RF2 5 GND Ground connection. 6 Description Min Max Unit Power supply voltage -0.3 4.0 V Voltage on CTRL input -0.3 5.5 V TST Storage temperature -65 150 °C TOP Operating temperature -40 85 °C PIN Input power (50 Ω), CTRL=1/CTRL=0 33/24 dBm 200 V VI VESD ESD voltage (Human Body Model) Absolute Maximum Ratings are those values listed in the above table. Exceeding these values may cause permanent device damage. Functional operation should be restricted to the limits in the DC Electrical Specifications table. Exposure to absolute maximum ratings for extended periods may affect device reliability. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 8 Unit VDD Power Supply 2.7 3.0 3.3 V 33 40 µA Control Voltage High 0.7xVDD 5 V Control Voltage Low 0 0.3xVDD V Control Voltage 3 Table 3. Absolute Maximum Ratings VDD Max Table 5. Control Logic Truth Table RF port. 2 Parameter/Condition Typ (VDD = 3 V, VCNTL = 3 V) Notes: 1. A bypass capacitor should be placed as close as possible to the pin. 2. Both RF pins must be DC blocked by an external capacitor or held at 0 VDC. 3. The exposed pad must be soldered to the ground plane for proper switch performance. Symbol Min IDD Power Supply Current Nominal 3 V supply connection.1 RF2 Parameter Signal Path CTRL = CMOS or TTL High RF1 to RF2 CTRL = CMOS or TTL Low RF1 isolated from RF2 Control Logic The control logic input pin (CTRL) is typically driven by a 3-volt CMOS logic level signal, and has a threshold of 50% of VDD. For flexibility to support systems that have 5-volt control logic drivers, the control logic input has been designed to handle a 5-volt logic HIGH signal. (A minimal current will be sourced out of the VDD pin when the control logic input voltage level exceeds VDD.) Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 3. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Document No. 70-0090-05 │ UltraCMOS™ RFIC Solutions PE4246 Product Specification Typical Performance Data @ 25 °C (Unless Otherwise Noted) Figure 4. Insertion Loss Figure 5. Input 1dB Compression Point and IIP3 T = -40 °C to 85 °C 0 60 60 -40 C -0.5 -1 85 C -1.5 IIP3 (dBm) Insertion Loss (dB) 50 IIP3 25 C 40 40 -2 30 -3 0 1000 2000 3000 4000 5000 Frequency (MHz) 30 Input 1dB Compression -2.5 20 0 1000 2000 3000 4000 1dB Compression Point (dBm) 50 20 5000 Frequency (MHz) Figure 6. Isolation 0 Isolation (dB) -20 -40 -60 -80 -100 0 1000 2000 3000 4000 5000 Frequency (MHz) Document No. 70-0090-05 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 8 PE4246 Product Specification Typical Performance Data @ +25 °C Figure 8. RF2 Return Loss (CTRL = High) 0 0 -5 -5 -10 -10 Return Loss (dB) Return Loss (dB) Figure 7. RF1 Return Loss (CTRL = High) -15 -15 -20 -20 -25 -25 -30 -30 0 1000 2000 3000 4000 5000 0 1000 Frequency (MHz) 3000 4000 5000 Frequency (MHz) Figure 9. RF1 Return Loss (CTRL = Low) Figure 10. RF2 Return Loss (CTRL = Low) 0 0 -5 -5 -10 -10 Return Loss (dB) Return Loss (dB) 2000 -15 -20 -15 -20 -25 -25 -30 -30 -35 -35 0 1000 2000 3000 4000 Frequency (MHz) ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 8 5000 0 1000 2000 3000 4000 5000 Frequency (MHz) Document No. 70-0090-05 │ UltraCMOS™ RFIC Solutions PE4246 Product Specification Evaluation Kit Figure 11. Evaluation Board Layouts Peregrine Specification 101/0102 The SPST Switch Evaluation Kit board was designed to ease customer evaluation of the PE4246 SPST switch. The RF1 port is connected through a 50 Ω transmission line to the top left SMA connector, J1. The RF2 port is connected through a 50 Ω transmission line to the top right SMA connector, J2. A through transmission line connects SMA connectors J3 and J4. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. The board is constructed of a two metal layer FR4 material with a total thickness of 0.031”. The bottom layer provides ground for the RF transmission lines. The transmission lines were designed using a coplanar waveguide model with trace width of 0.0476”, trace gaps of 0.030”, dielectric thickness of 0.028”, metal thickness of 0.0021” and εR of 4.3. Note that the predominate mode for these transmission lines is coplanar waveguide with a ground plane. J5 and J6 provide a means for controlling DC and digital inputs to the device. J6-1 is connected to the device VDD input. J5-1 is connected to the device CTRL input. J5-2 and J6-2 are GND connections. A decoupling capacitor (100 pF) is provided on both CTRL and VDD traces. It is the responsibility of the customer to determine proper supply decoupling for their design application. Removing these components from the evaluation board has not been shown to degrade RF performance. Document No. 70-0090-05 │ www.psemi.com Figure 12. Evaluation Board Schematic Peregrine Specification 102/0134 ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 8 PE4246 Product Specification Figure 13. Package Drawing 6-lead DFN -A- 3.00 6 5 CL -B4 0.125 CL 3.00 PIN MAR 1 K 0.10 C 4 1 2 3 0.10 C 4 0.125 10°+2° -10° TOP VIEW DETAIL C 0.025 ±0.025 0.100 C 0.70 ± 0.05 0.90 ±0.10 0.20 ±0.05 SEATING PLANE 0.080 C 3 SIDE VIEW SEE DETAIL B 0.025±0.025 CL +0.08 -0.02 0.10 0.05 C 0.95 0.17 MIN. 0.24 +0.20 -0.08 0.35 EXPOSED PAD 1 DETAIL B -C- 2 C A B 0.29 3 SEE DETAIL A +0.21 -0.08 0.125 EXPOSED SLUG/ HEAT SINK 0.17 0.30 R0.127 TYP R 0.15 TYP 1.21 ±0.10 0.605 ±0.05 EXPOSED (2X) 6 5 3 4 .20 MIN. THIS FEATURE APPLIES TO BOTH ENDS OF THE PKG. EXPOSED METALIZED FEATURE DETAIL A EDGE OF PLASTIC BODY 1.05±0.05 2.01±0.10 BOTTOM VIEW 1. DIMENSIONS AND TOLERANCES ARE PER ANSi Y14.5 2. DIMENSIONS ARE IN MILLIMETERS, ANGLES ARE IN DEGREES. 3 COPLANARITY APPLIES TO EXPOSED HEAT SLUG AS WELL AS THE TERMINALS. 4 PROFILE TOLERANCE APPLIES TO PLASTIC BODY ONLY. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 8 Document No. 70-0090-05 │ UltraCMOS™ RFIC Solutions PE4246 Product Specification Figure 14. Tape and Reel Specifications 6-lead DFN Table 6. Dimensions Dimension DFN 3x3mm Ao 3.23 ± 0.1 Bo 3.17 ± 0.1 Ko 1.37 ± 0.1 P 4 ± 0.1 W 8 +0.3, -0.1 T 0.254 ± 0.02 R7 Quantity 3000 R13 Quantity N.A. Note: R7 = 7 inch Lock Reel, R13 = 13 inch Lock Reel Table 7. Ordering Information Order Code Part Marking Description Package Shipping Method 4246-01 4246 PE4246-06DFN 3x3mm-12800F 6-lead 3x3 mm DFN 12800 units / Canister 4246-02 4246 PE4246-06DFN 3x3mm-3000C 6-lead 3x3 mm DFN 3000 units / T&R 4246-00 PE4246-EK PE4246-06DFN 3x3mm-EK Evaluation Kit 1 / Box 4246-51 4246 PE4246G-06DFN 3x3mm-12800F Green 6-lead 3x3 mm DFN 12800 units / Canister 4246-52 4246 PE4246G-06DFN 3x3mm-3000C Green 6-lead 3x3 mm DFN 3000 units / T&R ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 8 Document No. 70-0090-05 │ UltraCMOS™ RFIC Solutions PE4246 Product Specification Sales Offices The Americas North Asia Pacific Peregrine Semiconductor Corp. Peregrine Semiconductor K.K. 9450 Carroll Park Drive San Diego, CA 92121 Tel 858-731-9400 Fax 858-731-9499 5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Europe Peregrine Semiconductor Europe Commercial Products: Bâtiment Maine 13-15 rue des Quatre Vents F- 92380 Garches, France Tel: +33-1-47-41-91-73 Fax : +33-1-47-41-91-73 Space and Defense Products: 180 Rue Jean de Guiramand 13852 Aix-En-Provence cedex 3, France Tel: +33(0) 4 4239 3361 Fax: +33(0) 4 4239 7227 South Asia Pacific Peregrine Semiconductor 28G, Times Square, No. 500 Zhangyang Road, Shanghai, 200122, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Document No. 70-0090-05 │ www.psemi.com The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS is a trademark of Peregrine Semiconductor Corp. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 8