Product Specification PE9354 SPDT High Power UltraCMOS™ RF Switch Rad hard for Space Applications Product Description The PE9354 SPDT High Power UltraCMOS™ RF Switch is designed to cover a broad range of applications from near DC to 3000 MHz. This single-supply reflective switch integrates onboard CMOS control logic driven by a simple, single-pin CMOS and TTL compatible control input. Using a nominal +3-volt power supply, a typical input 1 dB compression point of +31 dBm can be achieved. The PE9354 also exhibits input-output isolation of better than 30 dB at 2000 MHz and is offered in a small 8-lead ceramic SOIC package. The PE9354 is optimized for commercial space applications. Single Event Latch up (SEL) is physically impossible and Single Event Upset (SEU) is better than 10-9 errors per bit/day. Fabricated in Peregrine’s UltraCMOS™ technology, the PE9354 offers excellent RF performance and intrinsic radiation tolerance. Figure 1. Functional Schematic Diagram Features • Single 3-volt power supply • Low insertion loss: 0.55 dB at 2000 MHz • High isolation of 30 dB at 2000 MHz • Typical input 1 dB compression point of +31 dBm • 100 Krad total dose • Single-pin CMOS or TTL logic control • Low cost Figure 2. Package Type 8-lead CSOIC RFC RF1 RF2 CMOS Control Driver CTRL Table 1. A/C Electrical Specifications -55 °C to +125 °C, VDD = 3.0 V (ZS = ZL = 50 Ω) Parameter Operation Frequency Conditions 1 Minimum Typical DC Units 3000 MHz 0.80 dB Insertion Loss 2000 MHz Isolation – RFC to RF1/RF2 2000 MHz 28 32 dB Isolation – RF1 to RF2 2000 MHz 24 28 dB 22 dB 31 dBm 2 2000 MHz Input 1 dB Compression 2000 MHz Return Loss 0.55 Maximum 28 Note: 1. Device linearity will begin to degrade below 10 MHz. Note: 2. Return loss not measured in production due to equipment limitations Document No. 70-0099-02 │ www.psemi.com ©2004-2006 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 7 PE9354 Product Specification Figure 3. Pin Configuration Table 3. Absolute Maximum Ratings Symbol VDD 1 CTRL 2 8 RF1 VDD 7 GND 6 GND VI PE9354 3 GND 4 RFC VCTRL 5 RF2 Pin Name 1 VDD 2 CTRL CMOS or TTL logic level: High = RFC to RF1 signal path Low = RFC to RF2 signal path 3 GND Ground connection. Traces should be physically short and connected to ground plane for best performance. 4 RFC Common RF port for switch.1 5 RF2 RF2 port.1 6 GND Ground Connection. Traces should be physically short and connected to ground plane for best performance. 7 GND Ground Connection. Traces should be physically short and connected to ground plane for best performance. 8 RF1 RF1 port.1 Description Nominal +3V supply connection. Units Power supply voltage -0.3 4.0 V Voltage on any input except for the CTRL input -0.3 VDD+ 0.3 V Voltage on CTRL input 5.0 V -65 150 °C TOP Operating temperature range -55 125 °C PIN Input power (50 Ω) 32 dBm ESD voltage (Human Body Model) Total Cumulative Exposure to Ionizing Radiation 200 V 100k Rads (Si) Absolute Maximum Ratings are those values listed in the above table. Exceeding these values may cause permanent device damage. Functional operation should be restricted to the limits in the DC Electrical Specifications table. Exposure to absolute maximum ratings for extended periods may affect device reliability. Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 3. Latch-Up Avoidance Note 1: All RF pins must be DC blocked with an external series capacitor or held at 0 VDC. Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Table 4. DC Electrical Specifications Parameter Max Storage temperature range Total Dose Pin No. Min TST VESD Table 2. Pin Descriptions Parameter/Conditions Table 5. Control Logic Truth Table Min Typ Max Units VDD Power Supply Voltage 2.7 3.0 3.3 V Input Leakage -1 1 µA 100 µA Control Voltage Signal Path CTRL = CMOS or TTL High RFC to RF1 CTRL = CMOS or TTL Low RFC to RF2 V The control logic input pin (CTRL) is typically driven by a 3-volt CMOS logic level signal, and has a threshold of 50% of VDD. For flexibility to support systems that have 5-volt control logic drivers, the control logic input has been designed to handle a 5-volt logic HIGH signal. (A minimal current will be sourced out of the VDD pin when the control logic input voltage level exceeds VDD.) ©2004-2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0099-02 │ UltraCMOS™ RFIC Solutions IDD Power Supply Current (VDD = 3V, VCNTL = 3V) Control Voltage High Control Voltage Low Page 2 of 7 28 V 0.7xVDD 0.3xVDD PE9354 Product Specification Typical Performance Data @ -55 °C to 125 °C Figure 4. Insertion Loss – RFC to RF1 Figure 5. Input 1dB Compression Point Figure 6. Insertion Loss – RFC to RF2 Figure 7. Isolation – RFC to RF1 Document No. 70-0099-02 │ www.psemi.com ©2004-2006 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 7 PE9354 Product Specification Typical Performance Data @ -55 °C to 125 °C Figure 8. Isolation – RFC to RF2 Figure 9. Isolation – RF1/RF2 to RF2/RF1 Figure 10. Return Loss – RFC Figure 11. Return Loss – RF1, RF2 ©2004-2006 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 7 Document No. 70-0099-02 │ UltraCMOS™ RFIC Solutions PE9354 Product Specification Evaluation Kit Information Figure 12. Evaluation Board Layouts Evaluation Kit The SPDT Switch Evaluation Kit board was designed to ease customer evaluation of the PE9354 SPDT switch. The RF common port is connected through a 50 Ω transmission line to the top left SMA connector, J1. Port 1 and Port 2 are connected through 50 Ω transmission lines to the top two SMA connectors on the right side of the board, J2 and J3. A through transmission line connects SMA connectors J4 and J5. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. The board is constructed of a two metal layer FR4 material with a total thickness of 0.031”. The bottom layer provides ground for the RF transmission lines. The transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 0.030”, trace gaps of 0.007”, dielectric thickness of 0.028”, metal thickness of 0.0014” and εr of 4.4. J6 provides a means for controlling DC and digital inputs to the device. Starting from the lower left pin, the second pin to the right (J2-3) is connected to the device CNTL input. The fourth pin to the right (J2-7) is connected to the device VDD input. A decoupling capacitor (100 pF) is provided on both CTRL and VDD traces. It is the responsibility of the customer to determine proper supply decoupling for their design application. Removing these components from the evaluation board has not been shown to degrade RF performance. The ground plane has been removed from beneath the device for performance issues. It was found that insertion loss dips (suck-outs) were experienced due to the capacitive effect of the metal package sitting insulated by the solder-mask on the ground plane. All Document No. 70-0099-02 │ www.psemi.com data specified and shown on this datasheet was taken using this evaluation board configuration. For optimal performance, the package may be soldered directly to the ground plane, but the reliability issues associated with this mounting must be addressed by the customer. Figure 13. Evaluation Board Schematic Peregrine specification 102/0129 ©2004-2006 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 7 PE9354 Product Specification Figure 14. Package Drawing 8-lead CSOIC .380 / .410 .210 / .250 Pin 1 .180 SQ MAX .050 TYP .150 TYP TOP VIEW .015 TYP SIDE VIEW .005 Typ .070 Max ALL DIMENSIONS ARE IN INCHES Table 6. Ordering Information Order Code Part Marking Description Package Shipping Method 9354-01 PE9354 ES Engineering Samples 8-lead Ceramic SOIC 50 units / Tray 9354-11 PE9354 Flight Units 8-lead Ceramic SOIC 50 units / Tray 9354-00 PE9354-EK PE9354 Evaluation Kit Evaluation Kit 1 / Box ©2004-2006 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 7 Document No. 70-0099-02 │ UltraCMOS™ RFIC Solutions PE9354 Product Specification Sales Offices The Americas North Asia Pacific Peregrine Semiconductor Corporation Peregrine Semiconductor K.K. 9450 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Europe Peregrine Semiconductor, Korea Peregrine Semiconductor Europe #B-2402, Kolon Tripolis, #210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-480 S. Korea Tel: +82-31-728-4300 Fax: +82-31-728-4305 Bâtiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France Tel: +33-1-47-41-91-73 Fax : +33-1-47-41-91-73 South Asia Pacific Space and Defense Products Peregrine Semiconductor, China Americas: Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Tel: 858-731-9453 Europe, Asia Pacific: 180 Rue Jean de Guiramand 13852 Aix-En-Provence Cedex 3, France Tel: +33(0) 4 4239 3361 Fax: +33(0) 4 4239 7227 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Document No. 70-0099-02 │ www.psemi.com The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp. ©2004-2006 Peregrine Semiconductor Corp. All rights reserved. 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