MC74LVX139 Dual 2−to−4 Decoder/ Demultiplexer The MC74LVX139 is an advanced high speed CMOS 2−to−4 decoder/ demultiplexer fabricated with silicon gate CMOS technology. When the device is enabled (E = low), it can be used for gating or as a data input for demultiplexing operations. When the enable input is held high, all four outputs are fixed high, independent of other inputs. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. http://onsemi.com MARKING DIAGRAMS Features • • • • • • • • • • • • 16 High Speed: tPD = 6.0 ns (Typ) at VCC = 3.3 V SOIC−16 D SUFFIX CASE 751B Low Power Dissipation: ICC = 4 Α (Max) at TA = 25°C High Noise Immunity: VNIH = VNIL = 28% VCC LVX139 AWLYWW 1 Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 V to 3.6 V Operating Range 16 Low Noise: VOLP = 0.5 V (Max) Pin and Function Compatible with Other Standard Logic Families LVX 139 ALYW TSSOP−16 DT SUFFIX CASE 948F 1 Latchup Performance Exceeds 300 mA Chip Complexity: 100 FETs or 25 Equivalent Gates ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Pb−Free Packages are Available* 16 SOEIAJ−16 M SUFFIX CASE 966 LVX139 ALYW 1 A WL or L Y WW or W = = = = Assembly Location Wafer Lot Year Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2005 March, 2005 − Rev. 2 1 Publication Order Number: MC74LVX139/D MC74LVX139 Ea 1 16 VCC A0a 2 15 Eb A1a 3 14 A0b Y0a 4 13 FUNCTION TABLE Inputs A1b Y1a 5 12 Y0b Y2a 6 11 Y1b Y3a 7 10 Y2b GND 8 9 Y3b Outputs E A1 A0 Y0 Y1 Y2 Y3 H L L L L X L L H H X L H L H H L H H H H H L H H H H H H L H H H L H Figure 1. Pin Assignment ADDRESS INPUTS A0a A1a 2 4 3 5 6 7 Ea ADDRESS INPUTS A0b A1b Y1a ACTIVE−LOW OUTPUTS Y2a Y3a 1 14 12 13 11 10 9 Eb Y0a Y0b Y1b Y2b ACTIVE−LOW OUTPUTS Y3b 15 Figure 2. Logic Diagram En Y0 Y1 A0 Y2 Y3 A1 Figure 3. Expanded Logic Diagram (1/2 of Device) http://onsemi.com 2 MC74LVX139 A1a 3 A0a 2 Ea 1 X/Y 1 0 2 1 EN 2 4 Y0a A1a 3 5 Y1a A0a 2 6 Y2a Ea 1 7 Y3a 3 0 1 DMUX 0 0 G 3 1 2 3 12 Y0b A1b 13 A0b 14 4 Y0a 5 Y1a 6 Y2a 7 Y3a 12 Y0b 11 Y1b A1b 13 10 Y2b A0b 14 10 Y2b Eb 15 9 Y3b Eb 15 9 Y3b INPUT 11 Y1b Figure 4. IEC Logic Diagram Figure 5. Input Equivalent Circuit MAXIMUM RATINGS Symbol Value Unit VCC Positive DC Supply Voltage −0.5 to +7.0 V VIN Digital Input Voltage −0.5 to +7.0 V VOUT DC Output Voltage −0.5 to VCC +0.5 V IIK Input Diode Current −20 mA IOK Output Diode Current 20 mA IOUT DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 75 mA PD Power Dissipation in Still Air 200 180 mW TSTG Storage Temperature Range −65 to +150 °C VESD ESD Withstand Voltage Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) >2000 >200 >2000 V Above VCC and Below GND at 125°C (Note 4) 300 mA 143 164 °C/W ILATCHU Parameter SOIC Package TSSOP Latchup Performance P JA Thermal Resistance, Junction−to−Ambient SOIC Package TSSOP Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Tested to EIA/JESD22−A114−A 2. Tested to EIA/JESD22−A115−A 3. Tested to JESD22−C101−A 4. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONS Symbol Characteristics VCC DC Supply Voltage VIN DC Input Voltage VOUT DC Output Voltage Output in 3−State High or Low State TA Operating Temperature Range, all Package Types tr, tf Input Rise or Fall Time VCC = 5.0 V + 0.5 V http://onsemi.com 3 Min Max Unit 2.0 3.6 V 0 5.5 V 0 VCC V −40 85 °C 0 100 ns/V MC74LVX139 DC CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Condition −40°C ≤ TA ≤ 85°C TA = 25°C (V) Min Typ Max Min Max Unit VIH Minimum High−Level Input Voltage 2.0 3.0 3.6 0.75 VCC 0.7 VCC 0.7 VCC − − − − − − 0.75 VCC 0.7 VCC 0.7 VCC − − − V VIL Maximum Low−Level Input Voltage 2.0 3.0 3.6 − − − − − − 0.25 VCC 0.3 VCC 0.3 VCC − − − 0.25 VCC 0.3 VCC 0.3 VCC V VOH High−Level Output Voltage IOH = −50 A IOH = −50 A IOH = −4 mA 2.0 3.0 3.0 1.9 2.9 2.58 2.0 3.0 3.0 − − − 1.9 2.9 2.48 − − − V VOL Low−Level Output Voltage IOL = 50 A IOH = 50 A IOH = 4 mA 2.0 3.0 3.0 − − − 0.0 0.1 0.1 0.36 − − − 0.1 0.1 0.44 V IIN Input Leakage Current VIN = 5.5 V or GND 0 to 3.6 − − ±0.1 − ±1.0 A ICC Maximum Quiescent Supply Current (per package) VIN = VCC or GND 3.6 1.0 1.0 2.0 − − A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns −40°C ≤ TA ≤ 85°C TA = 25°C Symbol tPLH, tPHL tPLH, tPHL CIN Parameter Maximum Propagation Delay, A to Y Maximum Propagation Delay, E to Y Test Conditions Min Typ Max Min Max Unit ns VCC = 2.7 V CL = 15 pF CL = 50 pF − − 8.5 11.0 15.0 16.5 1.0 1.0 17.8 18.0 VCC = 3.3 V ± 0.3 V CL = 15 pF CL = 50 pF − − 6.0 8.5 10.0 13.0 1.0 1.0 12.0 15.0 VCC = 2.7 V CL = 15 pF CL = 50 pF − − 8.0 10.0 13.0 16.5 1.0 1.0 15.5 18.0 VCC = 3.3 V ± 0.3 V CL = 15 pF CL = 50 pF − − 5.5 7.5 8.2 13.0 1.0 1.0 10.0 15.0 − 4 10 − 10 Maximum Input Capacitance ns pF Typical @ 25°C, VCC = 3.3 V CPD 26 Power Dissipation Capacitance (Note 5) pF 5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC/2 (per decoder). CPD is used to determine the no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. VCC A VCC E 50% 50% GND tPHL tPLH Y GND tPHL 50% VCC Y Figure 6. Switching Waveform tPLH 50% VCC Figure 7. Switching Waveform http://onsemi.com 4 MC74LVX139 TEST POINT OUTPUT DEVICE UNDER TEST CL * *Includes all probe and jig capacitance Figure 8. Test Circuit ORDERING INFORMATION Package Shipping† MC74LVX139DR2 SOIC−16 2500 Tape & Reel MC74LVX139DR2G SOIC−16 (Pb−Free) 2500 Tape & Reel MC74LVX139DTR2 TSSOP−16* 2500 Tape & Reel MC74LVX139M SOEIAJ−16 50 Units / Rail MC74LVX139MG SOEIAJ−16 (Pb−Free) 50 Units / Rail MC74LVX139MEL SOEIAJ−16 2000 Tape & Reel MC74LVX139MELG SOEIAJ−16 (Pb−Free) 2000 Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. EMBOSSED CARRIER DIMENSIONS (See Notes 6 and 7) Tape Size B1 Max 8 mm 4.35 mm (0.179”) 12 mm 8.2 mm (0.323”) 16 mm 24 mm D D1 E F K P P0 P2 R T W 1.5 mm + 0.1 −0.0 (0.059” ( 0 004 +0.004 −0.0) 1.0 mm Min (0.179”) 1.75 mm ±0.1 (0.069 ±0.004”)) 3.5 mm ±0.5 (1.38 ±0.002”) 2.4 mm Max (0.094”) 4.0 mm ±0.10 (0.157 ±0.004”) 4.0 mm ±0.1 (0.157 ±0.004”)) 2.0 mm ±0.1 (0.079 ±0.004”)) 25 mm (0.98”) 0.6 mm (0.024) 8.3 mm (0.327) 5.5 mm ±0.5 (0.217 ±0.002”) 6.4 mm Max (0.252”) 4.0 mm ±0.10 (0.157 ±0.004”) 8.0 mm ±0.10 (0.315 ±0.004”) 12.1 mm (0.476”) 7.5 mm ±0.10 (0.295 ±0.004”) 7.9 mm Max (0.311”) 4.0 mm ±0.10 (0.157 ±0.004”) 8.0 mm ±0.10 (0.315 ±0.004”) 12.0 mm ±0.10 (0.472 ±0.004”) 16.3 mm (0.642) 20.1 mm (0.791”) 11.5 mm ±0.10 (0.453 ±0.004”) 11.9 mm Max (0.468”) 16.0 mm ±0.10 (0.63 ±0.004”) 24.3 mm (0.957) 1.5 mm Min (0.060) 30 mm (1.18”) 12.0 mm ±0.3 (0.470 ±0.012”) 6. Metric Dimensions Govern−English are in parentheses for reference only. 7. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. The component cannot rotate more than 10° within the determined cavity http://onsemi.com 5 MC74LVX139 PACKAGE DIMENSIONS SOIC−16 D SUFFIX CASE 751B−05 ISSUE J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 16 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K DIM A B C D F G J K M P R F X 45 C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 S TSSOP−16 DT SUFFIX CASE 948F−01 ISSUE A 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. 8 1 N 0.15 (0.006) T U S 0.25 (0.010) A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. M N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE H D DETAIL E G http://onsemi.com 6 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 MC74LVX139 SOEIAJ−16 M SUFFIX CASE 966−01 ISSUE O 16 LE 9 Q1 M E HE 1 8 L DETAIL P Z D e VIEW P A DIM A A1 b c D E e HE L LE M Q1 Z A1 b 0.13 (0.005) c M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). 0.10 (0.004) http://onsemi.com 7 MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 0 0.70 0.90 −−− 0.78 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 0 0.028 0.035 −−− 0.031 MC74LVX139 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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