XILINX XCV405E

0
Virtex™-E 1.8 V Extended Memory
Field Programmable Gate Arrays
R
DS025-1 (v1.5) July 17, 2002
0
0
Production Product Specification
Features
•
•
•
•
Fast, Extended Block RAM, 1.8 V FPGA Family
- 560 Kb and 1,120 Kb embedded block RAM
- 130 MHz internal performance (four LUT levels)
- PCI compliant 3.3 V, 32/64-bit, 33/66-MHz
Sophisticated SelectRAM+™ Memory Hierarchy
- 294 Kb of internal configurable distributed RAM
- Up to 1,120 Kb of synchronous internal block RAM
- True Dual-Port block RAM
- Memory bandwidth up to 2.24 Tb/s (equivalent
bandwidth of over 100 RAMBUS channels)
- Designed for high-performance Interfaces to
external memories
·
200 MHz ZBT* SRAMs
·
200 Mb/s DDR SDRAMs
Highly Flexible SelectIO+™ Technology
- Supports 20 high-performance interface standards
- Up to 556 singled-ended I/Os or up to 201
differential I/O pairs for an aggregate bandwidth of
>100 Gb/s
Complete Industry-Standard Differential Signalling
Support
- LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL
- Al I/O signals can be input, output, or bi-directional
•
•
•
•
•
•
•
•
LVPECL and LVDS clock inputs for 300+ MHz
clocks
Proprietary High-Performance SelectLink™
Technology
- 80 Gb/s chip-to-chip communication link
- Support for Double Data Rate (DDR) interface
- Web-based HDL generation methodology
Eight Fully Digital Delay-Locked Loops (DLLs)
IEEE 1149.1 boundary-scan logic
Supported by Xilinx Foundation Series™ and Alliance
Series™ Development Systems
- Internet Team Design (Xilinx iTD™) tool ideal for
million-plus gate density designs
- Wide selection of PC or workstation platforms
SRAM-based In-System Configuration
- Unlimited re-programmability
Advanced Packaging Options
- 1.0 mm FG676 and FG900
- 1.27 mm BG560
0.18 µm 6-layer Metal Process with Copper
Interconnect
100% Factory Tested
* ZBT is a trademark of Integrated Device Technology, Inc.
Introduction
The Virtex™-E Extended Memory (Virtex-EM) family of
FPGAs is an extension of the highly successful Virtex-E
family architecture. The Virtex-EM family (devices shown in
Table 1) includes all of the features of Virtex-E, plus additional block RAM, useful for applications such as network
switches and high-performance video graphic systems.
Xilinx developed the Virtex-EM product family to enable
customers to design systems requiring high memory bandwidth, such as 160 Gb/s network switches. Unlike traditional
ASIC devices, this family also supports fast time-to-market
delivery, because the development engineering is already
completed. Just complete the design and program the
device. There is no NRE, no silicon production cycles, and no
additional delays for design re-work. In addition, designers
can update the design over a network at any time, providing
product upgrades or updates to customers even sooner.
ing customer applications by providing the highest level of
logic, RAM, and features available in the industry. The Virtex-EM family, first FPGAs to deploy copper interconnect,
offers the performance and high memory bandwidth for
advanced system integration without the initial investment,
long development cycles, and inventory risk expected in traditional ASIC development.
The Virtex-EM family is the result of more than fifteen years
of FPGA design experience. Xilinx has a history of support-
© 2000-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS025-1 (v1.5) July 17, 2002
Production Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
1
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 1: Virtex-E Extended Memory Field-Programmable Gate Array Family Members
Device
Logic Gates
CLB Array
Logic
Cells
Differential
I/O Pairs
User I/O
BlockRAM
Bits
Distributed
RAM Bits
XCV405E
129,600
40 x 60
10,800
183
404
573,440
153,600
XCV812E
254,016
56 x 84
21,168
201
556
1,146,880
301,056
Virtex-E Compared to Virtex Devices
The Virtex-E family offers up to 43,200 logic cells in devices
up to 30% faster than the Virtex family.
I/O performance is increased to 622 Mb/s using Source
Synchronous data transmission architectures and synchronous system performance up to 240 MHz using singled-ended SelectI/O technology. Additional I/O standards
are supported, notably LVPECL, LVDS, and BLVDS, which
use two pins per signal. Almost all signal pins can be used
for these new standards.
Virtex-E devices have up to 640 Kb of faster (250MHz)
block SelectRAM, but the individual RAMs are the same
size and structure as in the Virtex family. They also have
eight DLLs instead of the four in Virtex devices. Each individual DLL is slightly improved with easier clock mirroring
and 4x frequency multiplication.
VCCINT, the supply voltage for the internal logic and memory, is 1.8 V, instead of 2.5 V for Virtex devices. Advanced
processing and 0.18 µm design rules have resulted in
smaller dice, faster speed, and lower power consumption.
I/O pins are 3 V tolerant, and can be 5 V tolerant with an
external 100 Ω resistor. PCI 5 V is not supported. With the
addition of appropriate external resistors, any pin can tolerate any voltage desired.
Banking rules are different. With Virtex devices, all input
buffers are powered by VCCINT. With Virtex-E devices, the
LVTTL, LVCMOS2, and PCI input buffers are powered by
the I/O supply voltage VCCO.
The Virtex-E family is not bitstream-compatible with the Virtex family, but Virtex designs can be compiled into equivalent Virtex-E devices.
The same device in the same package for the Virtex-E and
Virtex families are pin-compatible with some minor exceptions. See the data sheet pinout section for details.
General Description
The Virtex-E FPGA family delivers high-performance,
high-capacity programmable logic solutions. Dramatic
increases in silicon efficiency result from optimizing the new
architecture for place-and-route efficiency and exploiting an
aggressive 6-layer metal 0.18 µm CMOS process. These
advances make Virtex-E FPGAs powerful and flexible alter-
Module 1 of 4
2
natives to mask-programmed gate arrays. The Virtex-E family includes the nine members in Table 1.
Building on experience gained from Virtex FPGAs, the Virtex-E family is an evolutionary step forward in programmable logic design. Combining a wide variety of programmable
system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the Virtex-E family delivers a high-speed and high-capacity
programmable logic solution that enhances design flexibility
while reducing time-to-market.
Virtex-E Architecture
Virtex-E devices feature a flexible, regular architecture that
comprises an array of configurable logic blocks (CLBs) surrounded by programmable input/output blocks (IOBs), all
interconnected by a rich hierarchy of fast, versatile routing
resources. The abundance of routing resources permits the
Virtex-E family to accommodate even the largest and most
complex designs.
Virtex-E FPGAs are SRAM-based, and are customized by
loading configuration data into internal memory cells. Configuration data can be read from an external SPROM (master serial mode), or can be written into the FPGA
(SelectMAP™, slave serial, and JTAG modes).
The standard Xilinx Foundation Series™ and Alliance
Series™ Development systems deliver complete design
support for Virtex-E, covering every aspect from behavioral
and schematic entry, through simulation, automatic design
translation and implementation, to the creation and downloading of a configuration bit stream.
Higher Performance
Virtex-E devices provide better performance than previous
generations of FPGAs. Designs can achieve synchronous
system clock rates up to 240 MHz including I/O or 622 Mb/s
using Source Synchronous data transmission architechtures. Virtex-E I/Os comply fully with 3.3 V PCI specifications, and interfaces can be implemented that operate at
33 MHz or 66 MHz.
While performance is design-dependent, many designs
operate internally at speeds in excess of 133 MHz and can
achieve over 311 MHz. Table 2, page 3, shows performance data for representative circuits, using worst-case
timing parameters.
www.xilinx.com
1-800-255-7778
DS025-1 (v1.5) July 17, 2002
Production Product Specification
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 2: Performance for Common Circuit Functions
Function
Bits
Virtex-E -7
16
64
4.3 ns
6.3 ns
8x8
16 x 16
4.4 ns
5.1 ns
16
64
3.8 ns
5.5 ns
Register-to-Register
Adder
Pipelined Multiplier
Address Decoder
16:1 Multiplexer
4.6 ns
9
18
36
Parity Tree
3.5 ns
4.3 ns
5.9 ns
Chip-to-Chip
HSTL Class IV
LVTTL,16mA, fast slew
LVDS
LVPECL
Virtex-E Extended Memory Device/Package Combinations and Maximum I/O
Table 3: Virtex-EM Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins)
Package
XCV405E
XCV812E
BG560
404
404
FG676
404
FG900
556
Virtex-E Extended Memory Ordering Information
Example: XCV405E-6BG560C
Device Type
Speed Grade
(-6, -7, -8)
Temperature Range
C = Commercial (TJ = 0˚C to +85˚C)
I = Industrial (TJ = −40˚C to +100˚C)
Number of Pins
Package Type
BG = Ball Grid Array
FG = Fine Pitch Ball Grid Array
DS025_001_112000
Figure 1: Virtex Ordering Information
DS025-1 (v1.5) July 17, 2002
Production Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
3
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Revision History
The following table shows the revision history for this document.
Date
Version
03/23/00
1.0
Initial Xilinx release.
08/01/00
1.1
Accumulated edits and fixes. Upgrade to Preliminary. Preview -8 numbers added.
Reformatted to adhere to corporate documentation style guidelines. Minor changes in
BG560 pin-out table.
09/19/00
1.2
•
1.3
•
•
11/20/00
Revision
•
•
•
•
04/02/01
1.4
•
•
•
07/17/02
1.5
•
In Table 3 (Module 4), FG676 Fine-Pitch BGA — XCV405E, the following pins are no
longer labeled as VREF: B7, G16, G26, W26, AF20, AF8, Y1, H1.
Min values added to Virtex-E Electrical Characteristics tables.
Updated speed grade -8 numbers in Virtex-E Electrical Characteristics tables
(Module 3).
Updated minimums in Table 11 (Module 2), and added notes to Table 12 (Module 2).
Added to note 2 of Absolute Maximum Ratings (Module 3).
Changed all minimum hold times to –0.4 for Global Clock Set-Up and Hold for LVTTL
Standard, with DLL (Module 3).
Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters (Module 3).
In Table 4, FG676 Fine-Pitch BGA — XCV405E, pin B19 is no longer labeled as VREF,
and pin G16 is now labeled as VREF.
Updated values in Virtex-E Switching Characteristics tables.
Converted data sheet to modularized format. See Virtex-E Extended Memory Data
Sheet, below.
Data sheet designation upgraded from Preliminary to Production.
Virtex-E Extended Memory Data Sheet
The Virtex-E Extended Memory Data Sheet contains the following modules:
•
DS025-1, Virtex-E 1.8V Extended Memory FPGAs:
•
Introduction and Ordering Information (Module 1)
•
DS025-2, Virtex-E 1.8V Extended Memory FPGAs:
Functional Description (Module 2)
Module 1 of 4
4
DS025-3, Virtex-E 1.8V Extended Memory FPGAs:
DC and Switching Characteristics (Module 3)
•
DS025-4, Virtex-E 1.8V Extended Memory FPGAs:
Pinout Tables (Module 4)
www.xilinx.com
1-800-255-7778
DS025-1 (v1.5) July 17, 2002
Production Product Specification
0
Virtex™-E 1.8 V Extended Memory
Field Programmable Gate Arrays
R
DS025-2 (v2.1) July 17, 2002
0
0
Production Product Specification
Architectural Description
Virtex-E Array
The Virtex-E user-programmable gate array (see Figure 1)
comprises two major configurable elements: configurable
logic blocks (CLBs) and input/output blocks (IOBs).
• CLBs provide the functional elements for constructing
logic.
• IOBs provide the interface between the package pins
and the CLBs.
CLBs interconnect through a general routing matrix (GRM).
The GRM comprises an array of routing switches located at
the intersections of horizontal and vertical routing channels.
Each CLB nests into a VersaBlock™ that also provides local
routing resources to connect the CLB to the GRM.
The VersaRing™ I/O interface provides additional routing
resources around the periphery of the device. This routing
improves I/O routability and facilitates pin locking.
The Virtex-E architecture also includes the following circuits
that connect to the GRM:
• Dedicated block memories of 4096 bits each
• Clock DLLs for clock-distribution delay compensation
and clock domain control
• 3-State buffers (BUFTs) associated with each CLB that
drive dedicated segmentable horizontal routing resources
Values stored in static memory cells control the configurable
logic elements and interconnect resources. These values
load into the memory cells on power-up, and can reload if
necessary to change the function of the device.
Input/Output Block
The Virtex-E IOB, Figure 2, features SelectIO+™ inputs and
outputs that support a wide variety of I/O signalling standards (see Table 1).
T
TCE
D Q
CE
Weak
Keeper
SR
O
OCE
PAD
D Q
CE
OBUFT
SR
I
IQ
Q
D
CE
Programmable
Delay
IBUF
Vref
SR
SR
CLK
ICE
ds022_02_091300
Figure 2: Virtex-E Input/Output Block (IOB)
DLLDLL
DLLDLL
The three IOB storage elements function either as
edge-triggered D-type flip-flops or as level-sensitive latches.
Each IOB has a clock signal (CLK) shared by the three
flip-flops and independent clock enable signals for each
flip-flop.
CLBs
BRAMs
BRAMs
CLBs
CLBs
BRAMs
CLBs
BRAMs
IOBs
IOBs
VersaRing
VersaRing
DLLDLL
DLLDLL
ds022_001_121099
Figure 1: Virtex-E Architecture Overview
© 2000-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS025-2 (v2.1) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 2 of 4
1
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
R
Input Path
Table 1:
Supported I/O Standards
I/O
Output
Input
Input
Board
Termination
Voltage
Standard
VCCO
VCCO
VREF
(VTT)
LVTTL
3.3
3.3
N/A
N/A
LVCMOS2
2.5
2.5
N/A
N/A
LVCMOS18
1.8
1.8
N/A
N/A
SSTL3 I & II
3.3
N/A
1.50
1.50
SSTL2 I & II
2.5
N/A
1.25
1.25
GTL
N/A
N/A
0.80
1.20
GTL+
N/A
N/A
1.0
1.50
HSTL I
1.5
N/A
0.75
0.75
HSTL III & IV
1.5
N/A
0.90
1.50
CTT
3.3
N/A
1.50
1.50
AGP-2X
3.3
N/A
1.32
N/A
PCI33_3
3.3
3.3
N/A
N/A
PCI66_3
3.3
3.3
N/A
N/A
BLVDS & LVDS
2.5
N/A
N/A
N/A
LVPECL
3.3
N/A
N/A
N/A
In addition to the CLK and CE control signals, the three
flip-flops share a Set/Reset (SR). For each flip-flop, this signal can be independently configured as a synchronous Set,
a synchronous Reset, an asynchronous Preset, or an asynchronous Clear.
The output buffer and all of the IOB control signals have
independent polarity controls.
All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. When
PCI 3.3 V compliance is required, a conventional clamp
diode is connected to the output supply voltage, VCCO.
Optional pull-up, pull-down and weak-keeper circuits are
attached to each pad. Prior to configuration all outputs not
involved in configuration are forced into their high-impedance state. The pull-down resistors and the weak-keeper
circuits are inactive, but IOs can optionally be pulled up.
The activation of pull-up resistors prior to configuration is
controlled on a global basis by the configuration mode pins.
If the pull-up resistors are not activated, all the pins are in a
high-impedance state. Consequently, external pull-up or
pull-down resistors must be provided on pins required to be
at a well-defined logic level prior to configuration.
All Virtex-E IOBs support IEEE 1149.1-compatible boundary scan testing.
Module 2 of 4
2
The Virtex-E IOB input path routes the input signal directly
to internal logic and/ or through an optional input flip-flop.
An optional delay element at the D-input of this flip-flop eliminates pad-to-pad hold time. The delay is matched to the
internal clock-distribution delay of the FPGA, and when
used, assures that the pad-to-pad hold time is zero.
Each input buffer can be configured to conform to any of the
low-voltage signalling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, VREF. The need to supply VREF imposes
constraints on which standards can be used in close proximity to each other. See "I/O Banking" on page 2.
There are optional pull-up and pull-down resistors at each
input for use after configuration. Their value is in the range
50 - 100 kΩ.
Output Path
The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output signal can be
routed to the buffer directly from the internal logic or through
an optional IOB output flip-flop.
The 3-state control of the output can also be routed directly
from the internal logic or through a flip-flip that provides synchronous enable and disable.
Each output driver can be individually programmed for a
wide range of low-voltage signalling standards. Each output
buffer can source up to 24 mA and sink up to 48 mA. Drive
strength and slew rate controls minimize bus transients.
In most signalling standards, the output High voltage
depends on an externally supplied VCCO voltage. The need
to supply VCCO imposes constraints on which standards
can be used in close proximity to each other. See "I/O Banking" on page 2.
An optional weak-keeper circuit is connected to each output. When selected, the circuit monitors the voltage on the
pad and weakly drives the pin High or Low to match the
input signal. If the pin is connected to a multiple-source signal, the weak keeper holds the signal in its last state if all
drivers are disabled. Maintaining a valid logic level in this
way eliminates bus chatter.
Since the weak-keeper circuit uses the IOB input buffer to
monitor the input level, an appropriate VREF voltage must be
provided if the signalling standard requires one. The provision of this voltage must comply with the I/O banking rules.
I/O Banking
Some of the I/O standards described above require VCCO
and/or VREF voltages. These voltages are externally supplied and connected to device pins that serve groups of
IOBs, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Eight I/O banks result from separating each edge of the
FPGA into two banks, as shown in Figure 3. Each bank has
multiple VCCO pins, all of which must be connected to the
same voltage. This voltage is determined by the output
standards in use.
GCLK3 GCLK2
Bank 2
Bank 1
In Virtex-E, input buffers with LVTTL, LVCMOS2,
LVCMOS18, PCI33_3, PCI66_3 standards are supplied by
VCCO rather than VCCINT. For these standards, only input
and output buffers that have the same VCCO can be mixed
together.
The VCCO and VREF pins for each bank appear in the device
pin-out tables and diagrams. The diagrams also show the
bank affiliation of each I/O.
Bank 6
VirtexE
Device
GCLK1 GCLK0
Bank 5
Bank 4
ds022_03_121799
Figure 3: Virtex-E I/O Banks
Within a bank, output standards can be mixed only if they
use the same VCCO. Compatible standards are shown in
Table 2. GTL and GTL+ appear under all voltages because
their open-drain outputs do not depend on VCCO.
Table 2:
Compatible Output Standards
VCCO
Compatible Standards
3.3 V
PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,
GTL+, LVPECL
2.5 V
SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+,
BLVDS, LVDS
1.8 V
LVCMOS18, GTL, GTL+
1.5 V
HSTL I, HSTL III, HSTL IV, GTL, GTL+
Some input standards require a user-supplied threshold
voltage, VREF. In this case, certain user-I/O pins are automatically configured as inputs for the VREF voltage. Approximately one in six of the I/O pins in the bank assume this
role.
DS025-2 (v2.1) July 17, 2002
Within a bank, inputs that require VREF can be mixed with
those that do not. However, only one VREF voltage can be
used within a bank.
Bank 3
Bank 7
Bank 0
The VREF pins within a bank are interconnected internally
and consequently only one VREF voltage can be used within
each bank. All VREF pins in the bank, however, must be connected to the external voltage source for correct operation.
Within a given package, the number of VREF and VCCO pins
can vary depending on the size of device. In larger devices,
more I/O pins convert to VREF pins. Since these are always
a super set of the VREF pins used for smaller devices, it is
possible to design a PCB that permits migration to a larger
device if necessary. All the VREF pins for the largest device
anticipated must be connected to the VREF voltage, and not
used for I/O.
In smaller devices, some VCCO pins used in larger devices
do not connect within the package. These unconnected pins
can be left unconnected externally, or they can be connected to the VCCO voltage to permit migration to a larger
device, if necessary.
Configurable Logic Block
The basic building block of the Virtex-E CLB is the logic cell
(LC). An LC includes a 4-input function generator, carry
logic, and a storage element. The output from the function
generator in each LC drives both the CLB output and the D
input of the flip-flop. Each Virtex-E CLB contains four LCs,
organized in two similar slices, as shown in Figure 4.
Figure 5 shows a more detailed view of a single slice.
www.xilinx.com
1-800-255-7778
Module 2 of 4
3
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
COUT
COUT
YB
Y
G4
G3
G2
LUT
SP
D Q
CE
Carry &
Control
YB
Y
G4
G3
YQ
G1
LUT
G2
SP
D Q
CE
Carry &
Control
YQ
G1
RC
BY
RC
BY
XB
F3
XB
X
F4
LUT
F2
SP
D Q
CE
Carry &
Control
F1
F3
XQ
LUT
F2
SP
D Q
CE
Carry &
Control
XQ
F1
RC
BX
X
F4
RC
BX
Slice 1
Slice 0
CIN
CIN
ds022_04_121799
Figure 4: 2-Slice Virtex-E CLB
COUT
YB
CY
G4
G3
G2
G1
I3
I2
I1
I0
Y
O
LUT
DI
WE
0
INIT
D Q
CE
1
REV
YQ
BY
XB
F5IN
F6
CY
CK
WE
A4
WSH
BX
X
DI
INIT
DQ
CE
BX
F4
F3
F2
F1
I3
I2
I1
I0
F5
F5
BY DG
WSO
WE
XQ
DI
REV
O
LUT
0
1
SR
CLK
CE
CIN
ds022_05_092000
Figure 5: Detailed View of Virtex-E Slice
In addition to the four basic LCs, the Virtex-E CLB contains
logic that combines function generators to provide functions
of five or six inputs. Consequently, when estimating the
number of system gates provided by a given device, each
CLB counts as 4.5 LCs.
Module 2 of 4
4
Look-Up Tables
Virtex-E function generators are implemented as 4-input
look-up tables (LUTs). In addition to operating as a function
generator, each LUT can provide a 16 x 1-bit synchronous
RAM. Furthermore, the two LUTs within a slice can be com-
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM,
or a 16 x 1-bit dual-port synchronous RAM.
The Virtex-E LUT can also provide a 16-bit shift register that
is ideal for capturing high-speed or burst-mode data. This
mode can also be used to store data in applications such as
Digital Signal Processing.
Storage Elements
The storage elements in the Virtex-E slice can be configured either as edge-triggered D-type flip-flops or as
level-sensitive latches. The D inputs can be driven either by
the function generators within the slice or directly from slice
inputs, bypassing the function generators.
In addition to Clock and Clock Enable signals, each Slice
has synchronous set and reset signals (SR and BY). SR
forces a storage element into the initialization state specified for it in the configuration. BY forces it into the opposite
state. Alternatively, these signals can be configured to operate asynchronously. All of the control signals are independently invertible, and are shared by the two flip-flops within
the slice.
Additional Logic
The F5 multiplexer in each slice combines the function generator outputs. This combination provides either a function
generator that can implement any 5-input function, a 4:1
multiplexer, or selected functions of up to nine inputs.
Similarly, the F6 multiplexer combines the outputs of all four
function generators in the CLB by selecting one of the
F5-multiplexer outputs. This permits the implementation of
any 6-input function, an 8:1 multiplexer, or selected functions of up to 19 inputs.
Arithmetic Logic
Dedicated carry logic provides fast arithmetic carry capability for high-speed arithmetic functions. The Virtex-E CLB
supports two separate carry chains, one per Slice. The
height of the carry chains is two bits per CLB.
The arithmetic logic includes an XOR gate that allows a
2-bit full adder to be implemented within a slice. In addition,
a dedicated AND gate improves the efficiency of multiplier
implementation.
The dedicated carry path can also be used to cascade function generators for implementing wide logic functions.
BUFTs
Each Virtex-E CLB contains two 3-state drivers (BUFTs)
that can drive on-chip busses. See "Dedicated Routing" on
page 7. Each Virtex-E BUFT has an independent 3-state
control pin and an independent input pin.
Block SelectRAM
Virtex-E FPGAs incorporate large block SelectRAM memories. These complement the Distributed SelectRAM memories that provide shallow RAM structures implemented in
CLBs.
Block SelectRAM memory blocks are organized in columns,
starting at the left (column 0) and right outside edges and
inserted every four CLB columns (see notes for smaller
devices). Each memory block is four CLBs high, and each
memory column extends the full height of the chip, immediately adjacent (to the right, except for column 0) of the CLB
column locations indicated in Table 3.
Each CLB has four direct feedthrough paths, two per slice.
These paths provide extra data input lines or additional local
routing that does not consume logic resources.
Table 3:
CLB/Block RAM Column Locations
Virtex-E Device
0
4 8
12
16
20
24
XCV405E
√
√ √
√
√
√
√
XCV812E
√
√ √
√
√
√
√
28
√
32
√
Table 4 shows the amount of block SelectRAM memory that
is available in each Virtex-E device.
Table 4:
Virtex-E Block SelectRAM Amounts
Virtex-E Device
# of Blocks
Block SelectRAM Bits
XCV405E
140
573,440
XCV812E
280
1,146,880
DS025-2 (v2.1) July 17, 2002
36
40
44
48
52
56
60
√
√
√
√
√
√
√
√
√
√
√
√
64
68
72
76
80
84
√
√
√
√
√
√
Each block SelectRAM cell, as illustrated in Figure 6, is a
fully synchronous dual-ported (True Dual Port) 4096-bit
RAM with independent control signals for each port. The
data widths of the two ports can be configured independently, providing built-in bus-width conversion.
www.xilinx.com
1-800-255-7778
Module 2 of 4
5
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
.
RAMB4_S#_S#
WEA
ENA
RSTA
CLKA
ADDRA[#:0]
DIA[#:0]
WEB
ENB
RSTB
CLKB
ADDRB[#:0]
DIB[#:0]
To Adjacent
GRM
To
Adjacent
GRM
DOA[#:0]
To Adjacent
GRM
To Adjacent
GRM
Direct Connection
To Adjacent
CLB
DOB[#:0]
CLB
Direct
Connection
To Adjacent
CLB
XCVE_ds_007
Figure 7: Virtex-E Local Routing
ds022_06_121699
Figure 6: Dual-Port Block SelectRAM
General Purpose Routing
Table 5 shows the depth and width aspect ratios for the
block SelectRAM. The Virtex-E block SelectRAM also
includes dedicated routing to provide an efficient interface
with both CLBs and other block SelectRAM modules.
Table 5:
GRM
Block SelectRAM Port Aspect Ratios
Width
Depth
ADDR Bus
Data Bus
1
4096
ADDR<11:0>
DATA<0>
2
2048
ADDR<10:0>
DATA<1:0>
4
1024
ADDR<9:0>
DATA<3:0>
8
512
ADDR<8:0>
DATA<7:0>
16
256
ADDR<7:0>
DATA<15:0>
Most Virtex-E signals are routed on the general purpose
routing, and consequently, the majority of interconnect
resources are associated with this level of the routing hierarchy. The general routing resources are located in horizontal and vertical routing channels associated with the CLB
rows and columns. The general-purpose routing resources
are listed below.
•
Adjacent to each CLB is a General Routing Matrix
(GRM). The GRM is the switch matrix through which
horizontal and vertical routing resources connect, and
is also the means by which the CLB gains access to
the general purpose routing.
•
24 single-length lines route GRM signals to adjacent
GRMs in each of the four directions.
•
72 buffered Hex lines route GRM signals to another
GRMs six-blocks away in each one of the four
directions. Organized in a staggered pattern, Hex lines
are driven only at their endpoints. Hex-line signals can
be accessed either at the endpoints or at the midpoint
(three blocks from the source). One third of the Hex
lines are bidirectional, while the remaining ones are
uni-directional.
•
12 Longlines are buffered, bidirectional wires that
distribute signals across the device quickly and
efficiently. Vertical Longlines span the full height of the
device, and horizontal ones span the full width of the
device.
Programmable Routing Matrix
It is the longest delay path that limits the speed of any
worst-case design. Consequently, the Virtex-E routing
architecture and its place-and-route software were defined
in a joint optimization process. This joint optimization minimizes long-path delays, and consequently, yields the best
system performance.
The joint optimization also reduces design compilation
times because the architecture is software-friendly. Design
cycles are correspondingly reduced due to shorter design
iteration times.
Local Routing
I/O Routing
The VersaBlock, shown in Figure 7, provides local routing
resources with the following types of connections:
Virtex-E devices have additional routing resources around
their periphery that form an interface between the CLB array
and the IOBs. This additional routing, called the VersaRing,
facilitates pin-swapping and pin-locking, such that logic
redesigns can adapt to existing PCB layouts. Time-to-market is reduced, since PCBs and other system components
can be manufactured while the logic design is still in
progress.
•
•
•
Interconnections among the LUTs, flip-flops, and GRM
Internal CLB feedback paths that provide high-speed
connections to LUTs within the same CLB, chaining
them together with minimal routing delay
Direct paths that provide high-speed connections
between horizontally adjacent CLBs, eliminating the
delay of the GRM
Module 2 of 4
6
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Dedicated Routing
Some signal classes require dedicated routing resources to
maximize performance. In the Virtex-E architecture, dedicated routing resources are provided for two signal classes.
• Horizontal routing resources are provided for on-chip
3-state busses. Four partitionable bus lines are
provided per CLB row, permitting multiple busses
within a row, as shown in Figure 8.
•
Two dedicated nets per CLB propagate carry signals
vertically to the adjacent CLB. Global Clock Distribution
Network.
•
DLL Location
Tri-State
Lines
CLB
CLB
CLB
CLB
buft_c.eps
Figure 8: BUFT Connections to Dedicated Horizontal Bus LInes
Clock Routing
Clock Routing resources distribute clocks and other signals
with very high fanout throughout the device. Virtex-E
devices include two tiers of clock routing resources referred
to as global and local clock routing resources.
•
The global routing resources are four dedicated global
nets with dedicated input pins that are designed to
distribute high-fanout clock signals with minimal skew.
Each global clock net can drive all CLB, IOB, and block
RAM clock pins. The global nets can be driven only by
global buffers. There are four global buffers, one for
each global net.
•
The local clock routing resources consist of 24
backbone lines, 12 across the top of the chip and 12
across bottom. From these lines, up to 12 unique
signals per column can be distributed via the 12
longlines in the column. These local resources are
more flexible than the global resources since they are
not restricted to routing only to clock pins.
Global Clock Distribution
Virtex-E provides high-speed, low-skew clock distribution
through the global routing resources described above. A
typical clock distribution net is shown in Figure 9.
GCLKPAD3
GCLKPAD2
GCLKBUF3
GCLKBUF2
Global Clock Column
Global Clock Rows
Four global buffers are provided, two at the top center of the
device and two at the bottom center. These drive the four
global nets that in turn drive any clock pin.
Four dedicated clock pads are provided, one adjacent to
each of the global buffers. The input to the global buffer is
selected either from these pads or from signals in the general purpose routing.
Digital Delay-Locked Loops
Global Clock Spine
GCLKBUF1
GCLKBUF0
GCLKPAD1
GCLKPAD0
XCVE_009
Figure 9: Global Clock Distribution Network
DS025-2 (v2.1) July 17, 2002
There are eight DLLs (Delay-Locked Loops) per device,
with four located at the top and four at the bottom,
Figure 10. The DLLs can be used to eliminate skew
between the clock input pad and the internal clock input pins
throughout the device. Each DLL can drive two global clock
networks.The DLL monitors the input clock and the distributed clock, and automatically adjusts a clock delay element.
Additional delay is introduced such that clock edges arrive
at internal flip-flops synchronized with clock edges arriving
at the input.
In addition to eliminating clock-distribution delay, the DLL
provides advanced control of multiple clock domains. The
www.xilinx.com
1-800-255-7778
Module 2 of 4
7
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
DLL provides four quadrature phases of the source clock,
and can double the clock or divide the clock by 1.5, 2, 2.5, 3,
4, 5, 8, or 16.
DLLDLL
Secondary DLLs
In order to guarantee that the system clock is operating correctly prior to the FPGA starting up after configuration, the
DLL can delay the completion of the configuration process
until after it has achieved lock.
Primary DLLs
Secondary DLLs
The DLL also operates as a clock mirror. By driving the output
from a DLL off-chip and then back on again, the DLL can be
used to de-skew a board level clock among multiple devices.
DLLDLL
For more information about DLL functionality, see the
Design Consideration section of the data sheet.
DLLDLL
DLLDLL
XCVE_0010
Figure 10: DLL Locations
Boundary Scan
Virtex-E devices support all the mandatory boundary-scan
instructions specified in the IEEE standard 1149.1. A Test
Access Port (TAP) and registers are provided that implement the EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,
IDCODE, USERCODE, and HIGHZ instructions. The TAP
also supports two internal scan chains and configuration/readback of the device.
the bidirectional test capability after configuration facilitates
the testing of external interconnections.
The JTAG input pins (TDI, TMS, TCK) do not have a VCCO
requirement, and operate with either 2.5 V or 3.3 V input
signalling levels. The output pin (TDO) is sourced from the
VCCO in bank 2, and for proper operation of LVTTL 3.3 V
levels, the bank should be supplied with 3.3 V.
Before the device is configured, all instructions except
USER1 and USER2 are available. After configuration, all
instructions are available. During configuration, it is recommended that those operations using the boundary-scan
register (SAMPLE/PRELOAD, INTEST, EXTEST) not be
performed.
Boundary-scan operation is independent of individual IOB
configurations, and unaffected by package type. All IOBs,
including un-bonded ones, are treated as independent
3-state bidirectional pins in a single scan chain. Retention of
Module 2 of 4
8
Table 6 lists the boundary-scan instructions supported in
Virtex-E FPGAs. Internal signals can be captured during
EXTEST by connecting them to un-bonded or unused IOBs.
They can also be connected to the unused outputs of IOBs
defined as unidirectional input pins.
In addition to the test instructions outlined above, the
boundary-scan circuitry can be used to configure the
FPGA, and also to read back the configuration data.
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Figure 11 is a diagram of the Virtex-E Series boundary scan logic. It includes three bits of Data Register per IOB, the IEEE
1149.1 Test Access Port controller, and the Instruction Register with decodes.
DATA IN
IOB.T
0
1
0
IOB
IOB
IOB
IOB
sd
D
D
Q
Q
1
LE
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
1
sd
D
Q
D
Q
0
LE
1
IOB.I
0
1
IOB
IOB
IOB
IOB
IOB
BYPASS
REGISTER
0
sd
D
Q
D
Q
LE
1
0
IOB.Q
IOB
IOB.T
TDI
INSTRUCTION REGISTER
0
M TDO
U
X
1
0
sd
D
Q
D
Q
1
LE
1
0
sd
D
Q
D
Q
LE
1
IOB.I
0
DATAOUT
SHIFT/
CLOCK DATA
CAPTURE
REGISTER
UPDATE
EXTEST
X9016
Figure 11: Virtex-E Family Boundary Scan Logic
DS025-2 (v2.1) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 2 of 4
9
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 6:
Each EXTEST CAPTURED-OR state captures all In, Out,
and 3-state pins.
Boundary Scan Instructions
Boundary-Scan
Command
Binary
Code (4:0)
EXTEST
00000
Enable boundary-scan
EXTEST operation.
SAMPLE/
PRELOAD
00001
Enable boundary-scan
SAMPLE/PRELOAD
operation.
USER1
00010
Access user-defined
register 1.
USER2
00011
Access user-defined
register 2.
Description
CFG_OUT
00100
Access the
configuration bus for
read operations.
CFG_IN
00101
Access the
configuration bus for
write operations.
INTEST
00111
Enable boundary-scan
INTEST operation.
USERCODE
01000
Enable shifting out
USER code.
IDCODE
01001
Enable shifting out of ID
Code.
HIGHZ
01010
3-state output pins while
enabling the Bypass
Register.
JSTART
01100
Clock the start-up
sequence when
StartupClk is TCK.
BYPASS
11111
RESERVED
All other
codes
The other standard data register is the single flip-flop
BYPASS register. It synchronizes data being passed
through the FPGA to the next downstream boundary scan
device.
The FPGA supports up to two additional internal scan
chains that can be specified using the BSCAN macro. The
macro provides two user pins (SEL1 and SEL2) which are
decodes of the USER1 and USER2 instructions respectively. For these instructions, two corresponding pins (T
DO1 and TDO2) allow user scan data to be shifted out of
TDO.
Likewise, there are individual clock pins (DRCK1 and
DRCK2) for each user register. There is a common input pin
(TDI) and shared output pins that represent the state of the
TAP controller (RESET, SHIFT, and UPDATE).
Bit Sequence
The order within each IOB is: In, Out, 3-State. The
input-only pins contribute only the In bit to the boundary
scan I/O data register, while the output-only pins contributes
all three bits.
From a cavity-up view of the chip (as shown in EPIC), starting in the upper right chip corner, the boundary scan
data-register bits are ordered as shown in Figure 12.
BSDL (Boundary Scan Description Language) files for Virtex-E Series devices are available on the Xilinx web site in
the File Download area.
Bit 0 ( TDO end)
Bit 1
Bit 2
GCLK2
GCLK3
Left half of top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
Enable BYPASS.
M1
M0
M2
Xilinx reserved
instructions.
Left half of bottom-edge IOBs (Left to Right)
GCLK1
GCLK0
Instruction Set
Right half of bottom-edge IOBs (Left to Right)
The Virtex-E Series boundary scan instruction set also
includes instructions to configure the device and read back
configuration data (CFG_IN, CFG_OUT, and JSTART). The
complete instruction set is coded as shown in Table 6.
DONE
PROG
Right-edge IOBs (Bottom to Top)
(TDI end)
Data Registers
CCLK
990602001
The primary data register is the boundary scan register. For
each IOB pin in the FPGA, bonded or not, it includes three
bits for In, Out, and 3-State Control. Non-IOB pins have
appropriate partial bit population if input-only or output-only.
Module 2 of 4
10
Right half of top-edge IOBs (Right to Left)
www.xilinx.com
1-800-255-7778
Figure 12: Boundary Scan Bit Sequence
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Identification Registers
Table 7:
The IDCODE register is supported. By using the IDCODE,
the device connected to the JTAG port can be determined.
The IDCODE register has the following binary format:
vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1
where
v = the die version number
f = the family code (05 for Virtex-E family)
a = the number of CLB rows (ranges from 16 for
XCV50E to 104 for XCV3200E)
c = the company code (49h for Xilinx)
The USERCODE register is supported. By using the USERCODE, a user-programmable identification code can be
loaded and shifted out for examination. The identification
code (see Table 7) is embedded in the bitstream during bitstream generation and is valid only after configuration.
IDCODEs Assigned to Virtex-E FPGAs
FPGA
IDCODE
XCV405EM
v0C28093h
XCV812EM
v0C38093h
Note:
Attempting to load an incorrect bitstream causes
configuration to fail and can damage the device.
Including Boundary Scan in a Design
Since the boundary scan pins are dedicated, no special element needs to be added to the design unless an internal
data register (USER1 or USER2) is desired.
If an internal data register is used, insert the boundary scan
symbol and connect the necessary pins as appropriate.
Development System
Virtex-E FPGAs are supported by the Xilinx Foundation and
Alliance Series CAE tools. The basic methodology for Virtex-E design consists of three interrelated steps: design
entry, implementation, and verification. Industry-standard
tools are used for design entry and simulation (for example,
Synopsys FPGA Express), while Xilinx provides proprietary
architecture-specific tools for implementation.
The Xilinx development system is integrated under the Xilinx Design Manager (XDM™) software, providing designers
with a common user interface regardless of their choice of
entry and verification tools. The XDM software simplifies the
selection of implementation options with pull-down menus
and on-line help.
Application programs ranging from schematic capture to
Placement and Routing (PAR) can be accessed through the
XDM software. The program command sequence is generated prior to execution, and stored for documentation.
Several advanced software features facilitate Virtex-E design.
RPMs, for example, are schematic-based macros with relative
location constraints to guide their placement. They help
ensure optimal implementation of common functions.
For HDL design entry, the Xilinx FPGA Foundation development system provides interfaces to the following synthesis
design environments.
•
Synopsys (FPGA Compiler, FPGA Express)
•
Exemplar (Spectrum)
•
Synplicity (Synplify)
For schematic design entry, the Xilinx FPGA Foundation
and Alliance development system provides interfaces to the
following schematic-capture design environments.
•
Mentor Graphics V8 (Design Architect, QuickSim II)
•
Viewlogic Systems (Viewdraw)
Third-party vendors support many other environments.
DS025-2 (v2.1) July 17, 2002
A standard interface-file specification, Electronic Design
Interchange Format (EDIF), simplifies file transfers into and
out of the development system.
Virtex-E FPGAs are supported by a unified library of standard functions. This library contains over 400 primitives and
macros, ranging from 2-input AND gates to 16-bit accumulators, and includes arithmetic functions, comparators,
counters, data registers, decoders, encoders, I/O functions,
latches, Boolean functions, multiplexers, shift registers, and
barrel shifters.
The “soft macro” portion of the library contains detailed
descriptions of common logic functions, but does not contain any partitioning or placement information. The performance of these macros depends, therefore, on the
partitioning and placement obtained during implementation.
RPMs, on the other hand, do contain predetermined partitioning and placement information that permits optimal
implementation of these functions. Users can create their
own library of soft macros or RPMs based on the macros
and primitives in the standard library.
The design environment supports hierarchical design entry,
with high-level schematics that comprise major functional
blocks, while lower-level schematics define the logic in
these blocks. These hierarchical design elements are automatically combined by the implementation tools. Different
design entry tools can be combined within a hierarchical
design, thus allowing the most convenient entry method to
be used for each portion of the design.
Design Implementation
The place-and-route tools (PAR) automatically provide the
implementation flow described in this section. The partitioner takes the EDIF net list for the design and maps the
logic into the architectural resources of the FPGA (CLBs
and IOBs, for example). The placer then determines the
best locations for these blocks based on their interconnec-
www.xilinx.com
1-800-255-7778
Module 2 of 4
11
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
tions and the desired performance. Finally, the router interconnects the blocks.
The PAR algorithms support fully automatic implementation
of most designs. For demanding applications, however, the
user can exercise various degrees of control over the process. User partitioning, placement, and routing information
is optionally specified during the design-entry process. The
implementation of highly structured designs can benefit
greatly from basic floor planning.
The implementation software incorporates Timing Wizard®
timing-driven placement and routing. Designers specify timing requirements along entire paths during design entry.
The timing path analysis routines in PAR then recognize
these user-specified requirements and accommodate them.
Timing requirements are entered on a schematic in a form
directly relating to the system requirements, such as the targeted clock frequency, or the maximum allowable delay
between two registers. In this way, the overall performance
of the system along entire signal paths is automatically tailored to user-generated specifications. Specific timing information for individual nets is unnecessary.
Design Verification
In addition to conventional software simulation, FPGA users
can use in-circuit debugging techniques. Because Xilinx
devices are infinitely reprogrammable, designs can be verified in real time without the need for extensive sets of software simulation vectors.
The development system supports both software simulation
and in-circuit debugging techniques. For simulation, the
system extracts the post-layout timing information from the
design database, and back-annotates this information into
the net list for use by the simulator. Alternatively, the user
can verify timing-critical portions of the design using the
TRCE® static timing analyzer.
For in-circuit debugging, an optional download and readback cable is available. This cable connects the FPGA in the
target system to a PC or workstation. After downloading the
design into the FPGA, the designer can single-step the
logic, readback the contents of the flip-flops, and so observe
the internal logic state. Simple modifications can be downloaded into the system in a matter of minutes.
Configuration
Virtex-E devices are configured by loading configuration
data into the internal configuration memory. Note that
attempting to load an incorrect bitstream causes configuration to fail and can damage the device.
Some of the pins used for configuration are dedicated pins,
while others can be re-used as general purpose inputs and
outputs once configuration is complete.
The following are dedicated pins:
• Mode pins (M2, M1, M0)
• Configuration clock pin (CCLK)
• PROGRAM pin
• DONE pin
• Boundary-scan pins (TDI, TDO, TMS, TCK)
Depending on the configuration mode chosen, CCLK can
be an output generated by the FPGA, or it can be generated
externally and provided to the FPGA as an input. For correct
operation, these pins require a VCCO of 3.3 V to permit
LVTTL operation. All of the pins affected are in banks 2 or 3.
Table 8:
Configuration Modes
Virtex-E supports the following four configuration modes.
•
Slave-serial mode
•
Master-serial mode
•
SelectMAP mode
•
Boundary-scan mode (JTAG)
The Configuration mode pins (M2, M1, M0) select among
these configuration modes with the option in each case of
having the IOB pins either pulled up or left floating prior to
configuration. The selection codes are listed in Table 8.
Configuration through the boundary-scan port is always
available, independent of the mode selection. Selecting the
boundary-scan mode simply turns off the other modes. The
three mode pins have internal pull-up resistors, and default
to a logic High if left unconnected.
Configuration Codes
Configuration Mode
M2
M1
M0
CCLK Direction
Data Width
Serial Dout
Configuration Pull-ups
Master-serial mode
0
0
0
Out
1
Yes
No
Boundary-scan mode
1
0
1
N/A
1
No
No
SelectMAP mode
1
1
0
In
8
No
No
Slave-serial mode
1
1
1
In
1
Yes
No
Master-serial mode
1
0
0
Out
1
Yes
Yes
Boundary-scan mode
0
0
1
N/A
1
No
Yes
SelectMAP mode
0
1
0
In
8
No
Yes
Slave-serial mode
0
1
1
In
1
Yes
Yes
Module 2 of 4
12
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 9 lists the total number of bits required to configure
each device.
ured, the data for the next device is routed to the DOUT pin.
Data on the DOUT pin changes on the rising edge of CCLK.
Table 9:
The change of DOUT on the rising edge of CCLK differs
from previous families but does not cause a problem for
mixed configuration chains. This change was made to
improve serial configuration rates for Virtex and Virtex-E
only chains.
Virtex-E Bitstream Lengths
Device
# of Configuration Bits
XCV405E
3,430,400
XCV812E
6,519,648
Slave-Serial Mode
Figure 13 shows a full master/slave system. A Virtex-E
device in slave-serial mode should be connected as shown
in the right-most device.
In slave-serial mode, the FPGA receives configuration data
in bit-serial form from a serial PROM or other source of
serial configuration data. The serial bitstream must be set
up at the DIN input pin a short time before each rising edge
of an externally generated CCLK.
Slave-serial mode is selected by applying <111> or <011>
to the mode pins (M2, M1, M0). A weak pull-up on the mode
pins makes slave-serial the default mode if the pins are left
unconnected. Figure 14 shows slave-serial configuration
timing.
For more information on serial PROMs, see the PROM data
sheet at http://www.xilinx.com/partinfo/ds026.pdf.
Table 10 provides more detail about the characteristics
shown in Figure 14. Configuration must be delayed until the
INIT pins of all daisy-chained FPGAs are High.
Multiple FPGAs can be daisy-chained for configuration from
a single source. After a particular FPGA has been configTable 10:
Master/Slave Serial Mode Programming Switching
Figure
References
Symbol
Values
Units
DIN setup/hold, slave mode
1/2
TDCC/TCCD
5.0/0.0
ns, min
DIN setup/hold, master mode
1/2
TDSCK/TCKDS
5.0/0.0
ns, min
DOUT
3
TCCO
12.0
ns, max
High time
4
TCCH
5.0
ns, min
Low time
5
TCCL
5.0
ns, min
FCC
66
MHz, max
Description
CCLK
Maximum Frequency
Frequency Tolerance, master mode with respect to nominal
+45% –30%
N/C
3.3V
4.7 K
M0 M1
M2
N/C
DOUT
VIRTEX-E
MASTER
SERIAL
CCLK
DIN
PROGRAM
DONE
INIT
M0 M1
M2
DIN
DOUT
CCLK
XC1701L
CLK
DATA
CEO
CE
RESET/OE
VIRTEX-E,
XC4000XL,
SLAVE
PROGRAM
DONE
INIT
(Low Reset Option Used)
PROGRAM
XCVE_ds_013
Figure 13: Master/Slave Serial Mode Circuit Diagram
DS025-2 (v2.1) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 2 of 4
13
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
DIN
1 TDCC
2 TCCD
5 TCCL
CCLK
4 TCCH
3 TCCO
DOUT
(Output)
X5379_a
Figure 14: Slave-Serial Mode Programming Switching Characteristics
Master-Serial Mode
In master-serial mode, the CCLK output of the FPGA drives
a Xilinx Serial PROM that feeds bit-serial data to the DIN
input. The FPGA accepts this data on each rising CCLK
edge. After the FPGA has been loaded, the data for the next
device in a daisy-chain is presented on the DOUT pin after
the rising CCLK edge.
RESET pin is driven by INIT, and the CE input is driven by
DONE. There is the potential for contention on the DONE pin,
depending on the start-up sequence options chosen.
The sequence of operations necessary to configure a
Virtex-E FPGA serially appears in Figure 15.
The interface is identical to slave-serial except that an internal oscillator is used to generate the configuration clock
(CCLK). A wide range of frequencies can be selected for
CCLK which always starts at a slow default frequency. Configuration bits then switch CCLK to a higher frequency for
the remainder of the configuration. Switching to a lower frequency is prohibited.
Apply Power
FPGA starts to clear
configuration memory.
Set PROGRAM = High
FPGA makes a final
clearing pass and releases
INIT when finished.
On power-up, the CCLK frequency is approximately
2.5 MHz. This frequency is used until the ConfigRate bits
have been loaded when the frequency changes to the
selected ConfigRate. Unless a different frequency is specified in the design, the default ConfigRate is 4 MHz.
Figure 13 shows a full master/slave system. In this system,
the left-most device operates in master-serial mode. The
remaining devices operate in slave-serial mode. The SPROM
Low
INIT?
The CCLK frequency is set using the ConfigRate option in
the bitstream generation software. The maximum CCLK frequency that can be selected is 60 MHz. When selecting a
CCLK frequency, ensure that the serial PROM and any
daisy-chained FPGAs are fast enough to support the clock
rate.
If used to delay
configuration
Release INIT
High
Load a Configuration Bit
Once per bitstream,
FPGA checks data using CRC
and pulls INIT Low on error.
If no CRC errors found,
FPGA enters start-up phase
causing DONE to go High.
End of
Bitstream?
No
Yes
Configuration Completed
ds009_15_111799
Figure 15: Serial Configuration Flowchart
Figure 16 shows the timing of master-serial configuration.
Master-serial mode is selected by a <000> or <100> on the
mode pins (M2, M1, M0). Table 10 shows the timing information for Figure 16
.
CCLK
(Output)
TCKDS 2
1 TDSCK
Serial Data In
Serial DOUT
(Output)
DS022_44_071201
Figure 16: Master-Serial Mode Programming Switching Characteristics
Module 2 of 4
14
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
At power-up, VCC must rise from 1.0 V to VCC min in less
than 50 ms, otherwise delay configuration by pulling
PROGRAM Low until VCC is valid.
SelectMAP Mode
The SelectMAP mode is the fastest configuration option.
Byte-wide data is written into the FPGA with a BUSY flag
controlling the flow of data.
An external data source provides a byte stream, CCLK, a
Chip Select (CS) signal and a Write signal (WRITE). If
BUSY is asserted (High) by the FPGA, the data must be
held until BUSY goes Low.
Data can also be read using the SelectMAP mode. If
WRITE is not asserted, configuration data is read out of the
FPGA as part of a readback operation.
After configuration, the pins of the SelectMAP port can be
used as additional user I/O. Alternatively, the port can be
retained to permit high-speed 8-bit readback.
Retention of the SelectMAP port is selectable on a
design-by-design basis when the bitstream is generated. If
retention is selected, PROHIBIT constraints are required to
prevent SelectMAP-port pins from being used as user I/O.
Multiple Virtex-E FPGAs can be configured using the
SelectMAP mode, and be made to start-up simultaneously.
To configure multiple devices in this way, wire the individual
CCLK, Data, WRITE, and BUSY pins of all the devices in
parallel. The individual devices are loaded separately by
asserting the CS pin of each device in turn and writing the
appropriate data. See Table 11 for SelectMAP Write Timing
Characteristics.
Table 11:
Write
Write operations send packets of configuration data into the
FPGA. The sequence of operations for a multi-cycle write
operation is shown below. Note that a configuration packet
can be split into many such sequences. The packet does
not have to complete within one assertion of CS, illustrated
in Figure 17.
1.
Assert WRITE and CS Low. Note that when CS is
asserted on successive CCLKs, WRITE must remain
either asserted or de-asserted. Otherwise an abort is
initiated, as described below.
2.
Drive data onto D[7:0]. Note that to avoid contention,
the data source should not be enabled while CS is Low
and WRITE is High. Similarly, while WRITE is High, no
more that one CS should be asserted.
3.
At the rising edge of CCLK: If BUSY is Low, the data is
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance instead
occurs on the first clock after BUSY goes Low, and the
data must be held until this has happened.
4.
Repeat steps 2 and 3 until all the data has been sent.
5.
De-assert CS and WRITE.
SelectMAP Write Timing Characteristics
Description
Symbol
Values
Units
D0-7 Setup/Hold
1/2
TSMDCC/TSMCCD
5.0 / 1.0
ns, min
CS Setup/Hold
3/4
TSMCSCC/TSMCCCS
7.0 / 1.0
ns, min
WRITE Setup/Hold
5/6
TSMCCW/TSMWCC
7.0 / 1.0
ns, min
7
TSMCKBY
12.0
ns, max
FCC
66
MHz, max
FCCNH
50
MHz, max
CCLK
BUSY Propagation Delay
Maximum Frequency
Maximum Frequency with no handshake
DS025-2 (v2.1) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 2 of 4
15
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
CCLK
CS
WRITE
3
4
5
6
1
2
DATA[0:7]
7
BUSY
No Write
Write
No Write
Write
DS022_45_071702
Figure 17: Write Operations
A flowchart for the write operation appears in Figure 18.
Note that if CCLK is slower than fCCNH, the FPGA never
asserts BUSY, In this case, the above handshake is unnecessary, and data can simply be entered into the FPGA every
CCLK cycle.
Apply Power
FPGA starts to clear
configuration memory.
Set PROGRAM = High
FPGA makes a final
clearing pass and releases
INIT when finished.
Abort
During a given assertion of CS, the user cannot switch from
a write to a read, or vice-versa. This action causes the current packet command to be aborted. The device remains
BUSY until the aborted operation has completed. Following
an abort, data is assumed to be unaligned to word boundaries, and the FPGA requires a new synchronization word
prior to accepting any new packets.
If used to delay
configuration
Release INIT
INIT?
Low
High
Set WRITE = Low
Enter Data Source
Sequence A
On first FPGA
Set CS = Low
To initiate an abort during a write operation, de-assert
WRITE. At the rising edge of CCLK, an abort is initiated, as
shown in Figure 19.
Apply Configuration Byte
Once per bitstream,
FPGA checks data using CRC
and pulls INIT Low on error.
Busy?
High
Low
End of Data?
If no errors,
first FPGAs enter start-up phase
releasing DONE.
If no errors,
later FPGAs enter start-up phase
releasing DONE.
No
Yes
Set CS = High
Repeat Sequence A
On first FPGA
For any other FPGAs
Disable Data Source
Set WRITE = High
When all DONE pins
are released, DONE goes High
and start-up sequences complete.
Configuration Completed
ds009_18_111799
Figure 18: SelectMAP Flowchart for Write Operations
Module 2 of 4
16
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
CCLK
CS
WRITE
DATA[0:7]
BUSY
Abort
DS022_46_071702
Figure 19: SelectMAP Write Abort Waveforms
Boundary-Scan Mode
7.
Clock TCK through the startup sequence
In the boundary-scan mode, no non-dedicated pins are
required, configuration being done entirely through the
IEEE 1149.1 Test Access Port.
8.
Return to RTI
Configuration through the TAP uses the CFG_IN instruction. This instruction allows data input on TDI to be converted into data packets for the internal configuration bus.
The following steps are required to configure the FPGA
through the boundary-scan port (when using TCK as a
start-up clock).
1. Load the CFG_IN instruction into the boundary-scan
instruction register (IR)
2. Enter the Shift-DR (SDR) state
3. Shift a configuration bitstream into TDI
4. Return to Run-Test-Idle (RTI)
5. Load the JSTART instruction into IR
6. Enter the SDR state
DS025-2 (v2.1) July 17, 2002
Configuration and readback via the TAP is always available.
The boundary-scan mode is selected by a <101> or <001>
on the mode pins (M2, M1, M0).
Configuration Sequence
The configuration of Virtex-E devices is a three-phase process. First, the configuration memory is cleared. Next, configuration data is loaded into the memory, and finally, the
logic is activated by a start-up process.
Configuration is automatically initiated on power-up unless
it is delayed by the user, as described below. The configuration process can also be initiated by asserting PROGRAM.
The end of the memory-clearing phase is signalled by INIT
going High, and the completion of the entire process is signalled by DONE going High.
The power-up timing of configuration signals is shown in
Figure 20.
www.xilinx.com
1-800-255-7778
Module 2 of 4
17
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Vcc
TPOR
PROGRAM
TPL
INIT
TICCK
CCLK OUTPUT or INPUT
M0, M1, M2
(Required)
VALI
ds022_020_071201
Figure 20: Power-Up Timing Configuration Signals
The corresponding timing characteristics are listed in
Table 12.
Table 12:
Power-up Timing Characteristics
Description
Symbol
Value
Units
Power-on Reset1
TPOR
2.0
ms, max
Program Latency
TPL
100.0
µs, max
0.5
µs, min
4.0
µs, max
300
ns, min
CCLK (output) Delay
Program Pulse Width
TICCK
TPROGRAM
Notes:
1. TPOR delay is the initialization time required after VCCINT
reaches the recommended operating voltage.
Start-Up Sequence
The default Start-up sequence is that one CCLK cycle after
DONE goes High, the global 3-state signal (GTS) is
released. This permits device outputs to turn on as necessary.
One CCLK cycle later, the Global Set/Reset (GSR) and Global Write Enable (GWE) signals are released. This permits
the internal storage elements to begin changing state in
response to the logic and the user clock.
The relative timing of these events can be changed. In addition, the GTS, GSR, and GWE events can be made dependent on the DONE pins of multiple devices all going High,
forcing the devices to start synchronously. The sequence
can also be paused at any stage until lock has been
achieved on any or all DLLs.
Delaying Configuration
INIT can be held Low using an open-drain driver. An
open-drain is required since INIT is a bidirectional
open-drain pin that is held Low by the FPGA while the configuration memory is being cleared. Extending the time that
the pin is Low causes the configuration sequencer to wait.
Thus, configuration is delayed by preventing entry into the
phase where data is loaded.
Readback
The configuration data stored in the Virtex-E configuration
memory can be readback for verification. Along with the
configuration data it is possible to readback the contents all
flip-flops/latches, LUT RAMs, and block RAMs. This capa-
Module 2 of 4
18
bility is used for real-time debugging. For more detailed
information, see application note XAPP138 “Virtex FPGA
Series Configuration and Readback”.
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Design Considerations
This section contains more detailed design information on
the following features.
•
Delay-Locked Loop . . . see page 19
•
BlockRAM . . . see page 23
•
SelectI/O . . . see page 30
In order to guarantee the system clock establishes prior to
the device “waking up,” the DLL can delay the completion of
the device configuration process until after the DLL
achieves lock.
By taking advantage of the DLL to remove on-chip clock
delay, the designer can greatly simplify and improve system
level design involving high-fanout, high-performance clocks.
Using DLLs
The Virtex-E FPGA series provides up to eight fully digital
dedicated on-chip Delay-Locked Loop (DLL) circuits which
provide zero propagation delay, low clock skew between
output clock signals distributed throughout the device, and
advanced clock domain control. These dedicated DLLs can
be used to implement several circuits which improve and
simplify system level design.
Introduction
As FPGAs grow in size, quality on-chip clock distribution
becomes increasingly important. Clock skew and clock
delay impact device performance and the task of managing
clock skew and clock delay with conventional clock trees
becomes more difficult in large devices. The Virtex-E series
of devices resolve this potential problem by providing up to
eight fully digital dedicated on-chip DLL circuits which provide zero propagation delay and low clock skew between
output clock signals distributed throughout the device.
Library DLL Symbols
Figure 21 shows the simplified Xilinx library DLL macro
symbol, BUFGDLL. This macro delivers a quick and efficient way to provide a system clock with zero propagation
delay throughout the device. Figure 22 and Figure 23 show
the two library DLL primitives. These symbols provide
access to the complete set of DLL features when implementing more complex applications.
I
ds022_25_121099
Figure 21: Simplified DLL Macro Symbol BUFGDLL
Each DLL can drive up to two global clock routing networks
within the device. The global clock distribution network minimizes clock skews due to loading differences. By monitoring a sample of the DLL output clock, the DLL can
compensate for the delay on the routing network, effectively
eliminating the delay from the external input port to the individual clock loads within the device.
In addition to providing zero delay with respect to a user
source clock, the DLL can provide multiple phases of the
source clock. The DLL can also act as a clock doubler or it
can divide the user source clock by up to 16.
Clock multiplication gives the designer a number of design
alternatives. For instance, a 50 MHz source clock doubled
by the DLL can drive an FPGA design operating at 100
MHz. This technique can simplify board design because the
clock path on the board no longer distributes such a
high-speed signal. A multiplied clock also provides designers the option of time-domain-multiplexing, using one circuit
twice per clock cycle, consuming less area than two copies
of the same circuit. Two DLLs in can be connected in series
to increase the effective clock multiplication factor to four.
The DLL can also act as a clock mirror. By driving the DLL
output off-chip and then back in again, the DLL can be used
to de-skew a board level clock between multiple devices.
DS025-2 (v2.1) July 17, 2002
O
0ns
www.xilinx.com
1-800-255-7778
CLKDLL
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
CLK2X
CLKDV
RST
LOCKED
ds022_26_121099
Figure 22: Standard DLL Symbol CLKDLL
CLKDLLHF
CLKIN
CLKFB
CLK0
CLK180
CLKDV
RST
LOCKED
ds022_027_121099
Figure 23: High Frequency DLL Symbol
Module 2 of 4
19
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
BUFGDLL Pin Descriptions
Use the BUFGDLL macro as the simplest way to provide
zero propagation delay for a high-fanout on-chip clock from
an external input. This macro uses the IBUFG, CLKDLL and
BUFG primitives to implement the most basic DLL application as shown in Figure 24.
IBUFG
I
O
CLKDLL
CLKIN
CLKFB
CLK0
CLK90
CLK180
CLK270
BUFG
I
O
DLLs. This makes a total of eight usable input pins for DLLs
in the Virtex-E family.
Feedback Clock Input — CLKFB
The DLL requires a reference or feedback signal to provide
the delay-compensated output. Connect only the CLK0 or
CLK2X DLL outputs to the feedback clock input (CLKFB)
pin to provide the necessary feedback to the DLL. The feedback clock input can also be provided through one of the following pins.
IBUFG - Global Clock Input Pad
CLK2X
IO_LVDS_DLL - the pin adjacent to IBUF
CLKDV
RST
If an IBUFG sources the CLKFB pin, the following special
rules apply.
LOCKED
ds022_28_121099
1.
An external input port must source the signal that drives
the IBUFG I pin.
2.
The CLK2X output must feedback to the device if both
the CLK0 and CLK2X outputs are driving off chip
devices.
3.
That signal must directly drive only OBUFs and nothing
else.
Figure 24: BUFGDLL Schematic
This symbol does not provide access to the advanced clock
domain controls or to the clock multiplication or clock division features of the DLL. This symbol also does not provide
access to the RST, or LOCKED pins of the DLL. For access
to these features, a designer must use the library DLL primitives described in the following sections.
Source Clock Input — I
The I pin provides the user source clock, the clock signal on
which the DLL operates, to the BUFGDLL. For the BUFGDLL macro the source clock frequency must fall in the low
frequency range as specified in the data sheet. The BUFGDLL requires an external signal source clock. Therefore,
only an external input port can source the signal that drives
the BUFGDLL I pin.
Clock Output — O
The clock output pin O represents a delay-compensated
version of the source clock (I) signal. This signal, sourced by
a global clock buffer BUFG symbol, takes advantage of the
dedicated global clock routing resources of the device.
The output clock has a 50-50 duty cycle unless you deactivate the duty cycle correction property.
CLKDLL Primitive Pin Descriptions
The library CLKDLL primitives provide access to the complete set of DLL features needed when implementing more
complex applications with the DLL.
Source Clock Input — CLKIN
The CLKIN pin provides the user source clock (the clock
signal on which the DLL operates) to the DLL. The CLKIN
frequency must fall in the ranges specified in the data sheet.
A global clock buffer (BUFG) driven from another CLKDLL,
one of the global clock input buffers (IBUFG), or an
IO_LVDS_DLL pin on the same edge of the device (top or
bottom) must source this clock signal. There are four
IO_LVDS_DLL input pins that can be used as inputs to the
Module 2 of 4
20
These rules enable the software determine which DLL clock
output sources the CLKFB pin.
Reset Input — RST
When the reset pin RST activates the LOCKED signal deactivates within four source clock cycles. The RST pin, active
High, must either connect to a dynamic signal or tied to
ground. As the DLL delay taps reset to zero, glitches can
occur on the DLL clock output pins. Activation of the RST
pin can also severely affect the duty cycle of the clock output pins. Furthermore, the DLL output clocks no longer
de-skew with respect to one another. For these reasons,
rarely use the reset pin unless re-configuring the device or
changing the input frequency.
2x Clock Output — CLK2X
The output pin CLK2X provides a frequency-doubled clock
with an automatic 50/50 duty-cycle correction. Until the
CLKDLL has achieved lock, the CLK2X output appears as a
1x version of the input clock with a 25/75 duty cycle. This
behavior allows the DLL to lock on the correct edge with
respect to source clock. This pin is not available on the
CLKDLLHF primitive.
Clock Divide Output — CLKDV
The clock divide output pin CLKDV provides a lower frequency version of the source clock. The CLKDV_DIVIDE
property controls CLKDV such that the source clock is
divided by N where N is either 1.5, 2, 2.5, 3, 4, 5, 8, or 16.
This feature provides automatic duty cycle correction such
that the CLKDV output pin always has a 50/50 duty cycle,
with the exception of noninteger divides in HF mode, where
the duty cycle is 1/3 for N=1.5 and 2/5 for N=2.5.
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
1x Clock Outputs — CLK[0|90|180|270]
The 1x clock output pin CLK0 represents a delay-compensated version of the source clock (CLKIN) signal. The
CLKDLL primitive provides three phase-shifted versions of
the CLK0 signal while CLKDLLHF provides only the 180
phase-shifted version. The relationship between phase shift
and the corresponding period shift appears in Table 13.
Table 13:
Relationship of Phase-Shifted Output Clock
to Period Shift
Phase (degrees)
Period Shift (percent)
0
0%
90
25%
180
50%
270
75%
90 180 270
0
Locked Output — LOCKED
To achieve lock, the DLL might need to sample several thousand clock cycles. After the DLL achieves lock, the
LOCKED signal activates. The DLL timing parameter section of the data sheet provides estimates for locking times.
To guarantee that the system clock is established prior to
the device “waking up,” the DLL can delay the completion of
the device configuration process until after the DLL locks.
The STARTUP_WAIT property activates this feature.
Until the LOCKED signal activates, the DLL output clocks
are not valid and can exhibit glitches, spikes, or other spurious movement. In particular the CLK2X output appears as a
1x clock with a 25/75 duty cycle.
The timing diagrams in Figure 25 illustrate the DLL clock
output characteristics.
0
The DLL clock outputs can drive an OBUF, a BUFG, or they
can route directly to destination clock pins. The DLL clock
outputs can only drive the BUFGs that reside on the same
edge (top or bottom).
90 180 270
t
DLL Properties
Properties provide access to some of the Virtex-E series
DLL features, (for example, clock division and duty cycle
correction).
Duty Cycle Correction Property
CLKIN
The 1x clock outputs, CLK0, CLK90, CLK180, and CLK270,
use the duty-cycle corrected default, exhibiting a 50/50 duty
cycle. The DUTY_CYCLE_CORRECTION property (by
default TRUE) controls this feature. To deactivate the DLL
duty-cycle correction for the 1x clock outputs, attach the
DUTY_CYCLE_CORRECTION=FALSE property to the
DLL symbol. When duty-cycle correction deactivates, the
output clock has the same duty cycle as the source clock.
CLK2X
CLKDV_DIVIDE=2
CLKDV
DUTY_CYCLE_CORRECTION=FALSE
CLK0
CLK90
Clock Divide Property
CLK180
The CLKDV_DIVIDE property specifies how the signal on
the CLKDV pin is frequency divided with respect to the
CLK0 pin. The values allowed for this property are 1.5, 2,
2.5, 3, 4, 5, 8, or 16; the default value is 2.
CLK270
DUTY_CYCLE_CORRECTION=TRUE
CLK0
Startup Delay Property
CLK90
This property, STARTUP_WAIT, takes on a value of TRUE
or FALSE (the default value). When TRUE the device configuration DONE signal waits until the DLL locks before
going to High.
CLK180
CLK270
ds022_29_121099
Virtex-E DLL Location Constraints
Figure 25: DLL Output Characteristics
The DLL provides duty cycle correction on all 1x clock outputs such that all 1x clock outputs by default have a 50/50
duty cycle. The DUTY_CYCLE_CORRECTION property
(TRUE by default), controls this feature. In order to deactivate the DLL duty cycle correction, attach the
DUTY_CYCLE_CORRECTION=FALSE property to the
DLL symbol. When duty cycle correction deactivates, the
output clock has the same duty cycle as the source clock.
DS025-2 (v2.1) July 17, 2002
As shown in Figure 26, there are four additional DLLs in the
Virtex-E devices, for a total of eight per Virtex-E device.
These DLLs are located in silicon, at the top and bottom of
the two innermost block SelectRAM columns. The location
constraint LOC, attached to the DLL symbol with the identifier DLL0S, DLL0P, DLL1S, DLL1P, DLL2S, DLL2P, DLL3S,
or DLL3P, controls the DLL location.
The LOC property uses the following form:
LOC = DLL0P
www.xilinx.com
1-800-255-7778
Module 2 of 4
21
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
DLL-3S
DLL-3P
DLL-2P
DLL-2S
B
R
A
M
B
R
A
M
B
R
A
M
B
R
A
M
DLL-1S
DLL-1P
DLL-0P
DLL-0S
In a similar manner, a phase shift of the input clock is also
possible. The phase shift propagates one to four clocks to
the output after the original shift, with no disruption to the
CLKDLL control.
Output Clocks
Bottom Right
Half Edge
x132_14_100799
Figure 26: Virtex Series DLLs
Design Factors
Use the following design considerations to avoid pitfalls and
improve success designing with Xilinx devices.
Input Clock
The output clock signal of a DLL, essentially a delayed version of the input clock signal, reflects any instability on the
input clock in the output waveform. For this reason the quality of the DLL input clock relates directly to the quality of the
output clock waveforms generated by the DLL. The DLL
input clock requirements are specified in the data sheet.
In most systems a crystal oscillator generates the system
clock. The DLL can be used with any commercially available
quartz crystal oscillator. For example, most crystal oscillators produce an output waveform with a frequency tolerance
of 100 PPM, meaning 0.01 percent change in the clock
period. The DLL operates reliably on an input waveform with
a frequency drift of up to 1 ns — orders of magnitude in
excess of that needed to support any crystal oscillator in the
industry. However, the cycle-to-cycle jitter must be kept to
less than 300 ps in the low frequencies and 150 ps for the
high frequencies.
As mentioned earlier in the DLL pin descriptions, some
restrictions apply regarding the connectivity of the output
pins. The DLL clock outputs can drive an OBUF, a global
clock buffer BUFG, or they can route directly to destination
clock pins. The only BUFGs that the DLL clock outputs can
drive are the two on the same edge of the device (top or bottom). In addition, the CLK2X output of the secondary DLL
can connect directly to the CLKIN of the primary DLL in the
same quadrant.
Do not use the DLL output clock signals until after activation
of the LOCKED signal. Prior to the activation of the
LOCKED signal, the DLL output clocks are not valid and
can exhibit glitches, spikes, or other spurious movement.
Useful Application Examples
The Virtex-E DLL can be used in a variety of creative and
useful applications. The following examples show some of
the more common applications. The Verilog and VHDL
example files are available at:
ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip
Standard Usage
The circuit shown in Figure 27 resembles the BUFGDLL
macro implemented to provide access to the RST and
LOCKED pins of the CLKDLL.
CLKDLL
IBUFG
CLKIN
CLKFB
Input Clock Changes
BUFG
CLK0
CLK90
CLK180
CLK270
CLK2X
CLKDV
Changing the period of the input clock beyond the maximum
drift amount requires a manual reset of the CLKDLL. Failure
to reset the DLL produces an unreliable lock signal and output clock.
It is possible to stop the input clock with little impact to the
DLL. Stopping the clock should be limited to less than
100 µs to keep device cooling to a minimum. The clock
should be stopped during a Low phase, and when restored
the full High period should be seen. During this time
LOCKED stays High and remains High when the clock is
restored.
When the clock is stopped, one to four more clocks are still
observed as the delay line is flushed. When the clock is
restarted, the output clocks are not observed for one to four
clocks as the delay line is filled. The most common case is
two or three clocks.
Module 2 of 4
22
OBUF
IBUF
RST
LOCKED
ds022_028_121099
Figure 27: Standard DLL Implementation
Board Level De-Skew of Multiple Non-Virtex-E
Devices
The circuit shown in Figure 28 can be used to de-skew a
system clock between a Virtex-E chip and other non-Virtex-E chips on the same board. This application is commonly used when the Virtex-E device is used in conjunction
with other standard products such as SRAM or DRAM
devices. While designing the board level route, ensure that
the return net delay to the source equals the delay to the
other chips involved.
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Because any single DLL can access only two BUFGs at
most, any additional output clock signals must be routed
from the DLL in this example on the high speed backbone
routing.
Virtex-E Device
CLKDLL
IBUFG
CLKIN
OBUF
CLK0
CLK90
CLK180
CLK270
CLKFB
IBUFG
The dll_2x files in the xapp132.zip file show the VHDL and
Verilog implementation of this circuit.
CLK2X
Virtex-E 4x Clock
CLKDV
RST
LOCKED
BUFG
CLKDLL
CLKIN
Two DLLs located in the same half-edge (top-left, top-right,
bottom-right, bottom-left) can be connected together, without using a BUFG between the CLKDLLs, to generate a 4x
clock as shown in Figure 30. Virtex-E devices, like the Virtex
devices, have four clock networks that are available for internal de-skewing of the clock. Each of the eight DLLs have
access to two of the four clock networks. Although all the
DLLs can be used for internal de-skewing, the presence of
two GCLKBUFs on the top and two on the bottom indicate
that only two of the four DLLs on the top (and two of the four
DLLs on the bottom) can be used for this purpose.
CLK0
CLK90
CLK180
CLK270
CLKFB
CLK2X
CLKDV
RST
LOCKED
Non-Virtex-E Chip
CLKDLL-S
IBUFG
Non-Virtex-E Chip
CLKIN
CLKFB
Other Non_Virtex-E Chips
CLK0
CLK90
CLK180
CLK270
ds022_029_121099
CLK2X
Figure 28: DLL De-skew of Board Level Clock
CLKDV
RST
Board-level de-skew is not required for low-fanout clock networks. It is recommended for systems that have fanout limitations on the clock network, or if the clock distribution chip
cannot handle the load.
INV
LOCKED
CLKDLL-P
CLKIN
CLKFB
Do not use the DLL output clock signals until after activation
of the LOCKED signal. Prior to the activation of the
LOCKED signal, the DLL output clocks are not valid and
can exhibit glitches, spikes, or other spurious movement.
CLK0
CLK90
CLK180
CLK270
BUFG
CLK2X
CLKDV
RST
OBUF
LOCKED
The dll_mirror_1 files in the xapp132.zip file show the VHDL
and Verilog implementation of this circuit.
ds022_031_041901
De-Skew of Clock and Its 2x Multiple
The circuit shown in Figure 29 implements a 2x clock multiplier and also uses the CLK0 clock output with zero ns skew
between registers on the same chip. A clock divider circuit
could alternatively be implemented using similar connections.
Figure 30: DLL Generation of 4x Clock in Virtex-E
Devices
The dll_4xe files in the xapp 32.zip file show the DLL implementation in Verilog for Virtex-E devices. These files can be
found at:
ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip
CLKDLL
IBUFG
CLKIN
CLKFB
BUFG
CLK0
CLK90
CLK180
CLK270
Using Block SelectRAM+ Features
BUFG
CLK2X
CLKDV
IBUF
RST
OBUF
LOCKED
ds022_030_121099
Figure 29: DLL De-skew of Clock and 2x Multiple
DS025-2 (v2.1) July 17, 2002
The Virtex FPGA Series provides dedicated blocks of
on-chip, true dual-read/write port synchronous RAM, with
4096 memory cells. Each port of the block SelectRAM+
memory can be independently configured as a read/write
port, a read port, a write port, and can be configured to a
specific data width. block SelectRAM+ memory offers new
capabilities, allowing FPGA designers to simplify designs.
www.xilinx.com
1-800-255-7778
Module 2 of 4
23
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Operating Modes
RAMB4_S#_S#
Virtex-E block SelectRAM+ memory supports two operating
modes.
•
Read Through
•
Write Back
WEA
ENA
RSTA
CLKA
ADDRA[#:0]
DIA[#:0]
DOA[#:0]
Read Through (one clock edge)
The read address is registered on the read port clock edge
and data appears on the output after the RAM access time.
Some memories might place the latch/register at the outputs, depending on the desire to have a faster clock-to-out
versus set-up time. This is generally considered to be an
inferior solution, since it changes the read operation to an
asynchronous function with the possibility of missing an
address/control line transition during the generation of the read
pulse clock.
WEB
ENB
RSTB
CLKB
ADDRB[#:0]
DIB[#:0]
DOB[#:0]
ds022_032_121399
Figure 31: Dual-Port Block SelectRAM+ Memory
RAMB4_S#
Write Back (one clock edge)
WE
EN
RST
The write address is registered on the write port clock edge
and the data input is written to the memory and mirrored on
the output.
Block SelectRAM+ Characteristics
1. All inputs are registered with the port clock and have a
set-up to clock timing specification.
2. All outputs have a read through or write back function
depending on the state of the port WE pin. The outputs
relative to the port clock are available after the
clock-to-out timing specification.
3. The block SelectRAM elements are true SRAM
memories and do not have a combinatorial path from
the address to the output. The LUT SelectRAM+ cells in
the CLBs are still available with this function.
DO[#:0]
CLK
ADDR[#:0]
DI[#:0]
ds022_033_121399
Figure 32: Single-Port Block SelectRAM+ Memory
Table 14:
Available Library Primitives
Primitive
RAMB4_S1
Port A Width
Port B Width
1
N/A
RAMB4_S1_S1
1
RAMB4_S1_S2
2
RAMB4_S1_S4
4
4. The ports are completely independent from each other
(i.e., clocking, control, address, read/write function, and
data width) without arbitration.
RAMB4_S1_S8
8
RAMB4_S1_S16
16
5. A write operation requires only one clock edge.
RAMB4_S2
6. A read operation requires only one clock edge.
RAMB4_S2_S2
2
RAMB4_S2_S4
4
2
N/A
The output ports are latched with a self-timed circuit to guarantee a glitch-free read. The state of the output port does
not change until the port executes another read or write
operation.
RAMB4_S4
Library Primitives
RAMB4_S4_S4
4
RAMB4_S4_S8
8
RAMB4_S4_S16
16
Figure 31 and Figure 32 show the two generic library block
SelectRAM+ primitives. Table 14 describes all of the available primitives for synthesis and simulation.
RAMB4_S2_S8
8
RAMB4_S2_S16
16
RAMB4_S8
8
N/A
N/A
RAMB4_S8_S8
8
RAMB4_S8_S16
16
RAMB4_S16
RAMB4_S16_S16
Module 2 of 4
24
4
www.xilinx.com
1-800-255-7778
16
N/A
16
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Port Signals
Data Output Bus—DO[A|B]<#:0>
Each block SelectRAM+ port operates independently of the
others while accessing the same set of 4096 memory cells.
The data out bus reflects the contents of the memory cells
referenced by the address bus at the last active clock edge.
During a write operation, the data out bus reflects the data
in bus. The width of this bus equals the width of the port.
The allowed widths appear in Table 15.
Table 15 describes the depth and width aspect ratios for the
block SelectRAM+ memory.
Table 15:
Block SelectRAM+ Port Aspect Ratios
Inverting Control Pins
Width
Depth
ADDR Bus
Data Bus
1
4096
ADDR<11:0>
DATA<0>
2
2048
ADDR<10:0>
DATA<1:0>
4
1024
ADDR<9:0>
DATA<3:0>
Address Mapping
8
512
ADDR<8:0>
DATA<7:0>
16
256
ADDR<7:0>
DATA<15:0>
Each port accesses the same set of 4096 memory cells
using an addressing scheme dependent on the width of the
port. The physical RAM location addressed for a particular
width are described in the following formula (of interest only
when the two ports use different aspect ratios).
Clock—CLK[A|B]
Each port is fully synchronous with independent clock pins.
All port input pins have setup time referenced to the port
CLK pin. The data output bus has a clock-to-out time referenced to the CLK pin.
The four control pins (CLK, EN, WE and RST) for each port
have independent inversion control as a configuration option.
Start = ((ADDRport +1) * Widthport) –1
End = ADDRport * Widthport
Table 16 shows low order address mapping for each port
width.
Enable—EN[A|B]
The enable pin affects the read, write and reset functionality
of the port. Ports with an inactive enable pin keep the output
pins in the previous state and do not write data to the memory cells.
Table 16:
Port Address Mapping
Port
Port
Width
Addresses
Write Enable—WE[A|B]
1
4095...
1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
Activating the write enable pin allows the port to write to the
memory cells. When active, the contents of the data input
bus are written to the RAM at the address pointed to by the
address bus, and the new data also reflects on the data out
bus. When inactive, a read operation occurs and the contents of the memory cells referenced by the address bus
reflect on the data out bus.
2
2047...
07
4
1023...
8
511...
16
255...
Reset—RST[A|B]
The reset pin forces the data output bus latches to zero synchronously. This does not affect the memory cells of the
RAM and does not disturb a write operation on the other
port.
06
05
03
04
03
02
02
01
01
01
00
00
00
00
Creating Larger RAM Structures
The block SelectRAM+ columns have specialized routing to
allow cascading blocks together with minimal routing
delays. This achieves wider or deeper RAM structures with
a smaller timing penalty than when using normal routing
channels.
Address Bus—ADDR[A|B]<#:0>
Location Constraints
The address bus selects the memory cells for read or write.
The width of the port determines the required width of this
bus as shown in Table 15.
Block SelectRAM+ instances can have LOC properties
attached to them to constrain the placement. The block
SelectRAM+ placement locations are separate from the
CLB location naming convention, allowing the LOC properties to transfer easily from array to array.
Data In Bus—DI[A|B]<#:0>
The data in bus provides the new data value to be written
into the RAM. This bus and the port have the same width, as
shown in Table 15.
The LOC properties use the following form.
LOC = RAMB4_R#C#
RAMB4_R0C0 is the upper left RAMB4 location on the
device.
DS025-2 (v2.1) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 2 of 4
25
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
R
Conflict Resolution
The block SelectRAM+ memory is a true dual-read/write
port RAM that allows simultaneous access of the same
memory cell from both ports. When one port writes to a
given memory cell, the other port must not address that
memory cell (for a write or a read) within the clock-to-clock
setup window. The following lists specifics of port and memory cell write conflict resolution.
•
If both ports write to the same memory cell
simultaneously, violating the clock-to-clock setup
requirement, consider the data stored as invalid.
•
If one port attempts a read of the same memory cell
the other simultaneously writes, violating the
clock-to-clock setup requirement, the following occurs.
-
The write succeeds
-
The data out on the writing port accurately reflects
the data written.
-
The data out on the reading port is invalid.
Conflicts do not cause any physical damage.
Single Port Timing
Figure 33 shows a timing diagram for a single port of a block
SelectRAM+ memory. The block SelectRAM+ AC switching
characteristics are specified in the data sheet. The block
SelectRAM+ memory is initially disabled.
At the first rising edge of the CLK pin, the ADDR, DI, EN,
WE, and RST pins are sampled. The EN pin is High and the
WE pin is Low indicating a read operation. The DO bus contains the contents of the memory location, 0x00, as indicated by the ADDR bus.
At the second rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN and WE pins
are High indicating a write operation. The DO bus mirrors
the DI bus. The DI bus is written to the memory location
0x0F.
At the third rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN pin is High
Module 2 of 4
26
and the WE pin is Low indicating a read operation. The DO
bus contains the contents of the memory location 0x7E as
indicated by the ADDR bus.
At the fourth rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN pin is Low
indicating that the block SelectRAM+ memory is now disabled. The DO bus retains the last value.
Dual Port Timing
Figure 34 shows a timing diagram for a true dual-port
read/write block SelectRAM+ memory. The clock on port A
has a longer period than the clock on Port B. The timing
parameter TBCCS, (clock-to-clock set-up) is shown on this
diagram. The parameter, TBCCS is violated once in the diagram. All other timing parameters are identical to the single
port version shown in Figure 33.
TBCCS is only of importance when the address of both ports
are the same and at least one port is performing a write
operation. When the clock-to-clock set-up parameter is violated for a WRITE-WRITE condition, the contents of the
memory at that location are invalid. When the clock-to-clock
set-up parameter is violated for a WRITE-READ condition,
the contents of the memory are correct, but the read port
has invalid data. At the first rising edge of CLKA, memory
location 0x00 is to be written with the value 0xAAAA and is
mirrored on the DOA bus. The last operation of Port B was
a read to the same memory location 0x00. The DOB bus of
Port B does not change with the new value on Port A, and
retains the last read value. A short time later, Port B executes another read to memory location 0x00, and the DOB
bus now reflects the new memory value written by Port A.
At the second rising edge of CLKA, memory location 0x7E
is written with the value 0x9999 and is mirrored on the DOA
bus. Port B then executes a read operation to the same
memory location without violating the TBCCS parameter and
the DOB reflects the new memory values written by Port A.
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
TBPWH
TBPWL
CLK
TBACK
ADDR
00
0F
7E
8F
CCCC
BBBB
2222
TBDCK
DDDD
DIN
TBCKO
DOUT
MEM (00)
CCCC
MEM (7E)
TBECK
EN
RST
TBWCK
WE
DISABLED
READ
WRITE
READ
DISABLED
ds022_0343_121399
Figure 33: Timing Diagram for Single Port Block SelectRAM+ Memory
TBCCS
VIOLATION
CLK_A
PORT A
ADDR_A
00
EN_A
7E
0F
0F
7E
TBCCS
TBCCS
WE_A
DI_A
AAAA
DO_A
9999
AAAA
AAAA
1111
0000
9999
AAAA
UNKNOWN
2222
CLK_B
PORT B
ADDR_B
00
00
7E
0F
0F
7E
1A
1111
1111
1111
BBBB
1111
2222
FFFF
EN_B
WE_B
DI_B
DO_B
MEM (00)
AAAA
9999
BBBB
UNKNOWN
2222
FFFF
ds022_035_121399
Figure 34: Timing Diagram for a True Dual-port Read/Write Block SelectRAM+ Memory
At the third rising edge of CLKA, the TBCCS parameter is
violated with two writes to memory location 0x0F. The DOA
and DOB busses reflect the contents of the DIA and DIB
busses, but the stored value at 0x0F is invalid.
At the fourth rising edge of CLKA, a read operation is performed at memory location 0x0F and invalid data is present
DS025-2 (v2.1) July 17, 2002
on the DOA bus. Port B also executes a read operation to
memory location 0x0F and also reads invalid data.
At the fifth rising edge of CLKA a read operation is performed that does not violate the TBCCS parameter to the
previous write of 0x7E by Port B. THe DOA bus reflects the
recently written value by Port B.
www.xilinx.com
1-800-255-7778
Module 2 of 4
27
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Initialization
Design Examples
The block SelectRAM+ memory can initialize during the
device configuration sequence. The 16 initialization properties
of 64 hex values each (a total of 4096 bits) set the initialization
of each RAM. These properties appear in Table 17. Any initialization properties not explicitly set configure as zeros. Partial
initialization strings pad with zeros. Initialization strings
greater than 64 hex values generate an error. The RAMs can
be simulated with the initialization values using generics in
VHDL simulators and parameters in Verilog simulators.
Creating a 32-bit Single-Port RAM
Initialization in VHDL and Synopsys
The true dual-read/write port functionality of the block
SelectRAM+ memory allows a single port, 128 deep by
32-bit wide RAM to be created using a single block
SelectRAM+ cell as shown inTable 35.
Interleaving the memory space, setting the LSB of the
address bus of Port A to 1 (VCC), and the LSB of the
address bus of Port B to 0 (GND), allows a 32-bit wide single port RAM to be created.
The block SelectRAM+ structures can be initialized in VHDL
for both simulation and synthesis for inclusion in the EDIF
output file. The simulation of the VHDL code uses a generic
to pass the initialization. Synopsys FPGA compiler does not
presently support generics. The initialization values instead
attach as attributes to the RAM by a built-in Synopsys
dc_script. The translate_off statement stops synthesis
translation of the generic statements. The following code
illustrates a module that employs these techniques.
Table 17:
RAMB4_S16_S16
WE
EN
RST
CLK
ADDR[6:0], V CC
DI[31:16]
WEA
ENA
RSTA
CLKA
ADDRA[7:0]
DIA[15:0]
WE
EN
RST
CLK
ADDR[6:0], GND
DI[15:0]
WEB
ENB
RSTB
CLKB
ADDRB[7:0]
DIB[15:0]
DOA[15:0]
DO[31:16]
DOB[15:0]
DO[15:0]
RAM Initialization Properties
ds022_036_121399
Property
Memory Cells
INIT_00
255 to 0
INIT_01
511 to 256
Creating Two Single-Port RAMs
INIT_02
767 to 512
INIT_03
1023 to 768
The true dual-read/write port functionality of the block
SelectRAM+ memory allows a single RAM to be split into two
single port memories of 2K bits each as shown in Figure 36.
INIT_04
1279 to 1024
INIT_05
1535 to 1280
Figure 35: Single Port 128 x 32 RAM
RAMB4_S4_S16
WE1
EN1
RST1
CLK1
V CC , ADDR1[8:0]
DI1[3:0]
WEA
ENA
RSTA
CLKA
ADDRA[9:0]
DIA[3:0]
WE2
EN2
RST2
CLK2
GND, ADDR2[6:0]
DI2[15:0]
WEB
ENB
RSTB
CLKB
ADDRB[7:0]
DIB[15:0]
INIT_06
1791 to 2047
INIT_07
2047 to 1792
INIT_08
2303 to 2048
INIT_09
2559 to 2304
INIT_0a
2815 to 2560
INIT_0b
3071 to 2816
INIT_0c
3327 to 3072
INIT_0d
3583 to 3328
Figure 36: 512 x 4 RAM and 128 x 16 RAM
INIT_0e
3839 to 3584
INIT_0f
4095 to 3840
In this example, a 512K x 4 RAM (Port A) and a 128 x 16
RAM (Port B) are created out of a single block SelectRAM+.
The address space for the RAM is split by fixing the MSB of
Port A to 1 (VCC) for the upper 2K bits and the MSB of Port
B to 0 (GND) for the lower 2K bits.
DOA[3:0]
DO1[3:0]
DOB[15:0]
DO2[15:0]
ds022_037_121399
Initialization in Verilog and Synopsys
The block SelectRAM+ structures can be initialized in Verilog
for both simulation and synthesis for inclusion in the EDIF
output file. The simulation of the Verilog code uses a defparam to pass the initialization. The Synopsys FPGA compiler does not presently support defparam. The initialization
values instead attach as attributes to the RAM by a built-in
Synopsys dc_script. The translate_off statement stops synthesis translation of the defparam statements. The following
code illustrates a module that employs these techniques.
Module 2 of 4
28
Block Memory Generation
The CoreGen program generates memory structures using
the block SelectRAM+ features. This program outputs
VHDL or Verilog simulation code templates and an EDIF file
for inclusion in a design.
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
VHDL Initialization Example
library IEEE;
use IEEE.std_logic_1164.all;
entity MYMEM is
port (CLK, WE:in std_logic;
ADDR: in std_logic_vector(8 downto 0);
DIN: in std_logic_vector(7 downto 0);
DOUT: out std_logic_vector(7 downto 0));
end MYMEM;
architecture BEHAVE of MYMEM is
signal logic0, logic1: std_logic;
component RAMB4_S8
--synopsys translate_off
generic( INIT_00,INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0a, INIT_0b, INIT_0c, INIT_0d, INIT_0e, INIT_0f : BIT_VECTOR(255
downto 0)
:= X"0000000000000000000000000000000000000000000000000000000000000000");
--synopsys translate_on
port (WE, EN, RST, CLK: in STD_LOGIC;
ADDR: in STD_LOGIC_VECTOR(8 downto 0);
DI: in STD_LOGIC_VECTOR(7 downto 0);
DO: out STD_LOGIC_VECTOR(7 downto 0));
end component;
--synopsys dc_script_begin
--set_attribute ram0 INIT_00
"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string
--set_attribute ram0 INIT_01
"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string
--synopsys dc_script_end
begin
logic0 <=’0’;
logic1 <=’1’;
ram0: RAMB4_S8
--synopsys translate_off
generic map (
INIT_00 => X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF",
INIT_01 => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210")
--synopsys translate_on
port map (WE=>WE, EN=>logic1, RST=>logic0, CLK=>CLK,ADDR=>ADDR, DI=>DIN, DO=>DOUT);
end BEHAVE;
DS025-2 (v2.1) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 2 of 4
29
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Verilog Initialization Example
module MYMEM (CLK, WE, ADDR, DIN, DOUT);
input CLK, WE;
input [8:0] ADDR;
input [7:0] DIN;
output [7:0] DOUT;
wire logic0, logic1;
//synopsys dc_script_begin
//set_attribute ram0 INIT_00
"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string
//set_attribute ram0 INIT_01
"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string
//synopsys dc_script_end
assign logic0 = 1’b0;
assign logic1 = 1’b1;
RAMB4_S8 ram0 (.WE(WE), .EN(logic1), .RST(logic0), .CLK(CLK), .ADDR(ADDR), .DI(DIN),
.DO(DOUT));
//synopsys translate_off
defparam ram0.INIT_00 =
256h’0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF;
defparam ram0.INIT_01 =
256h’FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210;
//synopsys translate_on
endmodule
Using SelectI/O
The Virtex-E FPGA series includes a highly configurable,
high-performance I/O resource, called SelectI/O™ to provide support for a wide variety of I/O standards. The
SelectI/O resource is a robust set of features including programmable control of output drive strength, slew rate, and
input delay and hold time. Taking advantage of the flexibility
and SelectI/O features and the design considerations
described in this document can improve and simplify system level design.
Introduction
As FPGAs continue to grow in size and capacity, the larger
and more complex systems designed for them demand an
increased variety of I/O standards. Furthermore, as system
clock speeds continue to increase, the need for high performance I/O becomes more important. While chip-to-chip
delays have an increasingly substantial impact on overall
system speed, the task of achieving the desired system performance becomes more difficult with the proliferation of
low-voltage I/O standards.
SelectI/O, the revolutionary input/output resource of Virtex-E devices, has resolved this potential problem by providing a highly configurable, high-performance alternative to
the I/O resources of more conventional programmable
devices. The Virtex-E SelectI/O features combine the flexibility and time-to-market advantages of programmable logic
Module 2 of 4
30
with the high performance previously available only with
ASICs and custom ICs.
Each SelectI/O block can support up to 20 I/O standards.
Supporting such a variety of I/O standards allows the support
of a wide variety of applications, from general purpose standard applications to high-speed low-voltage memory busses.
SelectI/O blocks also provide selectable output drive
strengths and programmable slew rates for the LVTTL output buffers, as well as an optional, programmable weak
pull-up, weak pull-down, or weak “keeper” circuit ideal for
use in external bussing applications.
Each input/output block (IOB) includes three registers, one
each for the input, output, and 3-state signals within the
IOB. These registers are optionally configurable as either a
D-type flip-flop or as a level sensitive latch.
The input buffer has an optional delay element used to guarantee a zero hold time requirement for input signals registered within the IOB.
The Virtex-E SelectI/O features also provide dedicated
resources for input reference voltage (VREF) and output
source voltage (VCCO), along with a convenient banking
system that simplifies board design.
By taking advantage of the built-in features and wide variety
of I/O standards supported by the SelectI/O features, system-level design and board design can be greatly simplified
and improved.
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Fundamentals
Overview of Supported I/O Standards
Modern bus applications, pioneered by the largest and most
influential companies in the digital electronics industry, are
commonly introduced with a new I/O standard tailored specifically to the needs of that application. The bus I/O standards provide specifications to other vendors who create
products designed to interface with these applications.
Each standard often has its own specifications for current,
voltage, I/O buffering, and termination techniques.
This section provides a brief overview of the I/O standards
supported by all Virtex-E devices.
The ability to provide the flexibility and time-to-market
advantages of programmable logic is increasingly dependent on the capability of the programmable logic device to
support an ever increasing variety of I/O standards
LVTTL — Low-Voltage TTL
The SelectI/O resources feature highly configurable input
and output buffers which provide support for a wide variety
of I/O standards. As shown in Table 18, each buffer type can
support a variety of voltage requirements.
Table 18:
Virtex-E Supported I/O Standards
While most I/O standards specify a range of allowed voltages, this document records typical voltage values only.
Detailed information on each specification can be found on
the Electronic Industry Alliance Jedec website at:
http://www.jedec.org
The Low-Voltage TTL, or LVTTL standard is a general purpose EIA/JESDSA standard for 3.3 V applications that uses
an LVTTL input buffer and a Push-Pull output buffer. This
standard requires a 3.3 V output source voltage (VCCO), but
does not require the use of a reference voltage (VREF) or a
termination voltage (VTT).
LVCMOS2 — Low-Voltage CMOS for 2.5 Volts
The Low-Voltage CMOS for 2.5 Volts or lower, or LVCMOS2
standard is an extension of the LVCMOS standard (JESD
8.-5) used for general purpose 2.5 V applications. This standard requires a 2.5 V output source voltage (VCCO), but
does not require the use of a reference voltage (VREF) or a
board termination voltage (VTT).
I/O
Output
Input
Input
Standard
VCCO
VCCO
VREF
Board
Termination
Voltage (VTT)
LVTTL
3.3
3.3
N/A
N/A
LVCMOS2
2.5
2.5
N/A
N/A
LVCMOS18
1.8
1.8
N/A
N/A
SSTL3 I & II
3.3
N/A
1.50
1.50
This standard is an extension of the LVCMOS standard. It is
used in general purpose 1.8 V applications. The use of a
reference voltage (VREF) or a board termination voltage
(VTT) is not required.
SSTL2 I & II
2.5
N/A
1.25
1.25
PCI — Peripheral Component Interface
GTL
N/A
N/A
0.80
1.20
GTL+
N/A
N/A
1.0
1.50
HSTL I
1.5
N/A
0.75
0.75
HSTL III & IV
1.5
N/A
0.90
1.50
GTL — Gunning Transceiver Logic Terminated
CTT
3.3
N/A
1.50
1.50
AGP-2X
3.3
N/A
1.32
N/A
PCI33_3
3.3
3.3
N/A
N/A
The Gunning Transceiver Logic, or GTL standard is a
high-speed bus standard (JESD8.3) invented by Xerox. Xilinx has implemented the terminated variation for this standard. This standard requires a differential amplifier input
buffer and a Open Drain output buffer.
PCI66_3
3.3
3.3
N/A
N/A
GTL+ — Gunning Transceiver Logic Plus
BLVDS & LVDS
2.5
N/A
N/A
N/A
LVPECL
3.3
N/A
N/A
N/A
The Gunning Transceiver Logic Plus, or GTL+ standard is a
high-speed bus standard (JESD8.3) first used by the Pentium Pro processor.
LVCMOS18 — 1.8 V Low Voltage CMOS
The Peripheral Component Interface, or PCI standard specifies support for both 33 MHz and 66 MHz PCI bus applications. It uses a LVTTL input buffer and a Push-Pull output
buffer. This standard does not require the use of a reference
voltage (VREF) or a board termination voltage (VTT), however, it does require a 3.3 V output source voltage (VCCO).
HSTL — High-Speed Transceiver Logic
The High-Speed Transceiver Logic, or HSTL standard is a
general purpose high-speed, 1.5 V bus standard sponsored
by IBM (EIA/JESD 8-6). This standard has four variations or
classes. SelectI/O devices support Class I, III, and IV. This
DS025-2 (v2.1) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 2 of 4
31
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
standard requires a Differential Amplifier input buffer and a
Push-Pull output buffer.
SSTL3 — Stub Series Terminated Logic for 3.3V
The Stub Series Terminated Logic for 3.3 V, or SSTL3 standard is a general purpose 3.3 V memory bus standard also
sponsored by Hitachi and IBM (JESD8-8). This standard has
two classes, I and II. SelectI/O devices support both classes
for the SSTL3 standard. This standard requires a Differential
Amplifier input buffer and an Push-Pull output buffer.
SSTL2 — Stub Series Terminated Logic for 2.5V
The Stub Series Terminated Logic for 2.5 V, or SSTL2 standard is a general purpose 2.5 V memory bus standard
sponsored by Hitachi and IBM (JESD8-9). This standard
has two classes, I and II. SelectI/O devices support both
classes for the SSTL2 standard. This standard requires a
Differential Amplifier input buffer and an Push-Pull output
buffer.
Library Symbols
The Xilinx library includes an extensive list of symbols
designed to provide support for the variety of SelectI/O features. Most of these symbols represent variations of the five
generic SelectI/O symbols.
•
•
•
•
•
IBUF (input buffer)
IBUFG (global clock input buffer)
OBUF (output buffer)
OBUFT (3-state output buffer)
IOBUF (input/output buffer)
IBUF
Signals used as inputs to the Virtex-E device must source
an input buffer (IBUF) via an external input port. The generic
Virtex-E IBUF symbol appears in Figure 37. The extension
to the base name defines which I/O standard the IBUF
uses. The assumed standard is LVTTL when the generic
IBUF has no specified extension.
CTT — Center Tap Terminated
IBUF
The Center Tap Terminated, or CTT standard is a 3.3 V
memory bus standard sponsored by Fujitsu (JESD8-4).
This standard requires a Differential Amplifier input buffer
and a Push-Pull output buffer.
I
x133_01_111699
AGP-2X — Advanced Graphics Port
Figure 37: Input Buffer (IBUF) Symbols
The Intel AGP standard is a 3.3 V Advanced Graphics
Port-2X bus standard used with the Pentium II processor for
graphics applications. This standard requires a Push-Pull
output buffer and a Differential Amplifier input buffer.
LVDS — Low Voltage Differential Signal
LVDS is a differential I/O standard. It requires that one data
bit is carried through two signal lines. As with all differential
signaling standards, LVDS has an inherent noise immunity
over single-ended I/O standards. The voltage swing
between two signal lines is approximately 350 mV. The use
of a reference voltage (VREF) or a board termination voltage
(VTT) is not required. LVDS requires the use of two pins per
input or output. LVDS requires external resistor termination.
BLVDS — Bus LVDS
This standard allows for bidirectional LVDS communication
between two or more devices. The external resistor termination is different than the one for standard LVDS.
LVPECL — Low Voltage Positive Emitter Coupled
Logic
LVPECL is another differential I/O standard. It requires two
signal lines for transmitting one data bit. This standard
specifies two pins per input or output. The voltage swing
between these two signal lines is approximately 850 mV.
The use of a reference voltage (VREF) or a board termination voltage (VTT) is not required. The LVPECL standard
requires external resistor termination.
Module 2 of 4
32
O
The following list details the variations of the IBUF symbol:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IBUF
IBUF_LVCMOS2
IBUF_PCI33_3
IBUF_PCI66_3
IBUF_GTL
IBUF_GTLP
IBUF_HSTL_I
IBUF_HSTL_III
IBUF_HSTL_IV
IBUF_SSTL3_I
IBUF_SSTL3_II
IBUF_SSTL2_I
IBUF_SSTL2_II
IBUF_CTT
IBUF_AGP
IBUF_LVCMOS18
IBUF_LVDS
IBUF_LVPECL
When the IBUF symbol supports an I/O standard that
requires a VREF, the IBUF automatically configures as a differential amplifier input buffer. The VREF voltage must be
supplied on the VREF pins. In the case of LVDS, LVPECL,
and BLVDS, VREF is not required.
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
The voltage reference signal is “banked” within the Virtex-E
device on a half-edge basis such that for all packages there
are eight independent VREF banks internally. See Figure 38
for a representation of the Virtex-E I/O banks. Within each
bank approximately one of every six I/O pins is automatically configured as a VREF input. After placing a differential
amplifier input signal within a given VREF bank, the same
external source must drive all I/O pins configured as a VREF
input.
IBUF placement restrictions require that any differential
amplifier input signals within a bank be of the same standard. How to specify a specific location for the IBUF via the
LOC property is described below. Table 19 summarizes the
Virtex-E input standards compatibility requirements.
An optional delay element is associated with each IBUF.
When the IBUF drives a flip-flop within the IOB, the delay
element by default activates to ensure a zero hold-time
requirement. The NODELAY=TRUE property overrides this
default.
When the IBUF does not drive a flip-flop within the IOB, the
delay element de-activates by default to provide higher performance. To delay the input signal, activate the delay element with the DELAY=TRUE property.
Bank 1
GCLK3
Bank 2
Bank 7
Bank 0
GCLK2
GCLK1
Bank 5
Bank 3
Bank 6
Virtex-E
Device
GCLK0
Bank 4
Figure 38: Virtex-E I/O Banks
Rule 1
Xilinx Input Standards Compatibility
Requirements
Standards with the same input VCCO, output VCCO,
and VREF can be placed within the same bank.
IBUFG
Signals used as high fanout clock inputs to the Virtex-E
device should drive a global clock input buffer (IBUFG) via
an external input port in order to take advantage of one of
the four dedicated global clock distribution networks. The
output of the IBUFG symbol can only drive a CLKDLL,
DS025-2 (v2.1) July 17, 2002
IBUFG
I
O
x133_03_111699
Figure 39: Virtex-E Global Clock Input Buffer (IBUFG)
Symbol
The extension to the base name determines which I/O standard is used by the IBUFG. With no extension specified for
the generic IBUFG symbol, the assumed standard is
LVTTL.
The following list details variations of the IBUFG symbol.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IBUFG
IBUFG_LVCMOS2
IBUFG_PCI33_3
IBUFG_PCI66_3
IBUFG_GTL
IBUFG_GTLP
IBUFG_HSTL_I
IBUFG_HSTL_III
IBUFG_HSTL_IV
IBUFG_SSTL3_I
IBUFG_SSTL3_II
IBUFG_SSTL2_I
IBUFG_SSTL2_II
IBUFG_CTT
IBUFG_AGP
IBUFG_LVCMOS18
IBUFG_LVDS
IBUFG_LVPECL
When the IBUFG symbol supports an I/O standard that
requires a differential amplifier input, the IBUFG automatically configures as a differential amplifier input buffer. The
low-voltage I/O standards with a differential amplifier input
require an external reference voltage input VREF.
ds022_42_012100
Table 19:
CLKDLLHF, or a BUFG symbol. The generic Virtex-E
IBUFG symbol appears in Figure 39.
The voltage reference signal is “banked” within the Virtex-E
device on a half-edge basis such that for all packages there
are eight independent VREF banks internally. See Figure 38
for a representation of the Virtex-E I/O banks. Within each
bank approximately one of every six I/O pins is automatically configured as a VREF input. After placing a differential
amplifier input signal within a given VREF bank, the same
external source must drive all I/O pins configured as a VREF
input.
IBUFG placement restrictions require any differential amplifier input signals within a bank be of the same standard. The
LOC property can specify a location for the IBUFG.
www.xilinx.com
1-800-255-7778
Module 2 of 4
33
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
As an added convenience, the BUFGP can be used to
instantiate a high fanout clock input. The BUFGP symbol
represents a combination of the LVTTL IBUFG and BUFG
symbols, such that the output of the BUFGP can connect
directly to the clock pins throughout the design.
Unlike previous architectures, the Virtex-E BUFGP symbol
can only be placed in a global clock pad location. The LOC
property can specify a location for the BUFGP.
OBUF
An OBUF must drive outputs through an external output
port. The generic output buffer (OBUF) symbol appears in
Figure 40.
OBUF
I
O
x133_04_111699
Figure 40: Virtex-E Output Buffer (OBUF) Symbol
The extension to the base name defines which I/O standard
the OBUF uses. With no extension specified for the generic
OBUF symbol, the assumed standard is slew rate limited
LVTTL with 12 mA drive strength.
The LVTTL OBUF additionally can support one of two slew
rate modes to minimize bus transients. By default, the slew
rate for each output buffer is reduced to minimize power bus
transients when switching non-critical signals.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
OBUF_F_24
OBUF_LVCMOS2
OBUF_PCI33_3
OBUF_PCI66_3
OBUF_GTL
OBUF_GTLP
OBUF_HSTL_I
OBUF_HSTL_III
OBUF_HSTL_IV
OBUF_SSTL3_I
OBUF_SSTL3_II
OBUF_SSTL2_I
OBUF_SSTL2_II
OBUF_CTT
OBUF_AGP
OBUF_LVCMOS18
OBUF_LVDS
OBUF_LVPECL
The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS packages support four VCCO banks.
OBUF placement restrictions require that within a given
VCCO bank each OBUF share the same output source drive
voltage. Input buffers of any type and output buffers that do
not require VCCO can be placed within any VCCO bank.
Table 20 summarizes the Virtex-E output compatibility
requirements. The LOC property can specify a location for
the OBUF.
LVTTL output buffers have selectable drive strengths.
The format for LVTTL OBUF symbol names is as follows.
OBUF_<slew_rate>_<drive_strength>
<slew_rate> is either F (Fast), or S (Slow) and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).
Table 20:
Rule 1
Only outputs with standards that share compatible
VCCO can be used within the same bank.
Rule 2
There are no placement restrictions for outputs
with standards that do not require a VCCO.
VCCO
Compatible Standards
3.3
LVTTL, SSTL3_I, SSTL3_II, CTT, AGP, GTL,
GTL+, PCI33_3, PCI66_3
2.5
SSTL2_I, SSTL2_II, LVCMOS2, GTL, GTL+
1.5
HSTL_I, HSTL_III, HSTL_IV, GTL, GTL+
The following list details variations of the OBUF symbol.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
OBUF
OBUF_S_2
OBUF_S_4
OBUF_S_6
OBUF_S_8
OBUF_S_12
OBUF_S_16
OBUF_S_24
OBUF_F_2
OBUF_F_4
OBUF_F_6
OBUF_F_8
OBUF_F_12
OBUF_F_16
Module 2 of 4
34
Output Standards Compatibility
Requirements
OBUFT
The generic 3-state output buffer OBUFT, shown in
Figure 41, typically implements 3-state outputs or bidirectional I/O.
The extension to the base name defines which I/O standard
OBUFT uses. With no extension specified for the generic
OBUFT symbol, the assumed standard is slew rate limited
LVTTL with 12 mA drive strength.
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
The LVTTL OBUFT additionally can support one of two slew
rate modes to minimize bus transients. By default, the slew
rate for each output buffer is reduced to minimize power bus
transients when switching non-critical signals.
LVTTL 3-state output buffers have selectable drive
strengths.
The format for LVTTL OBUFT symbol names is as follows.
OBUFT_<slew_rate>_<drive_strength>
<slew_rate> can be either F (Fast), or S (Slow) and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).
T
OBUFT
I
O
x133_05_111699
Figure 41: 3-State Output Buffer Symbol (OBUFT)
The following list details variations of the OBUFT symbol.
• OBUFT
• OBUFT_S_2
• OBUFT_S_4
• OBUFT_S_6
• OBUFT_S_8
• OBUFT_S_12
• OBUFT_S_16
• OBUFT_S_24
• OBUFT_F_2
• OBUFT_F_4
• OBUFT_F_6
• OBUFT_F_8
• OBUFT_F_12
• OBUFT_F_16
• OBUFT_F_24
• OBUFT_LVCMOS2
• OBUFT_PCI33_3
• OBUFT_PCI66_3
• OBUFT_GTL
• OBUFT_GTLP
• OBUFT_HSTL_I
• OBUFT_HSTL_III
• OBUFT_HSTL_IV
• OBUFT_SSTL3_I
• OBUFT_SSTL3_II
• OBUFT_SSTL2_I
• OBUFT_SSTL2_II
• OBUFT_CTT
• OBUFT_AGP
• OBUFT_LVCMOS18
• OBUFT_LVDS
• OBUFT_LVPECL
DS025-2 (v2.1) July 17, 2002
The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS package supports four VCCO banks.
The SelectI/O OBUFT placement restrictions require that
within a given VCCO bank each OBUFT share the same output source drive voltage. Input buffers of any type and output buffers that do not require VCCO can be placed within
the same VCCO bank.
The LOC property can specify a location for the OBUFT.
3-state output buffers and bidirectional buffers can have
either a weak pull-up resistor, a weak pull-down resistor, or
a weak “keeper” circuit. Control this feature by adding the
appropriate symbol to the output net of the OBUFT (PULLUP, PULLDOWN, or KEEPER).
The weak “keeper” circuit requires the input buffer within the
IOB to sample the I/O signal. So, OBUFTs programmed for
an I/O standard that requires a VREF have automatic placement of a VREF in the bank with an OBUFT configured with
a weak “keeper” circuit. This restriction does not affect most
circuit design as applications using an OBUFT configured
with a weak “keeper” typically implement a bidirectional I/O.
In this case the IBUF (and the corresponding VREF) are
explicitly placed.
The LOC property can specify a location for the OBUFT.
IOBUF
Use the IOBUF symbol for bidirectional signals that require
both an input buffer and a 3-state output buffer with an
active high 3-state pin. The generic input/output buffer
IOBUF appears in Figure 42.
The extension to the base name defines which I/O standard
the IOBUF uses. With no extension specified for the generic
IOBUF symbol, the assumed standard is LVTTL input buffer
and slew rate limited LVTTL with 12 mA drive strength for
the output buffer.
The LVTTL IOBUF additionally can support one of two slew
rate modes to minimize bus transients. By default, the slew
rate for each output buffer is reduced to minimize power bus
transients when switching non-critical signals.
LVTTL bidirectional buffers have selectable output drive
strengths.
The format for LVTTL IOBUF symbol names is as follows.
IOBUF_<slew_rate>_<drive_strength>
<slew_rate> can be either F (Fast), or S (Slow) and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).
www.xilinx.com
1-800-255-7778
Module 2 of 4
35
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
T
I
The voltage reference signal is “banked” within the Virtex-E
device on a half-edge basis such that for all packages there
are eight independent VREF banks internally. See Figure 38
on page 33 for a representation of the Virtex-E I/O banks.
Within each bank approximately one of every six I/O pins is
automatically configured as a VREF input. After placing a differential amplifier input signal within a given VREF bank, the
same external source must drive all I/O pins configured as a
VREF input.
IOBUF
IO
O
x133_06_111699
Figure 42: Input/Output Buffer Symbol (IOBUF)
The following list details variations of the IOBUF symbol.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IOBUF
IOBUF_S_2
IOBUF_S_4
IOBUF_S_6
IOBUF_S_8
IOBUF_S_12
IOBUF_S_16
IOBUF_S_24
IOBUF_F_2
IOBUF_F_4
IOBUF_F_6
IOBUF_F_8
IOBUF_F_12
IOBUF_F_16
IOBUF_F_24
IOBUF_LVCMOS2
IOBUF_PCI33_3
IOBUF_PCI66_3
IOBUF_GTL
IOBUF_GTLP
IOBUF_HSTL_I
IOBUF_HSTL_III
IOBUF_HSTL_IV
IOBUF_SSTL3_I
IOBUF_SSTL3_II
IOBUF_SSTL2_I
IOBUF_SSTL2_II
IOBUF_CTT
IOBUF_AGP
IOBUF_LVCMOS18
IOBUF_LVDS
IOBUF_LVPECL
IOBUF placement restrictions require any differential amplifier input signals within a bank be of the same standard.
The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS package supports four VCCO banks.
Additional restrictions on the Virtex-E SelectI/O IOBUF
placement require that within a given VCCO bank each
IOBUF must share the same output source drive voltage.
Input buffers of any type and output buffers that do not
require VCCO can be placed within the same VCCO bank.
The LOC property can specify a location for the IOBUF.
An optional delay element is associated with the input path
in each IOBUF. When the IOBUF drives an input flip-flop
within the IOB, the delay element activates by default to
ensure a zero hold-time requirement. Override this default
with the NODELAY=TRUE property.
In the case when the IOBUF does not drive an input flip-flop
within the IOB, the delay element de-activates by default to
provide higher performance. To delay the input signal, activate the delay element with the DELAY=TRUE property.
3-state output buffers and bidirectional buffers can have
either a weak pull-up resistor, a weak pull-down resistor, or
a weak “keeper” circuit. Control this feature by adding the
appropriate symbol to the output net of the IOBUF (PULLUP, PULLDOWN, or KEEPER).
SelectI/O Properties
Access to some of the SelectI/O features (for example, location constraints, input delay, output drive strength, and slew
rate) is available through properties associated with these
features.
Input Delay Properties
An optional delay element is associated with each IBUF.
When the IBUF drives a flip-flop within the IOB, the delay
element activates by default to ensure a zero hold-time
requirement. Use the NODELAY=TRUE property to override this default.
When the IOBUF symbol used supports an I/O standard
that requires a differential amplifier input, the IOBUF automatically configures with a differential amplifier input buffer.
The low-voltage I/O standards with a differential amplifier
input require an external reference voltage input VREF.
Module 2 of 4
36
R
In the case when the IBUF does not drive a flip-flop within
the IOB, the delay element by default de-activates to provide higher performance. To delay the input signal, activate
the delay element with the DELAY=TRUE property.
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
IOB Flip-Flop/Latch Property
Design Considerations
The Virtex-E series I/O block (IOB) includes an optional register on the input path, an optional register on the output
path, and an optional register on the 3-state control pin. The
design implementation software automatically takes advantage of these registers when the following option for the Map
program is specified.
Reference Voltage (VREF) Pins
map -pr b <filename>
Alternatively, the IOB = TRUE property can be placed on a
register to force the mapper to place the register in an IOB.
Location Constraints
Specify the location of each SelectI/O symbol with the location constraint LOC attached to the SelectI/O symbol. The
external port identifier indicates the value of the location
constrain. The format of the port identifier depends on the
package chosen for the specific design.
The LOC properties use the following form.
Within each VREF bank, any input buffers that require a
VREF signal must be of the same type. Output buffers of any
type and input buffers can be placed without requiring a reference voltage within the same VREF bank.
Many of the low voltage I/O standards supported by
SelectI/O devices require a different output drive source
voltage (VCCO). As a result each device can often have to
support multiple output drive source voltages.
LOC=P37
Output Slew Rate Property
As mentioned above, a variety of symbol names provide the
option of choosing the desired slew rate for the output buffers. In the case of the LVTTL output buffers (OBUF, OBUFT,
and IOBUF), slew rate control can be alternatively programed with the SLEW= property. By default, the slew rate
for each output buffer is reduced to minimize power bus
transients when switching non-critical signals. The SLEW=
property has one of the two following values.
SLEW=SLOW
SLEW=FAST
Output Drive Strength Property
The desired output drive strength can be additionally specified by choosing the appropriate library symbol. The Xilinx
library also provides an alternative method for specifying
this feature. For the LVTTL output buffers (OBUF, OBUFT,
and IOBUF, the desired drive strength can be specified with
the DRIVE= property. This property could have one of the
following seven values.
DRIVE=4
The voltage reference signal is “banked” within the device on
a half-edge basis such that for all packages there are eight
independent VREF banks internally. See Figure 38 for a representation of the Virtex-E I/O banks. Within each bank
approximately one of every six I/O pins is automatically configured as a VREF input. After placing a differential amplifier
input signal within a given VREF bank, the same external
source must drive all I/O pins configured as a VREF input.
Output Drive Source Voltage (VCCO) Pins
LOC=A42
DRIVE=2
Low-voltage I/O standards with a differential amplifier input
buffer require an input reference voltage (VREF). Provide the
VREF as an external signal to the device.
The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS package supports four VCCO banks.
Output buffers within a given VCCO bank must share the
same output drive source voltage. Input buffers for LVTTL,
LVCMOS2, LVCMOS18, PCI33_3, and PCI 66_3 use the
VCCO voltage for Input VCCO voltage.
Transmission Line Effects
The delay of an electrical signal along a wire is dominated
by the rise and fall times when the signal travels a short distance. Transmission line delays vary with inductance and
capacitance, but a well-designed board can experience
delays of approximately 180 ps per inch.
Transmission line effects, or reflections, typically start at
1.5" for fast (1.5 ns) rise and fall times. Poor (or non-existent) termination or changes in the transmission line impedance cause these reflections and can cause additional
delay in longer traces. As system speeds continue to
increase, the effect of I/O delays can become a limiting factor and therefore transmission line termination becomes
increasingly more important.
DRIVE=6
Termination Techniques
DRIVE=8
A variety of termination techniques reduce the impact of
transmission line effects.
DRIVE=12 (Default)
DRIVE=16
DRIVE=24
DS025-2 (v2.1) July 17, 2002
The following are output termination techniques:
•
None
•
Series
•
Parallel (Shunt)
•
Series and Parallel (Series-Shunt)
www.xilinx.com
1-800-255-7778
Module 2 of 4
37
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Input termination techniques include the following:
Table 21:
•
None
•
Parallel (Shunt)
Guidelines for Maximum Number of
Simultaneously Switching Outputs per
Power/Ground Pair
These termination techniques can be applied in any combination. A generic example of each combination of termination methods appears in Figure 43.
Double Parallel Terminated
Unterminated
VTT
Package
Standard
BGA, FGA
LVTTL Slow Slew Rate, 2 mA drive
68
LVTTL Slow Slew Rate, 4 mA drive
41
LVTTL Slow Slew Rate, 6 mA drive
29
LVTTL Slow Slew Rate, 8 mA drive
22
LVTTL Slow Slew Rate, 12 mA drive
17
LVTTL Slow Slew Rate, 16 mA drive
14
LVTTL Slow Slew Rate, 24 mA drive
9
LVTTL Fast Slew Rate, 2 mA drive
40
LVTTL Fast Slew Rate, 4 mA drive
24
LVTTL Fast Slew Rate, 6 mA drive
17
LVTTL Fast Slew Rate, 8 mA drive
13
LVTTL Fast Slew Rate, 12 mA drive
10
LVTTL Fast Slew Rate, 16 mA drive
8
LVTTL Fast Slew Rate, 24 mA drive
5
LVCMOS2
10
PCI
8
GTL
4
GTL+
4
HSTL Class I
18
HSTL Class III
9
HSTL Class IV
5
SSTL2 Class I
15
SSTL2 Class II
10
SSTL3 Class I
11
SSTL3 Class II
7
CTT
14
AGP
9
VTT
Z=50
Z=50
VREF
Unterminated Output Driving
a Parallel Terminated Input
Series Terminated Output Driving
a Parallel Terminated Input
VTT
VTT
Z=50
Z=50
VREF
VREF
Series-Parallel Terminated Output
Driving a Parallel Terminated Input
Series Terminated Output
VTT
VTT
Z=50
Z=50
VREF
VREF
x133_07_111699
Figure 43: Overview of Standard Input and Output
Termination Methods
Simultaneous Switching Guidelines
Ground bounce can occur with high-speed digital ICs when
multiple outputs change states simultaneously, causing
undesired transient behavior on an output, or in the internal
logic. This problem is also referred to as the Simultaneous
Switching Output (SSO) problem.
Ground bounce is primarily due to current changes in the
combined inductance of ground pins, bond wires, and
ground metallization. The IC internal ground level deviates
from the external system ground level for a short duration (a
few nanoseconds) after multiple outputs change state
simultaneously.
Ground bounce affects stable Low outputs and all inputs
because they interpret the incoming signal by comparing it
to the internal ground. If the ground bounce amplitude
exceeds the actual instantaneous noise margin, then a
non-changing input can be interpreted as a short pulse with
a polarity opposite to the ground bounce.
Table 21 provides the guidelines for the maximum number
of simultaneously switching outputs allowed per output
power/ground pair to avoid the effects of ground bounce.
Refer to Table 22 for the number of effective output
power/ground pairs for each Virtex-E device and package
combination.
Note: This analysis assumes a 35 pF load for each output.
Table 22:
Virtex-E Extended Memory Family
Equivalent Power/Ground Pairs
Pkg/Part
XCV405E
BG560
FG676
XCV812E
56
56
FG900
Module 2 of 4
38
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Application Examples
Table 23:
Creating a design with the SelectI/O features requires the
instantiation of the desired library symbol within the design
code. At the board level, designers need to know the termination techniques required for each I/O standard.
GTL Voltage Specifications
Parameter
Min
Typ
Max
-
N/A
-
0.74
0.8
0.86
VCCO
VREF = N × VTT
1
This section describes some common application examples
illustrating the termination techniques recommended by
each of the standards supported by the SelectI/O features.
VTT
1.14
1.2
1.26
VIH = VREF + 0.05
0.79
0.85
-
Termination Examples
VIL = VREF – 0.05
-
0.75
0.81
Circuit examples involving typical termination techniques for
each of the SelectI/O standards follow. For a full range of
accepted values for the DC voltage specifications for each
standard, refer to the table associated with each figure.
VOH
-
-
-
VOL
-
0.2
0.4
IOH at VOH(mA)
-
-
-
The resistors used in each termination technique example
and the transmission lines depicted represent board level
components and are not meant to represent components
on the device.
IOLat VOL(mA) at 0.4V
32
-
-
IOLat VOL(mA) at 0.2V
-
-
40
GTL
Note: N must be greater than or equal to 0.653 and less than
or equal to 0.68.
GTL+
A sample circuit illustrating a valid termination technique for
GTL is shown in Figure 44. Table 23 lists DC voltage specifications.
A sample circuit illustrating a valid termination technique for
GTL+ appears in Figure 45. DC voltage specifications
appear in Table 24.
GTL+
VTT = 1.5V VTT = 1.5V
GTL
VTT = 1.2V
VTT = 1.2V
50Ω
50Ω
VCCO = N/A
50Ω
VCCO = N/A
50Ω
Z = 50
Z = 50
VREF = 1.0V
VREF = 0.8V
x133_09_012400
x133_08_111699
Figure 45: Terminated GTL+
Figure 44: Terminated GTL
Table 24:
GTL+ Voltage Specifications
Parameter
Min
Typ
Max
-
-
-
VREF = N × VTT1
0.88
1.0
1.12
VTT
1.35
1.5
1.65
VIH = VREF + 0.1
0.98
1.1
-
VIL = VREF – 0.1
-
0.9
1.02
VOH
-
-
-
VOL
0.3
0.45
0.6
-
-
-
IOLat VOL (mA) at 0.6V
36
-
-
IOLat VOL (mA) at 0.3V
-
-
48
VCCO
IOH at VOH (mA)
Note: N must be greater than or equal to 0.653 and less than
or equal to 0.68.
DS025-2 (v2.1) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 2 of 4
39
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
HSTL
A sample circuit illustrating a valid termination technique for
HSTL_I appears in Figure 46. A sample circuit illustrating a
valid termination technique for HSTL_III appears in
Figure 47.
HSTL Class I
VTT= 0.75V
VCCO = 1.5V
50Ω
Z = 50
VREF = 0.75V
x133_10_111699
Figure 46: Terminated HSTL Class I
Table 25:
Table 26:
Parameter
Min
Typ
Max
1.40
1.50
1.60
VREF (1)
-
0.90
-
VTT
-
VCCO
-
VIH
VREF + 0.1
-
-
VIL
-
-
VREF – 0.1
VOH
VCCO – 0.4
-
-
VOL
-
-
0.4
IOH at VOH (mA)
−8
-
-
IOLat VOL (mA)
24
-
-
VCCO
HSTL Class I Voltage Specification
Parameter
Min
Typ
Max
VCCO
1.40
1.50
1.60
VREF
0.68
0.75
0.90
VTT
-
VCCO × 0.5
-
VIH
VREF + 0.1
-
-
VIL
-
-
VREF – 0.1
VOH
VCCO – 0.4
-
-
VOL
HSTL Class III Voltage Specification
Note: Per EIA/JESD8-6, “The value of VREF is to be selected
by the user to provide optimum noise margin in the use
conditions specified by the user.”
A sample circuit illustrating a valid termination technique for
HSTL_IV appears in Figure 48.
HSTL Class IV
VCCO = 1.5V VTT= 1.5V VTT= 1.5V
50Ω
50Ω
Z = 50
VREF = 0.9V
0.4
x133_12_111699
IOH at VOH (mA)
−8
-
-
IOLat VOL (mA)
8
-
-
Figure 48: Terminated HSTL Class IV
Table 27:
Parameter
Min
Typ
Max
VCCO
1.40
1.50
1.60
VREF
-
0.90
-
VTT
-
VCCO
-
VIH
VREF + 0.1
-
-
VIL
-
-
VREF – 0.1
VOH
VCCO – 0.4
-
-
VOL
-
-
0.4
IOH at VOH (mA)
−8
-
-
IOLat VOL (mA)
48
-
-
HSTL Class III
VCCO = 1.5V
HSTL Class IV Voltage Specification
VTT= 1.5V
50Ω
Z = 50
VREF = 0.9V
x133_11_111699
Figure 47: Terminated HSTL Class III
Note: Per EIA/JESD8-6, “The value of VREF is to be selected
by the user to provide optimum noise margin in the use
conditions specified by the user.
Module 2 of 4
40
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
SSTL3_I
Table 29:
A sample circuit illustrating a valid termination technique for
SSTL3_I appears in Figure 49. DC voltage specifications
appear in Table 28.
SSTL3 Class I
VTT= 1.5V
VCCO = 3.3V
50Ω
25Ω
Z = 50
VREF = 1.5V
x133_13_111699
Figure 49: Terminated SSTL3 Class I
Table 28:
SSTL3_I Voltage Specifications
Parameter
Min
Typ
Max
VCCO
3.0
3.3
3.6
VREF = 0.45 × VCCO
1.3
1.5
1.7
VTT = VREF
1.3
1.5
1.7
VIH = VREF + 0.2
1.5
1.7
3.9(1)
VIL = VREF – 0.2
−0.3(2)
1.3
1.5
VOH = VREF + 0.6
1.9
-
-
VOL = VREF – 0.6
-
-
1.1
IOH at VOH (mA)
−8
-
-
IOLat VOL (mA)
8
-
-
SSTL3_II Voltage Specifications
Parameter
Min
Typ
Max
VCCO
3.0
3.3
3.6
VREF = 0.45 × VCCO
1.3
1.5
1.7
VTT = VREF
1.3
1.5
1.7
VIH = VREF + 0.2
1.5
1.7
3.9(1)
VIL= VREF – 0.2
−0.3(2)
1.3
1.5
VOH = VREF + 0.8
2.1
-
-
VOL= VREF – 0.8
-
-
0.9
IOH at VOH (mA)
−16
-
-
IOLat VOL (mA)
16
-
-
Notes:
1. VIH maximum is VCCO + 0.3
2. VIL minimum does not conform to the formula
SSTL2_I
A sample circuit illustrating a valid termination technique for
SSTL2_I appears in Figure 51. DC voltage specifications
appear in Table 30.
SSTL2 Class I
VTT= 1.25V
VCCO = 2.5V
50Ω
25Ω
Z = 50
V
REF
= 1.25V
xap133_15_011000
Figure 51: Terminated SSTL2 Class I
Notes:
1. VIH maximum is VCCO + 0.3
2. VIL minimum does not conform to the formula
Table 30:
SSTL2_I Voltage Specifications
Parameter
SSTL3_II
A sample circuit illustrating a valid termination technique for
SSTL3_II appears in Figure 50. DC voltage specifications
appear in Table 29.
25Ω
VREF = 0.5 × VCCO
Typ
Max
2.3
2.5
2.7
1.15
1.25
1.35
N(1)
1.11
1.25
1.39
VIH = VREF + 0.18
1.33
1.43
3.0(2)
VTT= 1.5V VTT= 1.5V
VIL = VREF – 0.18
−0.3(3)
1.07
1.17
50Ω
VOH = VREF + 0.61
1.76
-
-
VOL= VREF – 0.61
-
-
0.74
IOH at VOH (mA)
−7.6
-
-
IOLat VOL (mA)
7.6
-
-
SSTL3 Class II
VCCO = 3.3V
VCCO
Min
50Ω
Z = 50
VREF = 1.5V
x133_14_111699
Figure 50: Terminated SSTL3 Class II
VTT = VREF +
Notes:
1. N must be greater than or equal to –0.04 and less than or
equal to 0.04.
2. VIH maximum is VCCO + 0.3.
3. VIL minimum does not conform to the formula.
DS025-2 (v2.1) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 2 of 4
41
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
SSTL2_II
A sample circuit illustrating a valid termination technique for
SSTL2_II appears in Figure 52. DC voltage specifications
appear in Table 31.
SSTL2 Class II
VCCO = 2.5V
25Ω
VTT= 1.25V VTT= 1.25V
50Ω
50Ω
Z = 50
VREF = 1.25V
x133_16_111699
Figure 52: Terminated SSTL2 Class II
Table 31:
SSTL2_II Voltage Specifications
Parameter
Table 32:
CTT Voltage Specifications
Parameter
Min
Typ
Max
VCCO
2.05(1)
3.3
3.6
VREF
1.35
1.5
1.65
VTT
1.35
1.5
1.65
VIH = VREF + 0.2
1.55
1.7
-
VIL = VREF – 0.2
-
1.3
1.45
VOH = VREF + 0.4
1.75
1.9
-
VOL= VREF – 0.4
-
1.1
1.25
IOH at VOH (mA)
−8
-
-
IOLat VOL (mA)
8
-
-
Min
Typ
Max
VCCO
2.3
2.5
2.7
VREF = 0.5 × VCCO
1.15
1.25
1.35
PCI33_3 & PCI66_3
VTT = VREF + N (1)
1.11
1.25
1.39
PCI33_3 or PCI66_3 require no termination. DC voltage
specifications appear in Table 33.
VIH = VREF + 0.18
1.33
1.43
3.0(2)
VIL = VREF – 0.18
−0.3(3)
1.07
1.17
VOH = VREF + 0.8
1.95
-
-
VOL = VREF – 0.8
-
-
0.55
IOH at VOH (mA)
−15.2
-
IOLat VOL (mA)
15.2
-
Notes:
1. Timing delays are calculated based on VCCO min of 3.0V.
Table 33:
PCI33_3 and PCI66_3 Voltage
Specifications
Min
Typ
Max
VCCO
3.0
3.3
3.6
-
VREF
-
-
-
-
VTT
-
-
-
VIH = 0.5 × VCCO
1.5
1.65
VCCO+ 0.5
VIL = 0.3 × VCCO
−0.5
0.99
1.08
VOH = 0.9 × VCCO
2.7
-
-
VOL= 0.1 × VCCO
-
-
0.36
IOH at VOH (mA)
Note 1
-
-
IOLat VOL (mA)
Note 1
-
-
Notes:
1. N must be greater than or equal to –0.04 and less than or
equal to 0.04.
2. VIH maximum is VCCO + 0.3.
3. VIL minimum does not conform to the formula.
CTT
A sample circuit illustrating a valid termination technique for
CTT appear in Figure 53. DC voltage specifications appear
in Table 32.
Parameter
Note 1: Tested according to the relevant specification.
CTT
VCCO = 3.3V
VTT = 1.5V
50Ω
Z = 50
VREF= 1.5V
x133_17_111699
Figure 53: Terminated CTT
Module 2 of 4
42
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
LVTTL
LVCMOS18
LVTTL requires no termination. DC voltage specifications
appears in Table 34.
LVCMOS18 does not require termination. Table 36 lists DC
voltage specifications.
Table 34:
Table 36:
LVTTL Voltage Specifications
Parameter
Min
Typ
Max
VCCO
3.0
3.3
3.6
VREF
-
-
VTT
-
VIH
LVCMOS18 Voltage Specifications
Parameter
Min
Typ
Max
VCCO
1.70
1.80
1.90
-
VREF
-
-
-
-
-
VTT
-
-
-
2.0
-
3.6
VIH
0.7 x VCCO
-
1.95
VIL
−0.5
-
0.8
VIL
– 0.5
-
0.2 x VCCO
VOH
2.4
-
-
VOH
VCCO – 0.4
-
-
VOL
-
-
0.4
VOL
-
-
0.4
IOH at VOH (mA)
−24
-
-
IOH at VOH (mA)
–8
-
-
IOLat VOL (mA)
24
-
-
IOLat VOL (mA)
8
-
-
Note: VOLand VOH for lower drive currents sample tested.
AGP-2X
LVCMOS2
LVCMOS2 requires no termination. DC voltage specifications appear in Table 35.
The specification for the AGP-2X standard does not document a recommended termination technique. DC voltage
specifications appear in Table 37.
Table 35:
Table 37:
LVCMOS2 Voltage Specifications
AGP-2X Voltage Specifications
Min
Typ
Max
VCCO
3.0
3.3
3.6
-
VREF = N × VCCO(1)
1.17
1.32
1.48
-
-
VTT
-
-
-
1.7
-
3.6
VIH = VREF + 0.2
1.37
1.52
-
VIL
−0.5
-
0.7
VIL = VREF – 0.2
-
1.12
1.28
VOH
1.9
-
-
VOH = 0.9 × VCCO
2.7
3.0
-
VOL
-
-
0.4
VOL = 0.1 × VCCO
-
0.33
0.36
IOH at VOH (mA)
−12
-
-
IOH at VOH (mA)
Note 2
-
-
IOLat VOL (mA)
12
-
-
IOLat VOL (mA)
Note 2
-
-
Parameter
Min
Typ
Max
VCCO
2.3
2.5
2.7
VREF
-
-
VTT
-
VIH
Parameter
Notes:
1. N must be greater than or equal to 0.39 and less than or
equal to 0.41.
2. Tested according to the relevant specification.
DS025-2 (v2.1) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 2 of 4
43
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
LVDS
LVPECL
Depending on whether the device is transmitting an LVDS
signal or receiving an LVDS signal, there are two different
circuits used for LVDS termination. A sample circuit illustrating a valid termination technique for transmitting LVDS signals appears in Figure 54. A sample circuit illustrating a
valid termination for receiving LVDS signals appears in
Figure 55. Table 38 lists DC voltage specifications. Further
information on the specific termination resistor packs shown
can be found on Table 40.
Depending on whether the device is transmitting or receiving an LVPECL signal, two different circuits are used for
LVPECL termination. A sample circuit illustrating a valid termination technique for transmitting LVPECL signals
appears in Figure 56. A sample circuit illustrating a valid termination for receiving LVPECL signals appears in
Figure 57. Table 39 lists DC voltage specifications. Further
information on the specific termination resistor packs shown
can be found on Table 40.
Virtex-E
FPGA
Q
2.5V
RS
Q
3.3V
Z0 = 50Ω
RS
Q
RS
RDIV
140
Q
Z0 = 50Ω
RS
Z0 = 50Ω LVPECL_OUT
to LVPECL Receiver
100
DATA
Transmit
to LVDS Receiver
165
DATA
Transmit
1/4 of Bourns
Part Number
CAT16-PC4F12
Virtex-E
FPGA
1/4 of Bourns
Part Number
CAT16-LV4F12
RDIV
187
Z0 = 50Ω
100
to LVPECL Receiver
LVPECL_OUT
to LVDS Receiver
165
x133_20_122799
VCCO = 2.5V
LVDS
Output
Figure 56: Transmitting LVPECL Signal Circuit
x133_19_122799
Figure 54: Transmitting LVDS Signal Circuit
Q
Q
Z0 = 50Ω
from
LVDS
Driver
VIRTEX-E
FPGA
LVDS_IN
+
from
LVPECL
Driver
RT
100Ω
Z0 = 50Ω
+
RT
100Ω
Z0 = 50Ω
Q
DATA
Receive
–
VIRTEX-E
FPGA
Z0 = 50Ω LVPECL_IN
DATA
Receive
–
LVPECL_IN
x133_21_122799
Q
LVDS_IN
Figure 57: Receiving LVPECL Signal Circuit
x133_29_122799
Figure 55: Receiving LVDS Signal Circuit
Table 39:
LVPECL Voltage Specifications
Parameter
Table 38:
LVDS Voltage Specifications
Parameter
Min
Typ
Max
2.375
2.5
2.625
VICM(2)
0.2
1.25
2.2
VOCM(1)
1.125
1.25
1.375
VIDIFF (1)
0.1
0.35
-
VODIFF (1)
0.25
0.35
0.45
VOH(1)
1.25
-
-
VOL(1)
-
-
1.25
VCCO
Min
Typ
Max
VCCO
3.0
3.3
3.6
VREF
-
-
-
VTT
-
-
-
VIH
1.49
-
2.72
VIL
0.86
-
2.125
VOH
1.8
-
-
VOL
-
-
1.57
Note: For more detailed information, see LVPECL DC
Specifications
Notes:
1. Measured with a 100 Ω resistor across Q and Q.
2. Measured with a differential input voltage = +/− 350 mV.
Module 2 of 4
44
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Termination Resistor Packs
HDL Instantiation
Resistor packs are available with the values and the configuration required for LVDS and LVPECL termination from
Bourns, Inc., as listed in Table. For pricing and availability,
please contact Bourns directly at www.bourns.com.
Only one global clock input buffer is required to be instantiated in the design and placed on the correct GCLKPAD
location. The N-side of the buffer is reserved and no other
IOB is allowed to be placed on this location.
I/O Standard
Term.
for:
Pairs/
Pack
Pins
CAT16−LV2F6
LVDS
Driver
2
8
In the physical device, a configuration option is enabled that
routes the pad wire to the differential input buffer located in
the GCLKIOB. The output of this buffer then drives the output of the GCLKIOB cell. In EPIC it appears that the second
buffer is unused. Any attempt to use this location for another
purpose leads to a DRC error in the software.
CAT16−LV4F12
LVDS
Driver
4
16
VHDL Instantiation
CAT16−PC2F6
LVPECL
Driver
2
8
CAT16−PC4F12
LVPECL
Driver
4
16
CAT16−PT2F2
LVDS/LVPECL
Receiver
2
8
CAT16−PT4F4
LVDS/LVPECL
Receiver
4
16
Table 40:
Bourns LVDS/LVPECL Resistor Packs
Part Number
gclk0_p : IBUFG_LVDS port map
(I=>clk_external, O=>clk_internal);
Verilog Instantiation
IBUFG_LVDS gclk0_p (.I(clk_external),
.O(clk_internal));
Location Constraints
LVDS Design Guide
The SelectI/O library elements have been expanded for Virtex-E devices to include new LVDS variants. At this time all
of the cells might not be included in the Synthesis libraries.
The 2.1i-Service Pack 2 update for Alliance and Foundation
software includes these cells in the VHDL and Verilog libraries. It is necessary to combine these cells to create the
P-side (positive) and N-side (negative) as described in the
input, output, 3-state and bidirectional sections.
IBUF_LVDS
I
OBUF_LVDS
O
I
IOBUF_LVDS
T
O
I
IBUFG_LVDS
I
OBUFT_LVDS
T
O
I
IO
O
All LVDS buffers must be explicitly placed on a device. For
the global clock input buffers this can be done with the following constraint in the UCF or NCF file.
NET clk_external LOC = GCLKPAD3;
GCLKPAD3 can also be replaced with the package pin
name, such as D17 for the BG432 package.
Optional N-Side
Some designers might prefer to also instantiate the N-side
buffer for the global clock buffer. This allows the top-level net
list to include net connections for both PCB layout and system-level integration. In this case, only the output P-side
IBUFG connection has a net connected to it. Since the
N-side IBUFG does not have a connection in the EDIF net
list, it is trimmed from the design in MAP.
O
VHDL Instantiation
x133_22_122299
gclk0_p : IBUFG_LVDS port map
(I=>clk_p_external, O=>clk_internal);
Figure 58: LVDS Elements
gclk0_n : IBUFG_LVDS port map
(I=>clk_n_external, O=>clk_internal);
Creating LVDS Global Clock Input Buffers
The global clock input buffer can be combined with the adjacent IOB to form an LVDS clock input buffer. The P-side
resides in the GCLKPAD location and the N-side resides in
the adjacent IO_LVDS_DLL site.
Table 41:
Global Clock Input Buffer Pair Locations
Pair 3
Pair 2
Pair 2
Pair 0
Pkg
P
N
P
N
P
N
P
N
BG560
A17
C18
D17
E17
AJ17
AM18
AL17
AM17
FG676
E13
B13
C13
F14
AB13
AF13
AA14
AC14
FG900
C15
A15
E15
E16
AK16
AH16
AJ16
AF16
Verilog Instantiation
IBUFG_LVDS gclk0_p (.I(clk_p_external),
.O(clk_internal));
IBUFG_LVDS gclk0_n (.I(clk_n_external),
.O(clk_internal));
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the global clock input buffers this can be done with the following constraint in the UCF or NCF file.
NET clk_p_external LOC = GCLKPAD3;
NET clk_n_external LOC = C17;
DS025-2 (v2.1) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 2 of 4
45
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
GCLKPAD3 can also be replaced with the package pin
name, such as D17 for the BG432 package.
Creating LVDS Input Buffers
An LVDS input buffer can be placed in a wide number of IOB
locations. The exact location is dependent on the package
that is used. The Virtex-E package information lists the possible locations as IO_L#P for the P-side and IO_L#N for the
N-side where # is the pair number.
HDL Instantiation
Only one input buffer is required to be instantiated in the
design and placed on the correct IO_L#P location. The
N-side of the buffer is reserved and no other IOB is allowed
to be placed on this location. In the physical device, a configuration option is enabled that routes the pad wire from the
IO_L#N IOB to the differential input buffer located in the
IO_L#P IOB. The output of this buffer then drives the output
of the IO_L#P cell or the input register in the IO_L#P IOB. In
EPIC it appears that the second buffer is unused. Any
attempt to use this location for another purpose leads to a
DRC error in the software.
VHDL Instantiation
data0_p : IBUF_LVDS port map (I=>data(0),
O=>data_int(0));
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the global clock input buffers this can be done with the following constraint in the UCF or NCF file.
NET data_p<0> LOC = D28; # IO_L0P
NET data_n<0> LOC = B29; # IO_L0N
Adding an Input Register
All LVDS buffers can have an input register in the IOB. The
input register is in the P-side IOB only. All the normal IOB
register options are available (FD, FDE, FDC, FDCE, FDP,
FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE,
LDP, LDPE). The register elements can be inferred or
explicitly instantiated in the HDL code.
The register elements can be packed in the IOB using the
IOB property to TRUE on the register or by using “map -pr
[i|o|b]”, where “i” is inputs only, “o” is outputs only, and “b” is
both inputs and outputs.
To improve design coding times VHDL and Verilog synthesis macro libraries available to explicitly create these structures. The input library macros are listed in Table 42. The I
and IB inputs to the macros are the external net connections.
Table 42:
Verilog Instantiation
Input Library Macros
Name
IBUF_LVDS data0_p (.I(data[0]),
.O(data_int[0]));
Inputs
Outputs
I, IB, C
Q
IBUFDS_FDE_LVDS
I, IB, CE, C
Q
IBUFDS_FDC_LVDS
I, IB, C, CLR
Q
I, IB, CE, C, CLR
Q
I, IB, C, PRE
Q
I, IB, CE, C, PRE
Q
I, IB, C, R
Q
I, IB, CE, C, R
Q
I, IB, C, S
Q
I, IB, CE, C, S
Q
I, IB, G
Q
IBUFDS_LDE_LVDS
I, IB, GE, G
Q
IBUFDS_LDC_LVDS
I, IB, G, CLR
Q
I, IB, GE, G, CLR
Q
I, IB, G, PRE
Q
I, IB, GE, G, PRE
Q
IBUFDS_FD_LVDS
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the input buffers this can be done with the following constraint in the UCF or NCF file.
NET data<0> LOC = D28; # IO_L0P
IBUFDS_FDCE_LVDS
IBUFDS_FDP_LVDS
Optional N-side
IBUFDS_FDPE_LVDS
Some designers might prefer to also instantiate the N-side
buffer for the input buffer. This allows the top-level net list to
include net connections for both PCB layout and system-level integration. In this case, only the output P-side
IBUF connection has a net connected to it. Since the N-side
IBUF does not have a connection in the EDIF net list, it is
trimmed from the design in MAP.
VHDL Instantiation
IBUFDS_FDR_LVDS
IBUFDS_FDRE_LVDS
IBUFDS_FDS_LVDS
IBUFDS_FDSE_LVDS
IBUFDS_LD_LVDS
data0_p : IBUF_LVDS port map
(I=>data_p(0), O=>data_int(0));
data0_n : IBUF_LVDS port map
(I=>data_n(0), O=>open);
IBUFDS_LDCE_LVDS
Verilog Instantiation
IBUFDS_LDP_LVDS
IBUF_LVDS data0_p (.I(data_p[0]),
.O(data_int[0]));
IBUFDS_LDPE_LVDS
IBUF_LVDS data0_n (.I(data_n[0]), .O());
Module 2 of 4
46
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Creating LVDS Output Buffers
LVDS output buffer can be placed in wide number of IOB
locations. The exact location are dependent on the package
that is used. The Virtex-E package information lists the possible locations as IO_L#P for the P-side and IO_L#N for the
N-side where # is the pair number.
HDL Instantiation
Both output buffers are required to be instantiated in the
design and placed on the correct IO_L#P and IO_L#N locations. The IOB must have the same net source the following
pins, clock (C), set/reset (SR), output (O), output clock
enable (OCE). In addition, the output (O) pins must be
inverted with respect to each other, and if output registers
are used, the INIT states must be opposite values (one
HIGH and one LOW). Failure to follow these rules leads to
DRC errors in software.
VHDL Instantiation
data0_p : OBUF_LVDS port map
(I=>data_int(0),
O=>data_p(0));
data0_inv: INV
(I=>data_int(0),
port map
O=>data_n_int(0));
data0_n : OBUF_LVDS port map
(I=>data_n_int(0), O=>data_n(0));
Verilog Instantiation
OBUF_LVDS data0_p
.O(data_p[0]));
Adding an Output Register
All LVDS buffers can have an output register in the IOB. The
output registers must be in both the P-side and N-side IOBs.
All the normal IOB register options are available (FD, FDE,
FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD,
LDE, LDC, LDCE, LDP, LDPE). The register elements can
be inferred or explicitly instantiated in the HDL code.
Special care must be taken to insure that the D pins of the
registers are inverted and that the INIT states of the registers are opposite. The clock pin (C), clock enable (CE) and
set/reset (CLR/PRE or S/R) pins must connect to the same
source. Failure to do this leads to a DRC error in the software.
The register elements can be packed in the IOB using the
IOB property to TRUE on the register or by using the “map
-pr [i|o|b]” where “i” is inputs only, “o” is outputs only and “b”
is both inputs and outputs.
To improve design coding times VHDL and Verilog synthesis macro libraries have been developed to explicitly create
these structures. The output library macros are listed in
Table 43. The O and OB inputs to the macros are the external net connections.
Table 43:
(.I(data_int[0]),
Output Library Macros
Name
Inputs
Outputs
D, C
O, OB
OBUFDS_FDE_LVDS
DD, CE, C
O, OB
OBUFDS_FDC_LVDS
D, C, CLR
O, OB
D, CE, C, CLR
O, OB
D, C, PRE
O, OB
D, CE, C, PRE
O, OB
D, C, R
O, OB
D, CE, C, R
O, OB
D, C, S
O, OB
D, CE, C, S
O, OB
D, G
O, OB
OBUFDS_LDE_LVDS
D, GE, G
O, OB
OBUFDS_LDC_LVDS
D, G, CLR
O, OB
D, GE, G, CLR
O, OB
D, G, PRE
O, OB
D, GE, G, PRE
O, OB
OBUFDS_FD_LVDS
INV
data0_inv (.I(data_int[0],
.O(data_n_int[0]);
OBUF_LVDS data0_n
.O(data_n[0]));
some point in the product lifetime, then only the common
pairs for all packages should be used.
(.I(data_n_int[0]),
OBUFDS_FDCE_LVDS
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the output buffers this can be done with the following constraint in the UCF or NCF file.
NET data_p<0> LOC = D28; # IO_L0P
OBUFDS_FDP_LVDS
OBUFDS_FDPE_LVDS
OBUFDS_FDR_LVDS
OBUFDS_FDRE_LVDS
NET data_n<0> LOC = B29; # IO_L0N
Synchronous vs. Asynchronous Outputs
OBUFDS_FDS_LVDS
If the outputs are synchronous (registered in the IOB), then
any IO_L#P|N pair can be used. If the outputs are asynchronous (no output register), then they must use one of the
pairs that are part of the same IOB group at the end of a
ROW or at the top/bottom of a COLUMN in the device.
OBUFDS_FDSE_LVDS
The LVDS pairs that can be used as asynchronous outputs
are listed in the Virtex-E pinout tables. Some pairs are
marked as asynchronous-capable for all devices in that
package, and others are marked as available only for that
device in the package. If the device size might change at
DS025-2 (v2.1) July 17, 2002
OBUFDS_LD_LVDS
OBUFDS_LDCE_LVDS
OBUFDS_LDP_LVDS
OBUFDS_LDPE_LVDS
www.xilinx.com
1-800-255-7778
Module 2 of 4
47
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Creating LVDS Output 3-State Buffers
LVDS output 3-state buffers can be placed in a wide number
of IOB locations. The exact locations are dependent on the
package used. The Virtex-E package information lists the
possible locations as IO_L#P for the P-side and IO_L#N for
the N-side, where # is the pair number.
HDL Instantiation
Adding Output and 3-State Registers
Both output 3-state buffers are required to be instantiated in
the design and placed on the correct IO_L#P and IO_L#N
locations. The IOB must have the same net source the following pins, clock (C), set/reset (SR), 3-state (T), 3-state
clock enable (TCE), output (O), output clock enable (OCE).
In addition, the output (O) pins must be inverted with
respect to each other, and if output registers are used, the
INIT states must be opposite values (one High and one
Low). If 3-state registers are used, they must be initialized to
the same state. Failure to follow these rules leads to DRC
errors in the software.
VHDL Instantiation
data0_p:
OBUFT_LVDS port map
(I=>data_int(0), T=>data_tri,
O=>data_p(0));
All LVDS buffers can have an output register in the IOB. The
output registers must be in both the P-side and N-side IOBs.
All the normal IOB register options are available (FD, FDE,
FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD,
LDE, LDC, LDCE, LDP, LDPE). The register elements can
be inferred or explicitly instantiated in the HDL code.
Special care must be taken to insure that the D pins of the
registers are inverted and that the INIT states of the registers are opposite. The 3-state (T), 3-state clock enable
(CE), clock pin (C), output clock enable (CE) and set/reset
(CLR/PRE or S/R) pins must connect to the same source.
Failure to do this leads to a DRC error in the software.
The register elements can be packed in the IOB using the
IOB property to TRUE on the register or by using the “map
-pr [i|o|b]” where “i” is inputs only, “o” is outputs only and “b”
is both inputs and outputs.
data0_inv: INV port map
(I=>data_int(0), O=>data_n_int(0));
data0_n:
OBUFT_LVDS port map
(I=>data_n_int(0), T=>data_tri,
O=>data_n(0));
Verilog Instantiation
OBUFT_LVDS data0_p
(.I(data_int[0]),
.T(data_tri), .O(data_p[0]));
INV
data0_inv (.I(data_int[0],
.O(data_n_int[0]);
OBUFT_LVDS data0_n
(.I(data_n_int[0]),
.T(data_tri), .O(data_n[0]));
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the output buffers this can be done with the following constraint in the UCF or NCF file.
NET data_p<0> LOC = D28; # IO_L0P
NET data_n<0> LOC = B29; # IO_L0N
Synchronous vs. Asynchronous 3-State Outputs
If the outputs are synchronous (registered in the IOB), then
any IO_L#P|N pair can be used. If the outputs are asynchronous (no output register), then they must use one of the
pairs that are part of the same IOB group at the end of a
ROW or at the top/bottom of a COLUMN in the device. This
applies for either the 3-state pin or the data out pin.
Module 2 of 4
48
LVDS pairs that can be used as asynchronous outputs are
listed in the Virtex-E pinout tables. Some pairs are marked
as “asynchronous capable” for all devices in that package,
and others are marked as available only for that device in
the package. If the device size might be changed at some
point in the product lifetime, then only the common pairs for
all packages should be used.
To improve design coding times VHDL and Verilog synthesis macro libraries have been developed to explicitly create
these structures. The input library macros are listed below.
The 3-state is configured to be 3-stated at GSR and when
the PRE,CLR,S or R is asserted and shares it's clock
enable with the output register. If this is not desirable, the
library can be updated by the user for the desired functionality. The O and OB inputs to the macros are the external
net connections.
Creating LVDS Bidirectional Buffer
LVDS bidirectional buffers can be placed in a wide number
of IOB locations. The exact locations are dependent on the
package used. The Virtex-E package information lists the
possible locations as IO_L#P for the P-side and IO_L#N for
the N-side, where # is the pair number.
HDL Instantiation
Both bidirectional buffers are required to be instantiated in
the design and placed on the correct IO_L#P and IO_L#N
locations. The IOB must have the same net source the following pins, clock (C), set/reset (SR), 3-state (T), 3-state
clock enable (TCE), output (O), output clock enable (OCE).
In addition, the output (O) pins must be inverted with
respect to each other, and if output registers are used, the
INIT states must be opposite values (one HIGH and one
LOW). If 3-state registers are used, they must be initialized
to the same state. Failure to follow these rules leads to DRC
errors in the software.
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
The LVDS pairs that can be used as asynchronous bidirectional buffers are listed in the Virtex-E pinout tables. Some
pairs are marked as asynchronous capable for all devices in
that package, and others are marked as available only for
that device in the package. If the device size might change
at some point in the product’s lifetime, then only the common pairs for all packages should be used.
VHDL Instantiation
data0_p:
IOBUF_LVDS port map
(I=>data_out(0), T=>data_tri,
IO=>data_p(0), O=>data_int(0));
data0_inv: INV
(I=>data_out(0),
port map
O=>data_n_out(0));
data0_n : IOBUF_LVDS port map
(I=>data_n_out(0), T=>data_tri,
IO=>data_n(0), O=>open);
Adding Output and 3-State Registers
Verilog Instantiation
IOBUF_LVDS data0_p(.I(data_out[0]),
.T(data_tri), .IO(data_p[0]),
.O(data_int[0]);
INV
data0_inv (.I(data_out[0],
.O(data_n_out[0]);
IOBUF_LVDS
data0_n(.I(data_n_out[0]),.T(data_tri),.
IO(data_n[0]).O());
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the output buffers this can be done with the following constraint in the UCF or NCF file.
NET data_p<0> LOC = D28; # IO_L0P
NET data_n<0> LOC = B29; # IO_L0N
Synchronous vs. Asynchronous Bidirectional
Buffers
If the output side of the bidirectional buffers are synchronous (registered in the IOB), then any IO_L#P|N pair can be
used. If the output side of the bidirectional buffers are asynchronous (no output register), then they must use one of the
pairs that is a part of the asynchronous LVDS IOB group.
This applies for either the 3-state pin or the data out pin.
Table 44:
All LVDS buffers can have output and input registers in the
IOB. The output registers must be in both the P-side and
N-side IOBs, the input register is only in the P-side. All the
normal IOB register options are available (FD, FDE, FDC,
FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD, LDE,
LDC, LDCE, LDP, LDPE). The register elements can be
inferred or explicitly instantiated in the HDL code. Special
care must be taken to insure that the D pins of the registers
are inverted and that the INIT states of the registers are
opposite. The 3-state (T), 3-state clock enable (CE), clock
pin (C), output clock enable (CE), and set/reset (CLR/PRE
or S/R) pins must connect to the same source. Failure to do
this leads to a DRC error in the software.
The register elements can be packed in the IOB using the
IOB property to TRUE on the register or by using the “map
-pr [i|o|b]”, where “i” is inputs only, “o” is outputs only, and “b”
is both inputs and outputs. To improve design coding times,
VHDL and Verilog synthesis macro libraries have been
developed to explicitly create these structures. The bidirectional I/O library macros are listed in Table 44.
The 3-state is configured to be 3-stated at GSR and when
the PRE, CLR, S, or R is asserted and shares its clock
enable with the output and input register. If this is not desirable, then the library can be updated with the desired functionality by the user. The I/O and IOB inputs to the macros
are the external net connections.
Bidirectional I/O Library Macros
Name
Inputs
Bidirectional
Outputs
D, T, C
IO, IOB
Q
IOBUFDS_FDE_LVDS
D, T, CE, C
IO, IOB
Q
IOBUFDS_FDC_LVDS
D, T, C, CLR
IO, IOB
Q
D, T, CE, C, CLR
IO, IOB
Q
D, T, C, PRE
IO, IOB
Q
D, T, CE, C, PRE
IO, IOB
Q
D, T, C, R
IO, IOB
Q
D, T, CE, C, R
IO, IOB
Q
D, T, C, S
IO, IOB
Q
IOBUFDS_FDSE_LVDS
D, T, CE, C, S
IO, IOB
Q
DS025-2 (v2.1) July 17, 2002
www.xilinx.com
1-800-255-7778
IOBUFDS_FD_LVDS
IOBUFDS_FDCE_LVDS
IOBUFDS_FDP_LVDS
IOBUFDS_FDPE_LVDS
IOBUFDS_FDR_LVDS
IOBUFDS_FDRE_LVDS
IOBUFDS_FDS_LVDS
Module 2 of 4
49
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 44:
Bidirectional I/O Library Macros (Continued)
Name
Inputs
Bidirectional
Outputs
D, T, G
IO, IOB
Q
IOBUFDS_LDE_LVDS
D, T, GE, G
IO, IOB
Q
IOBUFDS_LDC_LVDS
D, T, G, CLR
IO, IOB
Q
D, T, GE, G, CLR
IO, IOB
Q
D, T, G, PRE
IO, IOB
Q
D, T, GE, G, PRE
IO, IOB
Q
IOBUFDS_LD_LVDS
IOBUFDS_LDCE_LVDS
IOBUFDS_LDP_LVDS
IOBUFDS_LDPE_LVDS
Revision History
The following table shows the revision history for this document.
Date
Version
03/23/00
1.0
Initial Xilinx release.
08/01/00
1.1
Accumulated edits and fixes. Upgrade to Preliminary. Preview -8 numbers added.
Reformatted to adhere to corporate documentation style guidelines. Minor changes in
BG560 pin-out table.
09/19/00
1.2
•
1.3
•
•
11/20/00
Revision
•
•
•
•
In Table 3 (Module 4), FG676 Fine-Pitch BGA — XCV405E, the following pins are no
longer labeled as VREF: B7, G16, G26, W26, AF20, AF8, Y1, H1.
Min values added to Virtex-E Electrical Characteristics tables.
Updated speed grade -8 numbers in Virtex-E Electrical Characteristics tables
(Module 3).
Updated minimums in Table 11 (Module 2), and added notes to Table 12 (Module 2).
Added to note 2 of Absolute Maximum Ratings (Module 3).
Changed all minimum hold times to –0.4 for Global Clock Set-Up and Hold for LVTTL
Standard, with DLL (Module 3).
Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters (Module 3).
1.4
•
04/19/01
1.5
•
•
•
In Table 4, FG676 Fine-Pitch BGA — XCV405E, pin B19 is no longer labeled as VREF,
and pin G16 is now labeled as VREF.
Updated values in Virtex-E Switching Characteristics tables.
Converted data sheet to modularized format.
Modified Figure 30, which shows “DLL Generation of 4x Clock in Virtex-E Devices.”
07/23/01
1.6
•
Made minor edits to text under Configuration.
11/16/01
2.0
•
07/17/02
2.1
•
Added warning under Configuration section that attempting to load an incorrect
bitstream causes configuration to fail and can damage the device.
Data sheet designation upgraded from Preliminary to Production.
04/02/01
Virtex-E Extended Memory Data Sheet
The Virtex-E Extended Memory Data Sheet contains the following modules:
•
DS025-1, Virtex-E 1.8V Extended Memory FPGAs:
•
Introduction and Ordering Information (Module 1)
•
DS025-2, Virtex-E 1.8V Extended Memory FPGAs:
Functional Description (Module 2)
Module 2 of 4
50
DS025-3, Virtex-E 1.8V Extended Memory FPGAs:
DC and Switching Characteristics (Module 3)
•
DS025-4, Virtex-E 1.8V Extended Memory FPGAs:
Pinout Tables (Module 4)
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
0
Virtex™-E 1.8 V Extended Memory
Field Programmable Gate Arrays
R
DS025-3 (v2.2) July 17, 2002
0
0
Production Product Specification
Virtex-E Extended Memory Electrical Characteristics
Definition of Terms
Electrical and switching characteristics are specified on a
per-speed-grade basis and can be designated as Advance,
Preliminary, or Production. Each designation is defined as
follows:
Advance: These speed files are based on simulations only
and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative,
some under-reporting might still occur.
Preliminary: These speed files are based on complete ES
(engineering sample) silicon characterization. Devices and
speed grades with this designation are intended to give a
better indication of the expected performance of production
silicon. The probability of under-reporting delays is greatly
reduced as compared to Advance data.
Production: These speed files are released once enough
production silicon of a particular device family member has
been characterized to provide full correlation between
speed files and devices over numerous production lots.
There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes. Typ-
ically, the slowest speed grades transition to Production
before faster speed grades.
All specifications are representative of worst-case supply
voltage and junction temperature conditions. The parameters included are common to popular designs and typical
applications. Contact the factory for design considerations
requiring more detailed information.
Table 1 correlates the current status of each Virtex-E
Extended Memory device with a corresponding speed file
designation.
Table 1: Virtex-E Extended Memory Device
Speed Grade Designations
Speed Grade Designations
Device
Advance
Preliminary
Production
XCV405E
–8, –7, –6
XCV812E
–8, –7, –6
All specifications are subject to change without notice.
DC Characteristics
Absolute Maximum Ratings
Description(1)
Symbol
Units
Internal Supply voltage relative to GND (2)
–0.5 to 2.0
V
VCCO
Supply voltage relative to GND
–0.5 to 4.0
V
VREF
Input Reference Voltage
–0.5 to 4.0
V
VIN
Input voltage relative to GND
–0.5 to 4.0
V
VTS
Voltage applied to 3-state output
–0.5 to 4.0
V
VCC
Longest Supply Voltage Rise Time from 0 V – 1.71 V
50
ms
TSTG
Storage temperature (ambient)
–65 to +150
°C
+125
°C
VCCINT
TJ
Junction temperature (3)
Plastic packages
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time can affect device reliability.
2. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website.
© 2000-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS025-3 (v2.2) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 3 of 4
1
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Recommended Operating Conditions
Symbol
VCCINT
VCCO
Description
Min
Max
Units
Internal Supply voltage relative to GND, TJ = 0 °C to +85°C
Commercial
1.8 – 5%
1.8 + 5%
V
Internal Supply voltage relative to GND, TJ = –40°C to +100°C
Industrial
1.8 – 5%
1.8 + 5%
V
Supply voltage relative to GND, TJ = 0 °C to +85°C
Commercial
1.2
3.6
V
Supply voltage relative to GND, TJ = –40°C to +100°C
Industrial
1.2
3.6
V
250
ns
Input signal transition time
TIN
DC Characteristics Over Recommended Operating Conditions
Description(1)
Symbol
VDRINT
(below which configuration data might be lost)
ICCINTQ
IL
(below which configuration data might be lost)
Data Retention VCCO Voltage
VDRIO
ICCOQ
Data Retention VCCINT Voltage
Quiescent VCCINT supply current1
Quiescent VCCO supply current1
Input or output leakage current
Device
Min
All
1.5
V
All
1.2
V
Input capacitance (sample tested)
BGA, PQ, HQ, packages
IRPU
Pad pull-up (when selected) @ Vin = 0 V, VCCO = 3.3 V (sample tested)
IRPD
Pad pull-down (when selected) @ Vin = 3.6 V (sample tested)
Units
XCV405E
400
mA
XCV812E
500
mA
XCV405E
2
mA
XCV812E
2
mA
+10
µA
8
pF
Note 2
0.25
mA
Note 2
0.25
mA
All
CIN
Max
–10
All
All
Notes:
1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.
2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not guarantee valid logic levels when input pins are connected to other circuits.
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual
current consumed depends on the power-on ramp rate of the power supply. This is the time required to reach the nominal
power supply voltage of the device 1 from 0 V. The fastest suggested ramp rate is 0 V to nominal voltage in 2 ms and the
slowest allowed ramp rate is 0 V to nominal voltage in 50 ms. For more details on power supply requirements, see xapp158.
Product (Commercial Grade)
Description(2)
Current Requirement(3)
XCV50E - XCV600E
Minimum required current supply
500 mA
XCV812E - XCV2000E
Minimum required current supply
1A
XCV2600E - XCV3200E
Minimum required current supply
1.2 A
Virtex-E Family, Industrial Grade
Minimum required current supply
2A
Notes:
1. Ramp rate used for this specification is from 0 - 1.8 V DC. Peak current occurs on or near the internal power-on reset threshold and
lasts for less than 3 ms.
2. Devices are guaranteed to initialize properly with the minimum current available from the power supply as noted above.
3. Larger currents might result if ramp rates are forced to be faster.
Module 3 of 4
2
www.xilinx.com
1-800-255-7778
DS025-3 (v2.2) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended
operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that
all standards meet their specifications. The selected standards are tested at minimum VCCO with the respective VOL and
VOH voltage levels shown. Other standards are sample tested.
VIH
VIL
Input/Output
VOL
VOH
IOL
IOH
V, min
V, max
V, min
V, max
V, Max
V, Min
mA
mA
LVTTL(1)
– 0.5
0.8
2.0
3.6
0.4
2.4
24
– 24
LVCMOS2
– 0.5
0.7
1.7
2.7
0.4
1.9
12
– 12
LVCMOS18
– 0.5
20% VCCO
70% VCCO
1.95
0.4
VCCO – 0.4
8
–8
PCI, 3.3 V
– 0.5
30% VCCO
50% VCCO
VCCO + 0.5
10% VCCO
90% VCCO
Note 2
Note 2
GTL
– 0.5
VREF – 0.05
VREF + 0.05
3.6
0.4
n/a
40
n/a
GTL+
– 0.5
VREF – 0.1
VREF + 0.1
3.6
0.6
n/a
36
n/a
HSTL I(3)
– 0.5
VREF – 0.1
VREF + 0.1
3.6
0.4
VCCO – 0.4
8
–8
HSTL III
– 0.5
VREF – 0.1
VREF + 0.1
3.6
0.4
VCCO – 0.4
24
–8
HSTL IV
– 0.5
VREF – 0.1
VREF + 0.1
3.6
0.4
VCCO – 0.4
48
–8
SSTL3 I
– 0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.6
VREF + 0.6
8
–8
SSTL3 II
– 0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.8
VREF + 0.8
16
–16
SSTL2 I
– 0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.61
VREF + 0.61
7.6
–7.6
SSTL2 II
– 0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.80
VREF + 0.80
15.2
–15.2
CTT
– 0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.4
VREF + 0.4
8
–8
AGP
– 0.5
VREF – 0.2
VREF + 0.2
3.6
10% VCCO
90% VCCO
Note 2
Note 2
Standard
Notes:
1. VOL and VOH for lower drive currents are sample tested.
2. Tested according to the relevant specifications.
3. DC input and output levels for HSTL18 (HSTL I/O standard with VCCO of 1.8 V) are provided in an HSTL white paper on the Xilinx
website.
DS025-3 (v2.2) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 3 of 4
3
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
LVDS DC Specifications
DC Parameter
Symbol
Supply Voltage
Conditions
VCCO
Min
Typ
Max
Units
2.375
2.5
2.625
V
Output High Voltage for Q and Q
VOH
RT = 100 Ω across Q and Q signals
1.25
1.425
1.6
V
Output Low Voltage for Q and Q
VOL
RT = 100 Ω across Q and Q signals
0.9
1.075
1.25
V
VODIFF
RT = 100 Ω across Q and Q signals
250
350
450
mV
Output Common-Mode Voltage
VOCM
RT = 100 Ω across Q and Q signals
1.125
1.25
1.375
V
Differential Input Voltage (Q – Q),
VIDIFF
Common-mode input voltage = 1.25 V
100
350
NA
mV
VICM
Differential input voltage = ±350 mV
0.2
1.25
2.2
V
Differential Output Voltage (Q – Q),
Q = High (Q – Q), Q = High
Q = High (Q – Q), Q = High
Input Common-Mode Voltage
Notes:
1. Refer to the Design Consideration section for termination schematics.
LVPECL DC Specifications
These values are valid at the output of the source termination pack shown under LVPECL, with a 100 Ω differential load only.
The VOH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode
ranges. The following table summarizes the DC output specifications of LVPECL.
DC Parameter
Min
VCCO
Min
3.0
Max
Min
3.3
Max
3.6
Units
V
VOH
1.8
2.11
1.92
2.28
2.13
2.41
V
VOL
0.96
1.27
1.06
1.43
1.30
1.57
V
VIH
1.49
2.72
1.49
2.72
1.49
2.72
V
VIL
0.86
2.125
0.86
2.125
0.86
2.125
V
0.3
-
0.3
-
0.3
-
V
Differential Input Voltage
Module 3 of 4
4
Max
www.xilinx.com
1-800-255-7778
DS025-3 (v2.2) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Virtex-E Switching Characteristics
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed
below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. All
timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
Virtex-E devices unless otherwise noted.
IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values
shown in ‘‘IOB Input Switching Characteristics Standard Adjustments’’ on page 6.
Speed Grade(2)
Description(1)
Symbol
Device
Min
-8
-7
-6
Units
Pad to I output, no delay
TIOPI
All
0.43
0.8
0.8
0.8
ns, max
XCV405E
0.51
1.0
1.0
1.0
ns, max
Pad to I output, with delay
TIOPID
XCV812E
0.55
1.1
1.1
1.1
ns, max
All
0.75
1.4
1.5
1.6
ns, max
XCV405E
1.55
3.5
3.6
3.7
ns, max
XCV812E
1.55
3.5
3.6
3.7
ns, max
All
0.18
0.4
0.7
0.7
ns, max
Propagation Delays
Propagation Delays
Pad to output IQ via transparent latch,
no delay
TIOPLI
Pad to output IQ via transparent latch,
with delay
TIOPLID
Clock CLK to output IQ
TIOCKIQ
Setup and Hold Times with respect to Clock at IOB Input Register
Pad, no delay
TIOPICK /
TIOICKP
All
0.69 / 0
1.3 / 0
1.4 / 0
1.5 / 0
ns, min
TIOPICKD /
TIOICKPD
XCV405E
1.49 / 0
3.4 / 0
3.5 / 0
3.5 / 0
ns, min
XCV812E
1.49 / 0
3.4 / 0
3.5 / 0
3.5 / 0
ns, min
ICE input
TIOICECK /
TIOCKICE
All
0.28 /
0.0
0.55 /
0.01
0.7 /
0.01
0.7 /
0.01
ns, min
SR input (IFF, synchronous)
TIOSRCKI
All
0.38
0.8
0.9
1.0
ns, min
SR input to IQ (asynchronous)
TIOSRIQ
All
0.54
1.1
1.2
1.4
ns, max
GSR to output IQ
TGSRQ
All
3.88
7.6
8.5
9.7
ns, max
Pad, with delay
Set/Reset Delays
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
2. Input timing i for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
DS025-3 (v2.2) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 3 of 4
5
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
IOB Input Switching Characteristics Standard Adjustments
Speed Grade(1)
Description
Symbol
Standard
Min
-8
-7
-6
Units
TILVTTL
LVTTL
0.0
0.0
0.0
0.0
ns
TILVCMOS2
LVCMOS2
–0.02
0.0
0.0
0.0
ns
TILVCMOS18
LVCMOS18
–0.02
+0.20
+0.20
+0.20
ns
TILVDS
LVDS
0.00
+0.15
+0.15
+0.15
ns
TILVPECL
LVPECL
0.00
+0.15
+0.15
+0.15
ns
TIPCI33_3
PCI, 33 MHz, 3.3 V
–0.05
+0.08
+0.08
+0.08
ns
TIPCI66_3
PCI, 66 MHz, 3.3 V
–0.05
–0.11
–0.11
–0.11
ns
TIGTL
GTL
+0.10
+0.14
+0.14
+0.14
ns
TIGTLPLUS
GTL+
+0.06
+0.14
+0.14
+0.14
ns
TIHSTL
HSTL
+0.02
+0.04
+0.04
+0.04
ns
TISSTL2
SSTL2
–0.04
+0.04
+0.04
+0.04
ns
TISSTL3
SSTL3
–0.02
+0.04
+0.04
+0.04
ns
TICTT
CTT
+0.01
+0.10
+0.10
+0.10
ns
TIAGP
AGP
–0.03
+0.04
+0.04
+0.04
ns
Data Input Delay Adjustments
Standard-specific data input delay
adjustments
Notes:
1. Input timing i for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
I
T
TCE
D Q
CE
Weak
Keeper
SR
O
OCE
PAD
D Q
CE
OBUFT
SR
I
IQ
Q
D
CE
Programmable
Delay
IBUF
Vref
SR
SR
CLK
ICE
ds022_02_091300
Figure 1: Virtex-E Input/Output Block (IOB)
Module 3 of 4
6
www.xilinx.com
1-800-255-7778
DS025-3 (v2.2) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
IOB Output Switching Characteristics, Figure 1
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in ‘‘IOB Output Switching Characteristics Standard Adjustments’’ on page 8..
Speed Grade(2)
Description(1)
Symbol
Min3
-8
-7
-6
Units
O input to Pad
TIOOP
1.04
2.5
2.7
2.9
ns, max
O input to Pad via transparent latch
TIOOLP
1.24
2.9
3.1
3.4
ns, max
T input to Pad high-impedance (Note 2)
TIOTHZ
0.73
1.5
1.7
1.9
ns, max
T input to valid data on Pad
TIOTON
1.13
2.7
2.9
3.1
ns, max
T input to Pad high-impedance via transparent
latch (Note 2)
TIOTLPHZ
0.86
1.8
2.0
2.2
ns, max
T input to valid data on Pad via transparent latch
TIOTLPON
1.26
3.0
3.2
3.4
ns, max
TGTS
1.94
4.1
4.6
4.9
ns, max
Clock CLK to Pad
TIOCKP
0.97
2.4
2.8
2.9
ns, max
Clock CLK to Pad high-impedance (synchronous)
(Note 2)
TIOCKHZ
0.77
1.6
2.0
2.2
ns, max
Clock CLK to valid data on Pad (synchronous)
TIOCKON
1.17
2.8
3.2
3.4
ns, max
TIOOCK /
TIOCKO
0.43 / 0
0.9 / 0
1.0 / 0
1.1 / 0
ns, min
OCE input
TIOOCECK /
TIOCKOCE
0.28 / 0
0.55 / 0.01
0.7 / 0
0.7 / 0
ns, min
SR input (OFF)
TIOSRCKO /
TIOCKOSR
0.40 / 0
0.8 / 0
0.9 / 0
1.0 / 0
ns, min
TIOTCK /
TIOCKT
0.26 / 0
0.51 / 0
0.6 / 0
0.7 / 0
ns, min
3-State Setup Times, TCE input
TIOTCECK /
TIOCKTCE
0.30 / 0
0.6 / 0
0.7 / 0
0.8 / 0
ns, min
3-State Setup Times, SR input (TFF)
TIOSRCKT /
TIOCKTSR
0.38 / 0
0.8 / 0
0.9 / 0
1.0 / 0
ns, min
SR input to Pad (asynchronous)
TIOSRP
1.30
3.1
3.3
3.5
ns, max
SR input to Pad high-impedance (asynchronous)
(Note 2)
TIOSRHZ
1.08
2.2
2.4
2.7
ns, max
SR input to valid data on Pad (asynchronous)
TIOSRON
1.48
3.4
3.7
3.9
ns, max
GSR to Pad
TIOGSRQ
3.88
7.6
8.5
9.7
ns, max
Propagation Delays
3-State Delays
GTS to Pad high impedance (Note 2)
Sequential Delays
Setup and Hold Times before/after Clock CLK
O input
3-State Setup Times, T input
Set/Reset Delays
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
2. 3-state turn-off delays should not be adjusted.
DS025-3 (v2.2) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 3 of 4
7
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
IOB Output Switching Characteristics Standard Adjustments
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown.
Speed Grade
Description
Symbol
Standard
Min
-8
-7
-6
Units
TOLVTTL_S2
LVTTL, Slow, 2 mA
4.2
+14.7
+14.7
+14.7
ns
TOLVTTL_S4
4 mA
2.5
+7.5
+7.5
+7.5
ns
TOLVTTL_S6
6 mA
1.8
+4.8
+4.8
+4.8
ns
TOLVTTL_S8
8 mA
1.2
+3.0
+3.0
+3.0
ns
TOLVTTL_S12
12 mA
1.0
+1.9
+1.9
+1.9
ns
TOLVTTL_S16
16 mA
0.9
+1.7
+1.7
+1.7
ns
TOLVTTL_S24
24 mA
0.8
+1.3
+1.3
+1.3
ns
TOLVTTL_F2
LVTTL, Fast, 2 mA
1.9
+13.1
+13.1
+13.1
ns
TOLVTTL_F4
4 mA
0.7
+5.3
+5.3
+5.3
ns
TOLVTTL_F6
6 mA
0.20
+3.1
+3.1
+3.1
ns
TOLVTTL_F8
8 mA
0.10
+1.0
+1.0
+1.0
ns
TOLVTTL_F12
12 mA
0.0
0.0
0.0
0.0
ns
TOLVTTL_F16
16 mA
–0.10
–0.05
–0.05
–0.05
ns
TOLVTTL_F24
24 mA
–0.10
–0.20
–0.20
–0.20
ns
TOLVCMOS_2
LVCMOS2
0.10
+0.09
+0.09
+0.09
ns
TOLVCMOS_18
LVCMOS18
0.10
+0.7
+0.7
+0.7
ns
TOLVDS
LVDS
–0.39
–1.2
–1.2
–1.2
ns
TOLVPECL
LVPECL
–0.20
–0.41
–0.41
–0.41
ns
TOPCI33_3
PCI, 33 MHz, 3.3 V
0.50
+2.3
+2.3
+2.3
ns
TOPCI66_3
PCI, 66 MHz, 3.3 V
0.10
–0.41
–0.41
–0.41
ns
TOGTL
GTL
0.6
+0.49
+0.49
+0.49
ns
TOGTLP
GTL+
0.7
+0.8
+0.8
+0.8
ns
TOHSTL_I
HSTL I
0.10
–0.51
–0.51
–0.51
ns
TOHSTL_IIII
HSTL III
–0.10
–0.91
–0.91
–0.91
ns
TOHSTL_IV
HSTL IV
–0.20
–1.01
–1.01
–1.01
ns
TOSSTL2_I
SSTL2 I
–0.10
–0.51
–0.51
–0.51
ns
TOSSTL2_II
SSTL2 II
–0.20
–0.91
–0.91
–0.91
ns
TOSSTL3_I
SSTL3 I
–0.20
–0.51
–0.51
–0.51
ns
TOSSTL3_II
SSTL3 II
–0.30
–1.01
–1.01
–1.01
ns
TOCTT
CTT
0.0
–0.61
–0.61
–0.61
ns
TOAGP
AGP
–0.1
–0.91
–0.91
–0.91
ns
Output Delay Adjustments
Standard-specific adjustments for
output delays terminating at pads
(based on standard capacitive load,
Csl)
Module 3 of 4
8
www.xilinx.com
1-800-255-7778
DS025-3 (v2.2) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Calculation of Tioop as a Function of Capacitance
Tioop is the propagation delay from the O Input of the IOB to the
pad. The values for Tioop are based on the standard capacitive
load (Csl) for each I/O standard as listed in Table 2.
For other capacitive loads, use the formulas below to calculate the corresponding Tioop.
Table 2:
where:
Constants for Use in Calculation of Tioop
Csl
(pF)
fl
(ns/pF)
LVTTL Fast Slew Rate, 2mA drive
35
0.41
LVTTL Fast Slew Rate, 4mA drive
35
0.20
LVTTL Fast Slew Rate, 6mA drive
35
0.13
LVTTL Fast Slew Rate, 8mA drive
35
0.079
LVTTL Fast Slew Rate, 12mA drive
35
0.044
LVTTL Fast Slew Rate, 16mA drive
35
0.043
LVTTL Fast Slew Rate, 24mA drive
35
0.033
LVTTL Slow Slew Rate, 2mA drive
35
0.41
LVTTL Slow Slew Rate, 4mA drive
35
0.20
LVTTL Slow Slew Rate, 6mA drive
35
0.10
LVTTL Slow Slew Rate, 8mA drive
35
LVTTL Slow Slew Rate, 12mA drive
Standard
Tioop = Tioop + Topadjust + (Cload – Csl) * fl
Topadjust is reported above in the Output Delay
Adjustment section.
Cload is the capacitive load for the design.
Table 3:
Delay Measurement Methodology
VL1
VH1
Meas.
Point
VREF
(Typ)2
LVTTL
0
3
1.4
-
LVCMOS2
0
2.5
1.125
-
Standard
PCI33_3
Per PCI Spec
-
PCI66_3
Per PCI Spec
-
GTL
VREF –0.2
VREF +0.2
VREF
0.80
0.086
GTL+
VREF –0.2
VREF +0.2
VREF
1.0
35
0.058
HSTL Class I
VREF –0.5
VREF +0.5
VREF
0.75
LVTTL Slow Slew Rate, 16mA drive
35
0.050
HSTL Class III
VREF –0.5
VREF +0.5
VREF
0.90
LVTTL Slow Slew Rate, 24mA drive
35
0.048
HSTL Class IV
VREF –0.5
VREF +0.5
VREF
0.90
LVCMOS2
35
0.041
SSTL3 I & II
VREF –1.0
VREF +1.0
VREF
1.5
LVCMOS18
35
0.050
SSTL2 I & II
VREF –0.75
VREF +0.75
VREF
1.25
PCI 33 MHZ 3.3 V
10
0.050
CTT
10
0.033
VREF –0.2
VREF +0.2
VREF
1.5
PCI 66 MHz 3.3 V
GTL
0
0.014
AGP
VREF –
VREF +
GTL+
0
0.017
(0.2xVCCO)
(0.2xVCCO)
VREF
Per
AGP
Spec
HSTL Class I
20
0.022
LVDS
1.2 – 0.125
1.2 + 0.125
1.2
HSTL Class III
20
0.016
LVPECL
1.6 – 0.3
1.6 + 0.3
1.6
HSTL Class IV
20
0.014
SSTL2 Class I
30
0.028
SSTL2 Class II
30
0.016
SSTL3 Class I
30
0.029
SSTL3 Class II
30
0.016
CTT
20
0.035
AGP
10
0.037
Notes:
1. Input waveform switches between VLand VH.
2. Measurements are made at VREF (Typ), Maximum, and
Minimum. Worst-case values are reported.
I/O parameter measurements are made with the capacitance
values shown in Table 2. See the Application Examples for
appropriate terminations.
I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
Notes:
1. I/O parameter measurements are made with the capacitance
values shown above. See the Application Examples for
appropriate terminations.
2. I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
DS025-3 (v2.2) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 3 of 4
9
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Clock Distribution Switching Characteristics
Speed Grade
Description
Symbol
Min
-8
-7
-6
Units
Global Clock PAD to output.
TGPIO
0.38
0.7
0.7
0.7
ns, max
Global Clock Buffer I input to O output
TGIO
0.11
0.19
0.45
0.50
ns, max
GCLK IOB and Buffer
I/O Standard Global Clock Input Adjustments
Speed Grade
Description(1)
Symbol
Standard
Min
-8
-7
-6
Units
TGPLVTTL
LVTTL
0.0
0.0
0.0
0.0
ns, max
TGPLVCMOS2
LVCMOS2
–0.02
0.0
0.0
0.0
ns, max
TGPLVCMOS18
LVCMOS2
0.12
0.20
0.20
0.20
ns, max
TGLVDS
LVDS
0.23
0.38
0.38
0.38
ns, max
TGLVPECL
LVPECL
0.23
0.38
0.38
0.38
ns, max
TGPPCI33_3
PCI, 33 MHz, 3.3 V
–0.05
0.08
0.08
0.08
ns, max
TGPPCI66_3
PCI, 66 MHz, 3.3 V
–0.05
–0.11
–0.11
–0.11
ns, max
TGPGTL
GTL
0.20
0.37
0.37
0.37
ns, max
TGPGTLP
GTL+
0.20
0.37
0.37
0.37
ns, max
TGPHSTL
HSTL
0.18
0.27
0.27
0.27
ns, max
TGPSSTL2
SSTL2
0.21
0.27
0.27
0.27
ns, max
TGPSSTL3
SSTL3
0.18
0.27
0.27
0.27
ns, max
TGPCTT
CTT
0.22
0.33
0.33
0.33
ns, max
TGPAGP
AGP
0.21
0.27
0.27
0.27
ns, max
Data Input Delay Adjustments
Standard-specific global clock
input delay adjustments
Notes:
1. Input timing for GPLVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
Module 3 of 4
10
www.xilinx.com
1-800-255-7778
DS025-3 (v2.2) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used, see Figure 2. The values listed below are
worst-case. Precise values are provided by the timing analyzer.
Speed Grade
Description(1)
Symbol
Min
-8
-7
-6
Units
4-input function: F/G inputs to X/Y outputs
TILO
0.19
0.40
0.42
0.47
ns, max
5-input function: F/G inputs to F5 output
TIF5
0.36
0.76
0.8
0.9
ns, max
5-input function: F/G inputs to X output
TIF5X
0.35
0.74
0.8
0.9
ns, max
6-input function: F/G inputs to Y output via F6 MUX
TIF6Y
0.35
0.74
0.9
1.0
ns, max
6-input function: F5IN input to Y output
TF5INY
0.04
0.11
0.20
0.22
ns, max
Incremental delay routing through transparent latch
to XQ/YQ outputs
TIFNCTL
0.27
0.63
0.7
0.8
ns, max
TBYYB
0.19
0.38
0.46
0.51
ns, max
FF Clock CLK to XQ/YQ outputs
TCKO
0.34
0.78
0.9
1.0
ns, max
Latch Clock CLK to XQ/YQ outputs
TCKLO
0.40
0.77
0.9
1.0
ns, max
4-input function: F/G Inputs
TICK /
TCKI
0.39 / 0
0.9 / 0
1.0 / 0
1.1 / 0
ns, min
5-input function: F/G inputs
TIF5CK /
TCKIF5
0.55 / 0
1.3 / 0
1.4 / 0
1.5 / 0
ns, min
6-input function: F5IN input
TF5INCK /
TCKF5IN
0.27 / 0
0.6 / 0
0.8 / 0
0.8 / 0
ns, min
6-input function: F/G inputs via F6 MUX
TIF6CK /
TCKIF6
0.58 / 0
1.3 / 0
1.5 / 0
1.6 / 0
ns, min
BX/BY inputs
TDICK /
TCKDI
0.25 / 0
0.6 / 0
0.7 / 0
0.8 / 0
ns, min
CE input
TCECK /
TCKCE
0.28 / 0
0.55 / 0
0.7 / 0
0.7 / 0
ns, min
SR/BY inputs (synchronous)
TRCK /
TCKR
0.24 / 0
0.46 / 0
0.52 / 0
0.6 / 0
ns, min
Minimum Pulse Width, High
TCH
0.56
1.2
1.3
1.4
ns, min
Minimum Pulse Width, Low
TCL
0.56
1.2
1.3
1.4
ns, min
TRPW
0.94
1.9
2.1
2.4
ns, min
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
TRQ
0.39
0.8
0.9
1.0
ns, max
Toggle Frequency (MHz) (for export control)
FTOG
-
416
400
357
MHz
Combinatorial Delays
BY input to YB output
Sequential Delays
Setup and Hold Times before/after Clock CLK
Clock CLK
Set/Reset
Minimum Pulse Width, SR/BY inputs
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
DS025-3 (v2.2) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 3 of 4
11
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
COUT
YB
CY
G4
G3
G2
G1
I3
I2
I1
I0
Y
O
LUT
DI
WE
0
INIT
D Q
CE
1
REV
YQ
BY
XB
F5IN
F6
CY
CK
WE
A4
WSO
WSH
BX
X
DI
INIT
DQ
CE
BX
F4
F3
F2
F1
I3
I2
I1
I0
F5
F5
BY DG
WE
XQ
DI
REV
O
LUT
0
1
SR
CLK
CE
CIN
ds022_05_092000
Figure 2: Detailed View of Virtex-E Slice
Module 3 of 4
12
www.xilinx.com
1-800-255-7778
DS025-3 (v2.2) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
CLB Arithmetic Switching Characteristics
Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment
listed. Precise values are provided by the timing analyzer.
Speed Grade
Description(1)
Symbol
Min
-8
-7
-6
Units
F operand inputs to X via XOR
TOPX
0.32
0.68
0.8
0.8
ns, max
F operand input to XB output
TOPXB
0.35
0.65
0.8
0.9
ns, max
F operand input to Y via XOR
TOPY
0.59
1.07
1.4
1.5
ns, max
F operand input to YB output
TOPYB
0.48
0.89
1.1
1.3
ns, max
F operand input to COUT output
TOPCYF
0.37
0.71
0.9
1.0
ns, max
G operand inputs to Y via XOR
TOPGY
0.34
0.72
0.8
0.9
ns, max
G operand input to YB output
TOPGYB
0.47
0.78
1.2
1.3
ns, max
G operand input to COUT output
TOPCYG
0.36
0.60
0.9
1.0
ns, max
BX initialization input to COUT
TBXCY
0.19
0.36
0.51
0.57
ns, max
CIN input to X output via XOR
TCINX
0.27
0.50
0.6
0.7
ns, max
CIN input to XB
TCINXB
0.02
0.04
0.07
0.08
ns, max
CIN input to Y via XOR
TCINY
0.26
0.45
0.7
0.7
ns, max
CIN input to YB
TCINYB
0.16
0.28
0.38
0.43
ns, max
TBYP
0.05
0.10
0.14
0.15
ns, max
F1/2 operand inputs to XB output via AND
TFANDXB
0.10
0.30
0.35
0.39
ns, max
F1/2 operand inputs to YB output via AND
TFANDYB
0.28
0.56
0.7
0.8
ns, max
F1/2 operand inputs to COUT output via AND
TFANDCY
0.17
0.38
0.46
0.51
ns, max
G1/2 operand inputs to YB output via AND
TGANDYB
0.20
0.46
0.55
0.7
ns, max
G1/2 operand inputs to COUT output via AND
TGANDCY
0.09
0.28
0.30
0.34
ns, max
CIN input to FFX
TCCKX/TCKCX
0.47 / 0
1.0 / 0
1.2 / 0
1.3 / 0
ns, min
CIN input to FFY
TCCKY/TCKCY
0.49 / 0
0.92 / 0
1.2 / 0
1.3 / 0
ns, min
Combinatorial Delays
CIN input to COUT output
Multiplier Operation
Setup and Hold Times before/after Clock CLK
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
DS025-3 (v2.2) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 3 of 4
13
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
CLB Distributed RAM Switching Characteristics
Speed Grade
Description(1)
Symbol
Min
-8
-7
-6
Units
Clock CLK to X/Y outputs (WE active) 16 x 1 mode
TSHCKO16
0.67
1.38
1.5
1.7
ns, max
Clock CLK to X/Y outputs (WE active) 32 x 1 mode
TSHCKO32
0.84
1.66
1.9
2.1
ns, max
TREG
1.25
2.39
2.9
3.2
ns, max
F/G address inputs
TAS/TAH
0.19 / 0
0.38 / 0
0.42 / 0
0.47 / 0
ns, min
BX/BY data inputs (DIN)
TDS/TDH
0.44 / 0
0.87 / 0
0.97 / 0
1.09 / 0
ns, min
SR input (WE)
TWS/TWH
0.29 / 0
0.57 / 0
0.7 / 0
0.8 / 0
ns, min
Minimum Pulse Width, High
TWPH
0.96
1.9
2.1
2.4
ns, min
Minimum Pulse Width, Low
TWPL
0.96
1.9
2.1
2.4
ns, min
Minimum clock period to meet address write cycle time
TWC
1.92
3.8
4.2
4.8
ns, min
Minimum Pulse Width, High
TSRPH
1.0
1.9
2.1
2.4
ns, min
Minimum Pulse Width, Low
TSRPL
1.0
1.9
2.1
2.4
ns, min
Sequential Delays
Shift-Register Mode
Clock CLK to X/Y outputs
Setup and Hold Times before/after Clock CLK
Clock CLK
Shift-Register Mode
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
RAMB4_S#_S#
WEA
ENA
RSTA
CLKA
ADDRA[#:0]
DIA[#:0]
WEB
ENB
RSTB
CLKB
ADDRB[#:0]
DIB[#:0]
DOA[#:0]
DOB[#:0]
ds022_06_121699
Figure 3: Dual-Port Block SelectRAM
Module 3 of 4
14
www.xilinx.com
1-800-255-7778
DS025-3 (v2.2) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Block RAM Switching Characteristics
Speed Grade
Description(1)
Symbol
Min
-8
-7
-6
Units
TBCKO
0.63
2.46
3.1
3.5
ns, max
ADDR inputs
TBACK/TBCKA
0.42 / 0
0.9 / 0
1.0 / 0
1.1 / 0
ns, min
DIN inputs
TBDCK/TBCKD
0.42 / 0
0.9 / 0
1.0 / 0
1.1 / 0
ns, min
EN input
TBECK/TBCKE
0.97 / 0
2.0 / 0
2.2 / 0
2.5 / 0
ns, min
RST input
TBRCK/TBCKR
0.9 / 0
1.8 / 0
2.1 / 0
2.3 / 0
ns, min
WEN input
TBWCK/TBCKW
0.86 / 0
1.7 / 0
2.0 / 0
2.2 / 0
ns, min
Minimum Pulse Width, High
TBPWH
0.6
1.2
1.35
1.5
ns, min
Minimum Pulse Width, Low
TBPWL
0.6
1.2
1.35
1.5
ns, min
CLKA -> CLKB setup time for different ports
TBCCS
1.2
2.4
2.7
3.0
ns, min
Sequential Delays
Clock CLK to DOUT output
Setup and Hold Times before Clock CLK
Clock CLK
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
TBUF Switching Characteristics
Speed Grade
Description
Symbol
Min
-8
-7
-6
Units
TIO
0.0
0.0
0.0
0 .0
ns, max
TRI input to OUT output high-impedance
TOFF
0.05
0.092
0.10
0.11
ns, max
TRI input to valid data on OUT output
TON
0.05
0.092
0.10
0.11
ns, max
Combinatorial Delays
IN input to OUT output
JTAG Test Access Port Switching Characteristics
Description
Symbol
Value
Units
TMS and TDI Setup times before TCK
TTAPTK
4.0
ns, min
TMS and TDI Hold times after TCK
TTCKTAP
2.0
ns, min
Output delay from clock TCK to output TDO
TTCKTDO
11.0
ns, max
FTCK
33
MHz, max
Maximum TCK clock frequency
DS025-3 (v2.2) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 3 of 4
15
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Virtex-E Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL
Speed Grade(2)
Description(1)
LVTTL Global Clock Input to Output Delay using
Output Flip-flop, 12 mA, Fast Slew Rate, with
DLL.
Symbol
Device(3)
Min
-8
-7
-6
Units
TICKOFDLL
XCV405E
1.0
3.1
3.1
3.1
ns
XCV812E
1.0
3.1
3.1
3.1
ns
For data output with different standards, adjust
the delays with the values shown in ‘‘IOB Output
Switching Characteristics Standard Adjustments’’
on page 8.
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For other I/O standards and different loads, see
Table 2 and Table 3.
3. DLL output jitter is already included in the timing calculation.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLL
Speed Grade(2)
Description(1)
LVTTL Global Clock Input to Output Delay using
Output Flip-flop, 12 mA, Fast Slew Rate, without
DLL.
Symbol
Device
Min
-8
-7
-6
Units
TICKOF
XCV405E
1.6
4.5
4.7
4.9
ns
XCV812E
1.8
4.8
5.0
5.2
ns
For data output with different standards, adjust
the delays with the values shown in ‘‘IOB Output
Switching Characteristics Standard Adjustments’’
on page 8.
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For other I/O standards and different loads, see
Table 2 and Table 3.
Module 3 of 4
16
www.xilinx.com
1-800-255-7778
DS025-3 (v2.2) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Virtex-E Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Set-Up and Hold for LVTTL Standard, with DLL
Speed Grade(2)
Description(1)
Symbol
Device(3)
Min
-8
-7
-6
Units
XCV405E
1.5 / –0.4
1.5 / –0.4
1.6 / –0.4
1.7 / –0.4
ns
XCV812E
1.5 / –0.4
1.5 / –0.4
1.6 / –0.4
1.7 / –0.4
ns
Input Setup and Hold Time Relative to Global Clock Input Signal
for LVTTL Standard.
For data input with different standards, adjust the setup time
delay by the values shown in ‘‘IOB Input Switching
Characteristics Standard Adjustments’’ on page 6.
No Delay
TPSDLL/TPHDLL
Global Clock and IFF, with DLL
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. DLL output jitter is already included in the timing calculation.
Global Clock Set-Up and Hold for LVTTL Standard, without DLL
Speed Grade(2)
Description(1)
Symbol
Device(3)
Min
-8
-7
-6
Units
XCV405E
2.3 / 0
2.3 / 0
2.3 / 0
2.3 / 0
ns
XCV812E
2.5 / 0
2.5 / 0
2.5 / 0
2.5 / 0
ns
Input Setup and Hold Time Relative to Global Clock Input Signal
for LVTTL Standard.
For data input with different standards, adjust the setup time delay
by the values shown in ‘‘IOB Input Switching Characteristics
Standard Adjustments’’ on page 6.
Full Delay
Global Clock and IFF, without DLL
TPSFD/TPHFD
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
DS025-3 (v2.2) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 3 of 4
17
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
DLL Timing Parameters
All devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those
parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case values across the
recommended operating conditions.
Speed Grade
-8
Description
Symbol
FCLKIN
-7
-6
Min
Max
Min
Max
Min
Max
Units
Input Clock Frequency (CLKDLLHF)
FCLKINHF
60
320
60
320
60
260
MHz
Input Clock Frequency (CLKDLL)
FCLKINLF
25
160
25
160
25
135
MHz
Input Clock Low/High Pulse Width
TDLLPW
≥25 MHz
5.0
5.0
5.0
ns
≥50 MHz
3.0
3.0
3.0
ns
≥100 MHz
2.4
2.4
2.4
ns
≥150 MHz
2.0
2.0
2.0
ns
≥200 MHz
1.8
1.8
1.8
ns
≥250 MHz
1.5
1.5
1.5
ns
≥300 MHz
1.3
1.3
NA
ns
Period Tolerance: the allowed input clock period change in nanoseconds.
TCLKIN +_ TIPTOL
TCLKIN
Output Jitter: the difference between an ideal
reference clock edge and the actual design.
Phase Offset and Maximum Phase Difference
Ideal Period
Actual Period
+ Jitter
+/- Jitter
+ Maximum
Phase Difference
+ Phase Offset
ds022_24_091200
Figure 4: DLL Timing Waveforms
Module 3 of 4
18
www.xilinx.com
1-800-255-7778
DS025-3 (v2.2) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock
mirror configuration and matched drivers.
CLKDLLHF
Description
Symbol
FCLKIN
CLKDLL
Min
Max
Min
Max
Units
Input Clock Period Tolerance
TIPTOL
-
1.0
-
1.0
ns
Input Clock Jitter Tolerance (Cycle to Cycle)
TIJITCC
-
± 150
-
± 300
ps
Time Required for DLL to Acquire Lock(6)
TLOCK
> 60 MHz
-
20
-
20
µs
50 - 60 MHz
-
-
-
25
µs
40 - 50 MHz
-
-
-
50
µs
30 - 40 MHz
-
-
-
90
µs
25 - 30 MHz
-
-
-
120
µs
TOJITCC
± 60
± 60
ps
Phase Offset between CLKIN and CLKO(2)
TPHIO
± 100
± 100
ps
Phase Offset between Clock Outputs on the DLL(3)
TPHOO
± 140
± 140
ps
Maximum Phase Difference between CLKIN and CLKO(4)
TPHIOM
± 160
± 160
ps
Maximum Phase Difference between Clock Outputs on the DLL(5)
TPHOOM
± 200
± 200
ps
Output Jitter (cycle-to-cycle) for any DLL Clock Output(1)
Notes:
1. Output Jitter is cycle-to-cycle jitter measured on the DLL output clock and is based on a maximum tap delay resolution, excluding
input clock jitter.
2. Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding Output Jitter and input clock jitter.
3. Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding Output Jitter and input clock jitter.
4. Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,
or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
5. Maximum Phase DIfference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges sue to DLL alone (excluding input clock jitter).
6. Add 30% to the value for Industrial grade parts.
DS025-3 (v2.2) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 3 of 4
19
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Revision History
The following table shows the revision history for this document.
Date
Version
03/23/00
1.0
Initial Xilinx release.
08/01/00
1.1
Accumulated edits and fixes. Upgrade to Preliminary. Preview -8 numbers added.
Reformatted to adhere to corporate documentation style guidelines. Minor changes in
BG560 pin-out table.
09/19/00
1.2
•
1.3
•
•
11/20/00
Revision
•
•
•
•
04/19/01
1.5
•
In Table 4, FG676 Fine-Pitch BGA — XCV405E, pin B19 is no longer labeled as VREF,
and pin G16 is now labeled as VREF.
Updated values in Virtex-E Switching Characteristics tables.
Converted data sheet to modularized format. See the Virtex-E Extended Memory Data
Sheet section.
Updated values in Virtex-E Switching Characteristics tables.
07/23/01
1.6
•
Under Absolute Maximum Ratings, changed (TSOL) to 220 °C .
•
04/02/01
1.4
•
In Table 3 (Module 4), FG676 Fine-Pitch BGA — XCV405E, the following pins are no
longer labeled as VREF: B7, G16, G26, W26, AF20, AF8, Y1, H1.
Min values added to Virtex-E Electrical Characteristics tables.
Updated speed grade -8 numbers in Virtex-E Electrical Characteristics tables
(Module 3).
Updated minimums in Table 11 (Module 2), and added notes to Table 12 (Module 2).
Added to note 2 of Absolute Maximum Ratings (Module 3).
Changed all minimum hold times to –0.4 for Global Clock Set-Up and Hold for LVTTL
Standard, with DLL (Module 3).
Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters (Module 3).
•
•
07/26/01
1.7
•
Changes made to SSTL symbol names in IOB Input Switching Characteristics Standard
Adjustments table.
Removed TSOL parameter and added footnote to Absolute Maximum Ratings table.
09/18/01
1.8
•
Reworded power supplies footnote to Absolute Maximum Ratings table.
10/25/01
1.9
•
Updated the speed grade designations used in data sheets, and added Table 1, which
shows the current speed grade designation for each device.
Updated Power-On Power Supply Requirements table.
Updated the XCV405E device speed grade designation to Preliminary in Table 1.
Updated Power-On Power Supply Requirements table.
Updated footnotes to the DC Input and Output Levels and DLL Clock Tolerance, Jitter,
and Phase Information tables.
Data sheet designation upgraded from Preliminary to Production.
Removed mention of MIL-M-38510/605 specification.
Added link to xapp158 from the Power-On Power Supply Requirements section.
11/09/01
2.0
02/01/02
2.1
07/17/02
2.2
•
•
•
•
•
•
•
Virtex-E Extended Memory Data Sheet
The Virtex-E Extended Memory Data Sheet contains the following modules:
•
DS025-1, Virtex-E 1.8V Extended Memory FPGAs:
•
Introduction and Ordering Information (Module 1)
•
DS025-2, Virtex-E 1.8V Extended Memory FPGAs:
Functional Description (Module 2)
Module 3 of 4
20
DS025-3, Virtex-E 1.8V Extended Memory FPGAs:
DC and Switching Characteristics (Module 3)
•
DS025-4, Virtex-E 1.8V Extended Memory FPGAs:
Pinout Tables (Module 4)
www.xilinx.com
1-800-255-7778
DS025-3 (v2.2) July 17, 2002
0
Virtex™-E 1.8 V Extended Memory
Field Programmable Gate Arrays
R
DS025-4 (v1.6) July 17, 2002
0
0
Production Product Specification
Virtex-E Pin Definitions
Pin Name
Dedicated Pin
Direction
Description
GCK0, GCK1,
GCK2, GCK3
Yes
Input
Clock input pins that connect to Global Clock Buffers. These pins become
user inputs when not needed for clocks.
M0, M1, M2
Yes
Input
Mode pins are used to specify the configuration mode.
CCLK
Yes
Input or
Output
PROGRAM
Yes
Input
DONE
Yes
Bidirectional
Indicates that configuration loading is complete, and that the start-up
sequence is in progress. The output can be open drain.
INIT
No
Bidirectional
(Open-drain)
When Low, indicates that the configuration memory is being cleared. The pin
becomes a user I/O after configuration.
BUSY/DOUT
No
Output
In SelectMAP mode, BUSY controls the rate at which configuration data is
loaded. The pin becomes a user I/O after configuration unless the
SelectMAP port is retained.
The configuration Clock I/O pin: it is an input for SelectMAP and slave-serial
modes, and output in master-serial mode. After configuration, it is input only,
logic level = Don’t Care.
Initiates a configuration sequence when asserted Low.
In bit-serial modes, DOUT provides preamble and configuration data to
downstream devices in a daisy-chain. The pin becomes a user I/O after
configuration.
D0/DIN,
No
D1, D2,
Input or
Output
In SelectMAP mode, D0-7 are configuration data pins. These pins become
user I/Os after configuration unless the SelectMAP port is retained.
In bit-serial modes, DIN is the single data input. This pin becomes a user I/O
after configuration.
D3, D4,
D5, D6,
D7
WRITE
No
Input
In SelectMAP mode, the active-low Write Enable signal. The pin becomes a
user I/O after configuration unless the SelectMAP port is retained.
CS
No
Input
In SelectMAP mode, the active-low Chip Select signal. The pin becomes a
user I/O after configuration unless the SelectMAP port is retained.
TDI, TDO,
Yes
Mixed
Boundary-scan Test-Access-Port pins, as defined in IEEE1149.1.
DXN, DXP
Yes
N/A
Temperature-sensing diode pins. (Anode: DXP, cathode: DXN)
VCCINT
Yes
Input
Power-supply pins for the internal core logic.
VCCO
Yes
Input
Power-supply pins for the output drivers (subject to banking rules)
VREF
No
Input
Input threshold voltage pins. Become user I/Os when an external threshold
voltage is not needed (subject to banking rules).
GND
Yes
Input
Ground
TMS, TCK
© 2000-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS025-4 (v1.6) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 4 of 4
1
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
BG560 Ball Grid Array Packages
Table 1:
XCV405E and the XCV812E Virtex-E Extended Memory
devices are available in the BG560 BGA package. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
not used as VREF, it can be used as general I/O. Immediately following Table 1, see Table 2 for BG560 package Differential Pair information.
Table 1:
BG560 BGA — XCV405E and XCV812E
Bank
Pin Description
Pin#
0
GCK3
A17
0
IO
A27
0
IO
B25
0
IO
C28
0
IO
C30
0
IO
D30
0
IO
E18
0
IO_L0N
E28
0
IO_L0P
D29
0
IO_L1N_YY
D28
0
IO_L1P_YY
A31
0
IO_VREF_L2N_YY
E27
0
IO_L2P_YY
C29
0
IO_L3N_Y
B30
0
IO_L3P_Y
D27
0
IO_L4N_YY
E26
0
IO_L4P_YY
B29
0
IO_VREF_L5N_YY
D26
0
IO_L5P_YY
C27
0
IO_L6N
E25
0
IO_L6P
A28
0
IO_L7N_YY
D25
0
IO_L7P_YY
C26
0
IO_VREF_L8N_YY
E24 1
0
IO_L8P_YY
B26
0
IO_L9N_Y
C25
0
IO_L9P_Y
D24
0
IO_VREF_L10N_YY
E23
0
IO_L10P_YY
A25
0
IO_L11N_YY
D23
Module 4 of 4
2
BG560 BGA — XCV405E and XCV812E
Bank
Pin Description
Pin#
0
IO_L11P_YY
B24
0
IO_L12N
E22
0
IO_L12P
C23
0
IO_L13N_YY
A23
0
IO_L13P_YY
D22
0
IO_VREF_L14N_YY
E211
0
IO_L14P_YY
B22
0
IO_L15N_Y
D21
0
IO_L15P_Y
C21
0
IO_L16N_YY
B21
0
IO_L16P_YY
E20
0
IO_VREF_L17N_YY
D20
0
IO_L17P_YY
C20
0
IO_L18N
B20
0
IO_L18P
E19
0
IO_L19N_YY
D19
0
IO_L19P_YY
C19
0
IO_VREF_L20N_YY
A19
0
IO_L20P_YY
D18
0
IO_LVDS_DLL_L21N
C18
1
GCK2
D17
1
IO
A3
1
IO
D9
1
IO
E8
1
IO
E11
1
IO_LVDS_DLL_L21P
E17
1
IO_L22N_Y
C17
1
IO_L22P_Y
B17
1
IO_L23N_YY
B16
1
IO_VREF_L23P_YY
D16
1
IO_L24N_YY
E16
1
IO_L24P_YY
C16
1
IO_L25N
A15
1
IO_L25P
C15
1
IO_L26N_YY
D15
1
IO_VREF_L26P_YY
E15
www.xilinx.com
1-800-255-7778
DS025-4 (v1.6) July 17, 2002
R
Table 1:
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
BG560 BGA — XCV405E and XCV812E
Table 1:
BG560 BGA — XCV405E and XCV812E
Bank
Pin Description
Pin#
Bank
Pin Description
Pin#
1
IO_L27N_YY
C14
2
IO
D3
1
IO_L27P_YY
D14
2
IO
F3
1
IO_L28N_Y
A13
2
IO
G1
1
IO_L28P_Y
E14
2
IO
J2
1
IO_L29N_YY
C13
2
IO_DOUT_BUSY_L45P_YY
D4
1
IO_VREF_L29P_YY
D131
2
IO_DIN_D0_L45N_YY
E4
1
IO_L30N_YY
C12
2
IO_L46P_Y
F5
1
IO_L30P_YY
E13
2
IO_L46N_Y
B3
1
IO_L31N
A11
2
IO_L47P
F4
1
IO_L31P
D12
2
IO_L47N
C1
1
IO_L32N_YY
B11
2
IO_VREF_L48P_Y
G5
1
IO_L32P_YY
C11
2
IO_L48N_Y
E3
1
IO_L33N_YY
B10
2
IO_L49P_Y
D2
1
IO_VREF_L33P_YY
D11
2
IO_L49N_Y
G4
1
IO_L34N
C10
2
IO_L50P_Y
H5
1
IO_L34P
A9
2
IO_L50N_Y
E2
1
IO_L35N_YY
C9
2
IO_VREF_L51P_YY
H4
1
IO_VREF_L35P_YY
D101
2
IO_L51N_YY
G3
1
IO_L36N_YY
A8
2
IO_L52P_Y
J5
1
IO_L36P_YY
B8
2
IO_L52N_Y
F1
1
IO_L37N_Y
E10
2
IO_L53P
J4
1
IO_L37P_Y
C8
2
IO_L53N
H3
1
IO_L38N_YY
B7
2
IO_VREF_L54P_YY
K51
1
IO_VREF_L38P_YY
A6
2
IO_L54N_YY
H2
1
IO_L39N_YY
C7
2
IO_L55P_Y
J3
1
IO_L39P_YY
D8
2
IO_L55N_Y
K4
1
IO_L40N
A5
2
IO_VREF_L56P_YY
L5
1
IO_L40P
B5
2
IO_D1_L56N_YY
K3
1
IO_L41N_YY
C6
2
IO_D2_L57P_YY
L4
1
IO_VREF_L41P_YY
D7
2
IO_L57N_YY
K2
1
IO_L42N_YY
A4
2
IO_L58P_Y
M5
1
IO_L42P_YY
B4
2
IO_L58N_Y
L3
1
IO_L43N_Y
C5
2
IO_L59P
L1
1
IO_L43P_Y
E7
2
IO_L59N
M4
1
IO_WRITE_L44N_YY
D6
2
IO_VREF_L60P_Y
N51
1
IO_CS_L44P_YY
A2
2
IO_L60N_Y
M2
2
IO_L61P_Y
N4
DS025-4 (v1.6) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 4 of 4
3
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 1:
BG560 BGA — XCV405E and XCV812E
Table 1:
BG560 BGA — XCV405E and XCV812E
Bank
Pin Description
Pin#
Bank
Pin Description
Pin#
2
IO_L61N_Y
N3
3
IO_L77P
AB3
2
IO_L62P_Y
N2
3
IO_L77N
AA5
2
IO_L62N_Y
P5
3
IO_L78P
AC1
2
IO_VREF_L63P_YY
P4
3
IO_L78N
AB4
2
IO_D3_L63N_YY
P3
3
IO_L79P_YY
AC3
2
IO_L64P_Y
P2
3
IO_D5_L79N_YY
AB5
2
IO_L64N_Y
R5
3
IO_D6_L80P_YY
AC4
2
IO_L65P_Y
R4
3
IO_VREF_L80N_YY
AD3
2
IO_L65N_Y
R3
3
IO_L81P_Y
AE1
2
IO_VREF_L66P_Y
R1
3
IO_L81N_Y
AC5
2
IO_L66N_Y
T4
3
IO_L82P_YY
AD4
2
IO_L67P_Y
T5
3
IO_VREF_L82N_YY
AF11
2
IO_L67N_Y
T3
3
IO_L83P_Y
AF2
2
IO_L68P_YY
T2
3
IO_L83N_Y
AD5
2
IO_L68N_YY
U3
3
IO_L84P_Y
AG2
3
IO_L84N_Y
AE4
3
IO
U4
3
IO_L85P_YY
AH1
3
IO
AE3
3
IO_VREF_L85N_YY
AE5
3
IO
AF3
3
IO_L86P_Y
AF4
3
IO
AH3
3
IO_L86N_Y
AJ1
3
IO
AK3
3
IO_L87P_Y
AJ2
3
IO_L69P_Y
U1
3
IO_L87N_Y
AF5
3
IO_L69N_Y
U2
3
IO_L88P_Y
AG4
3
IO_L70P_Y
V2
3
IO_VREF_L88N_Y
AK2
3
IO_VREF_L70N_Y
V4
3
IO_L89P_Y
AJ3
3
IO_L71P_Y
V5
3
IO_L89N_Y
AG5
3
IO_L71N_Y
V3
3
IO_L90P_Y
AL1
3
IO_L72P
W1
3
IO_L90N_Y
AH4
3
IO_L72N
W3
3
IO_D7_L91P_YY
AJ4
3
IO_D4_L73P_YY
W4
3
IO_INIT_L91N_YY
AH5
3
IO_VREF_L73N_YY
W5
3
IO_L74P_Y
Y3
4
GCK0
AL17
3
IO_L74N_Y
Y4
4
IO
AJ8
3
IO_L75P
AA1
4
IO
AJ11
3
IO_L75N
Y5
4
IO
AK6
3
IO_L76P_Y
AA3
4
IO
AK9
3
IO_VREF_L76N_Y
AA41
4
IO_L92P_YY
AL4
Module 4 of 4
4
www.xilinx.com
1-800-255-7778
DS025-4 (v1.6) July 17, 2002
R
Table 1:
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
BG560 BGA — XCV405E and XCV812E
Table 1:
BG560 BGA — XCV405E and XCV812E
Bank
Pin Description
Pin#
Bank
Pin Description
Pin#
4
IO_L92N_YY
AJ6
4
IO_L111P
AJ15
4
IO_L93P
AK5
4
IO_L111N
AK15
4
IO_L93N
AN3
4
IO_L112P_YY
AL15
4
IO_L94P_YY
AL5
4
IO_L112N_YY
AM16
4
IO_L94N_YY
AJ7
4
IO_VREF_L113P_YY
AL16
4
IO_VREF_L95P_YY
AM4
4
IO_L113N_YY
AJ16
4
IO_L95N_YY
AM5
4
IO_L114P_Y
AK16
4
IO_L96P_Y
AK7
4
IO_L114N_Y
AN17
4
IO_L96N_Y
AL6
4
IO_LVDS_DLL_L115P
AM17
4
IO_L97P_YY
AM6
4
IO_L97N_YY
AN6
5
GCK1
AJ17
4
IO_VREF_L98P_YY
AL7
5
IO
AL18
4
IO_L98N_YY
AJ9
5
IO
AL25
4
IO_L99P
AN7
5
IO
AL28
4
IO_L99N
AL8
5
IO
AL30
4
IO_L100P_YY
AM8
5
IO
AN28
4
IO_L100N_YY
AJ10
5
IO_LVDS_DLL_L115N
AM18
4
IO_VREF_L101P_YY
AL91
5
IO_L116P_YY
AK18
4
IO_L101N_YY
AM9
5
IO_VREF_L116N_YY
AJ18
4
IO_L102P_Y
AK10
5
IO_L117P_YY
AN19
4
IO_L102N_Y
AN9
5
IO_L117N_YY
AL19
4
IO_VREF_L103P_YY
AL10
5
IO_L118P
AK19
4
IO_L103N_YY
AM10
5
IO_L118N
AM20
4
IO_L104P_YY
AL11
5
IO_L119P_YY
AJ19
4
IO_L104N_YY
AJ12
5
IO_VREF_L119N_YY
AL20
4
IO_L105P
AN11
5
IO_L120P_YY
AN21
4
IO_L105N
AK12
5
IO_L120N_YY
AL21
4
IO_L106P_YY
AL12
5
IO_L121P_Y
AJ20
4
IO_L106N_YY
AM12
5
IO_L121N_Y
AM22
4
IO_VREF_L107P_YY
AK131
5
IO_L122P_YY
AK21
4
IO_L107N_YY
AL13
5
IO_VREF_L122N_YY
AN231
4
IO_L108P_Y
AM13
5
IO_L123P_YY
AJ21
4
IO_L108N_Y
AN13
5
IO_L123N_YY
AM23
4
IO_L109P_YY
AJ14
5
IO_L124P
AK22
4
IO_L109N_YY
AK14
5
IO_L124N
AM24
4
IO_VREF_L110P_YY
AM14
5
IO_L125P_YY
AL23
4
IO_L110N_YY
AN15
5
IO_L125N_YY
AJ22
DS025-4 (v1.6) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 4 of 4
5
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 1:
BG560 BGA — XCV405E and XCV812E
Table 1:
BG560 BGA — XCV405E and XCV812E
Bank
Pin Description
Pin#
Bank
Pin Description
Pin#
5
IO_L126P_YY
AK23
6
IO_L141P_Y
AF29
5
IO_VREF_L126N_YY
AL24
6
IO_L142N_Y
AH32
5
IO_L127P_Y
AN26
6
IO_L142P_Y
AF30
5
IO_L127N_Y
AJ23
6
IO_VREF_L143N_YY
AE29
5
IO_L128P_YY
AK24
6
IO_L143P_YY
AH33
5
IO_VREF_L128N_YY
AM261
6
IO_L144N_Y
AG33
5
IO_L129P_YY
AM27
6
IO_L144P_Y
AE30
5
IO_L129N_YY
AJ24
6
IO_L145N_Y
AD29
5
IO_L130P_Y
AL26
6
IO_L145P_Y
AF32
5
IO_L130N_Y
AK25
6
IO_VREF_L146N_Y
AE311
5
IO_L131P_YY
AN29
6
IO_L146P_Y
AD30
5
IO_VREF_L131N_YY
AJ25
6
IO_L147N_Y
AE32
5
IO_L132P_YY
AK26
6
IO_L147P_Y
AC29
5
IO_L132N_YY
AM29
6
IO_VREF_L148N_YY
AD31
5
IO_L133P_Y
AM30
6
IO_L148P_YY
AC30
5
IO_L133N_Y
AJ26
6
IO_L149N_YY
AB29
5
IO_L134P_YY
AK27
6
IO_L149P_YY
AC31
5
IO_VREF_L134N_YY
AL29
6
IO_L150N_Y
AC33
5
IO_L135P_YY
AN31
6
IO_L150P_Y
AB30
5
IO_L135N_YY
AJ27
6
IO_L151N_Y
AB31
5
IO_L136P_Y
AM31
6
IO_L151P_Y
AA29
5
IO_L136N_Y
AK28
6
IO_VREF_L152N_Y
AA301
6
IO_L152P_Y
AA31
6
IO
U29
6
IO_L153N_Y
AA32
6
IO
AE33
6
IO_L153P_Y
Y29
6
IO
AF31
6
IO_L154N_Y
AA33
6
IO
AJ32
6
IO_L154P_Y
Y30
6
IO
AL33
6
IO_VREF_L155N_YY
Y32
6
IO_L137N_YY
AH29
6
IO_L155P_YY
W29
6
IO_L137P_YY
AJ30
6
IO_L156N_Y
W30
6
IO_L138N_Y
AK31
6
IO_L156P_Y
W31
6
IO_L138P_Y
AH30
6
IO_L157N_Y
W33
6
IO_L139N_Y
AG29
6
IO_L157P_Y
V30
6
IO_L139P_Y
AJ31
6
IO_VREF_L158N_Y
V29
6
IO_VREF_L140N_Y
AK32
6
IO_L158P_Y
V31
6
IO_L140P_Y
AG30
6
IO_L159N_Y
V32
6
IO_L141N_Y
AH31
6
IO_L159P_Y
U33
Module 4 of 4
6
www.xilinx.com
1-800-255-7778
DS025-4 (v1.6) July 17, 2002
R
Table 1:
Bank
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
BG560 BGA — XCV405E and XCV812E
Pin Description
Pin#
Table 1:
BG560 BGA — XCV405E and XCV812E
Bank
Pin Description
Pin#
7
IO_L175P_Y
H31
7
IO
E30
7
IO_L176N_Y
J30
7
IO
F29
7
IO_L176P_Y
G32
7
IO
F33
7
IO_L177N_YY
J29
7
IO
G30
7
IO_VREF_L177P_YY
G31
7
IO
K30
7
IO_L178N_Y
E33
7
IO_L160N_YY
U31
7
IO_L178P_Y
E32
7
IO_L160P_YY
U32
7
IO_L179N_Y
H29
7
IO_L161N_Y
T32
7
IO_L179P_Y
F31
7
IO_L161P_Y
T30
7
IO_L180N_Y
D32
7
IO_L162N_Y
T29
7
IO_VREF_L180P_Y
E31
7
IO_VREF_L162P_Y
T31
7
IO_L181N_Y
G29
7
IO_L163N_Y
R33
7
IO_L181P_Y
C33
7
IO_L163P_Y
R31
7
IO_L182N_Y
F30
7
IO_L164N_Y
R30
7
IO_L182P_Y
D31
7
IO_L164P_Y
R29
7
IO_L165N_YY
P32
2
CCLK
C4
7
IO_VREF_L165P_YY
P31
3
DONE
AJ5
7
IO_L166N_Y
P30
NA
DXN
AK29
7
IO_L166P_Y
P29
NA
DXP
AJ28
7
IO_L167N_Y
M32
NA
M0
AJ29
7
IO_L167P_Y
N31
NA
M1
AK30
7
IO_L168N_Y
N30
NA
M2
AN32
7
IO_VREF_L168P_Y
L331
NA
PROGRAM
AM1
7
IO_L169N_Y
M31
NA
TCK
E29
7
IO_L169P_Y
L32
NA
TDI
D5
7
IO_L170N_Y
M30
2
TDO
E6
7
IO_L170P_Y
L31
NA
TMS
B33
7
IO_L171N_YY
M29
7
IO_L171P_YY
J33
NA
NC
C31
7
IO_L172N_YY
L30
NA
NC
AC2
7
IO_VREF_L172P_YY
K31
NA
NC
AK4
7
IO_L173N_Y
L29
NA
NC
AL3
7
IO_L173P_Y
H33
7
IO_L174N_Y
J31
NA
VCCINT
A21
7
IO_VREF_L174P_Y
H32 1
NA
VCCINT
B12
7
IO_L175N_Y
K29
NA
VCCINT
B14
DS025-4 (v1.6) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 4 of 4
7
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 1:
BG560 BGA — XCV405E and XCV812E
Table 1:
BG560 BGA — XCV405E and XCV812E
Bank
Pin Description
Pin#
Bank
Pin Description
Pin#
NA
VCCINT
B18
0
VCCO
B19
NA
VCCINT
B28
0
VCCO
B32
NA
VCCINT
C22
1
VCCO
A10
NA
VCCINT
C24
1
VCCO
A16
NA
VCCINT
E9
1
VCCO
B13
NA
VCCINT
E12
1
VCCO
C3
NA
VCCINT
F2
1
VCCO
E5
NA
VCCINT
H30
2
VCCO
B2
NA
VCCINT
J1
2
VCCO
D1
NA
VCCINT
K32
2
VCCO
H1
NA
VCCINT
M3
2
VCCO
M1
NA
VCCINT
N1
2
VCCO
R2
NA
VCCINT
N29
3
VCCO
V1
NA
VCCINT
N33
3
VCCO
AA2
NA
VCCINT
U5
3
VCCO
AD1
NA
VCCINT
U30
3
VCCO
AK1
NA
VCCINT
Y2
3
VCCO
AL2
NA
VCCINT
Y31
4
VCCO
AN4
NA
VCCINT
AB2
4
VCCO
AN8
NA
VCCINT
AB32
4
VCCO
AN12
NA
VCCINT
AD2
4
VCCO
AM2
NA
VCCINT
AD32
4
VCCO
AM15
NA
VCCINT
AG3
5
VCCO
AL31
NA
VCCINT
AG31
5
VCCO
AM21
NA
VCCINT
AJ13
5
VCCO
AN18
NA
VCCINT
AK8
5
VCCO
AN24
NA
VCCINT
AK11
5
VCCO
AN30
NA
VCCINT
AK17
6
VCCO
W32
NA
VCCINT
AK20
6
VCCO
AB33
NA
VCCINT
AL14
6
VCCO
AF33
NA
VCCINT
AL22
6
VCCO
AK33
NA
VCCINT
AL27
6
VCCO
AM32
NA
VCCINT
AN25
7
VCCO
C32
7
VCCO
D33
0
VCCO
A22
7
VCCO
K33
0
VCCO
A26
7
VCCO
N32
0
VCCO
A30
7
VCCO
T33
Module 4 of 4
8
www.xilinx.com
1-800-255-7778
DS025-4 (v1.6) July 17, 2002
R
Table 1:
Bank
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
BG560 BGA — XCV405E and XCV812E
Pin Description
Pin#
Table 1:
BG560 BGA — XCV405E and XCV812E
Bank
Pin Description
Pin#
NA
GND
AD33
NA
GND
A1
NA
GND
AE2
NA
GND
A7
NA
GND
AG1
NA
GND
A12
NA
GND
AG32
NA
GND
A14
NA
GND
AH2
NA
GND
A18
NA
GND
AJ33
NA
GND
A20
NA
GND
AL32
NA
GND
A24
NA
GND
AM3
NA
GND
A29
NA
GND
AM7
NA
GND
A32
NA
GND
AM11
NA
GND
A33
NA
GND
AM19
NA
GND
B1
NA
GND
AM25
NA
GND
B6
NA
GND
AM28
NA
GND
B9
NA
GND
AM33
NA
GND
B15
NA
GND
AN1
NA
GND
B23
NA
GND
AN2
NA
GND
B27
NA
GND
AN5
NA
GND
B31
NA
GND
AN10
NA
GND
C2
NA
GND
AN14
NA
GND
E1
NA
GND
AN16
NA
GND
F32
NA
GND
AN20
NA
GND
G2
NA
GND
AN22
NA
GND
G33
NA
GND
AN27
NA
GND
J32
NA
GND
AN33
NA
GND
K1
NA
GND
L2
NA
GND
M33
NA
GND
P1
NA
GND
P33
NA
GND
R32
NA
GND
T1
NA
GND
V33
NA
GND
W2
NA
GND
Y1
NA
GND
Y33
NA
GND
AB1
NA
GND
AC32
DS025-4 (v1.6) July 17, 2002
Notes:
1. VREF or I/O option only in the XCV812E.
www.xilinx.com
1-800-255-7778
Module 4 of 4
9
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
BG560 Differential Pin Pairs
Table 2:
Virtex-E Extended Memory devices have differential pin
pairs that can also provide other functions when not used as
a differential pair. A √ in the AO column indicates that the pin
pair can be used as an asynchronous output for all devices
provided in this package.
Pairs with a note number in the AO column are device
dependent. They can have asynchronous outputs if the pin
pair is in the same CLB row and column in the device. Numbers in this column refer to footnotes that indicate which
devices have pin pairs that can be asynchronous outputs.
The Other Functions column indicates alternative function(s) not available when the pair is used as a differential
pair or differential clock.
Table 2:
Pair
BG560 Package Differential Pin Pair Summary
XCV405E and XCV812E
Bank
P
Pin
N
Pin
AO
Other
Functions
Global Differential Clock
3
0
A17
C18
NA
IO LVDS 21
2
1
D17
E17
NA
IO LVDS 21
1
5
AJ17
AM18
NA
IO LVDS 115
0
4
AL17
AM17
NA
IO LVDS 115
IO LVDS
Total Outputs: 183, Asyncronous Outputs: 79
0
0
D29
E28
NA
-
1
0
A31
D28
√
-
2
0
C29
E27
√
VREF_0
3
0
D27
B30
1
-
4
0
B29
E26
√
-
5
0
C27
D26
√
VREF_0
6
0
A28
E25
NA
-
7
0
C26
D25
1
-
8
0
B26
E24
1
VREF_0
9
0
D24
C25
1
-
10
0
A25
E23
√
VREF_0
11
0
B24
D23
√
-
12
0
C23
E22
NA
-
13
0
D22
A23
√
-
14
0
B22
E21
√
VREF_0
15
0
C21
D21
1
-
Module 4 of 4
10
BG560 Package Differential Pin Pair Summary
XCV405E and XCV812E
16
0
E20
B21
√
-
17
0
C20
D20
√
VREF_0
18
0
E19
B20
NA
-
19
0
C19
D19
1
-
20
0
D18
A19
1
VREF_0
21
1
E17
C18
NA
GCLK LVDS 3/2
22
1
B17
C17
1
-
23
1
D16
B16
1
VREF_1
24
1
C16
E16
1
-
25
1
C15
A15
NA
-
26
1
E15
D15
√
VREF_1
27
1
D14
C14
√
-
28
1
E14
A13
1
-
29
1
D13
C13
√
VREF_1
30
1
E13
C12
√
-
31
1
D12
A11
NA
-
32
1
C11
B11
√
-
33
1
D11
B10
√
VREF_1
34
1
A9
C10
2
-
35
1
D10
C9
1
VREF_1
36
1
B8
A8
1
-
37
1
C8
E10
NA
-
38
1
A6
B7
√
VREF_1
39
1
D8
C7
√
-
40
1
B5
A5
2
-
41
1
D7
C6
√
VREF_1
42
1
B4
A4
√
-
43
1
E7
C5
NA
-
44
1
A2
D6
√
CS
45
2
D4
E4
√
DIN_D0
46
2
F5
B3
2
-
47
2
F4
C1
NA
-
48
2
G5
E3
1
VREF_2
49
2
D2
G4
1
-
www.xilinx.com
1-800-255-7778
DS025-4 (v1.6) July 17, 2002
R
Table 2:
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
BG560 Package Differential Pin Pair Summary
XCV405E and XCV812E
Table 2:
BG560 Package Differential Pin Pair Summary
XCV405E and XCV812E
50
2
H5
E2
NA
-
84
3
AG2
AE4
NA
-
51
2
H4
G3
√
VREF_2
85
3
AH1
AE5
√
VREF_3
52
2
J5
F1
NA
-
86
3
AF4
AJ1
NA
-
53
2
J4
H3
2
-
87
3
AJ2
AF5
2
-
54
2
K5
H2
NA
VREF_2
88
3
AG4
AK2
1
VREF_3
55
2
J3
K4
NA
-
89
3
AJ3
AG5
NA
-
56
2
L5
K3
√
D1
90
3
AL1
AH4
NA
-
57
2
L4
K2
√
D2
91
3
AJ4
AH5
√
INIT
58
2
M5
L3
2
-
92
4
AL4
AJ6
√
-
59
2
L1
M4
NA
-
93
4
AK5
AN3
NA
-
60
2
N5
M2
1
VREF_2
94
4
AL5
AJ7
√
-
61
2
N4
N3
1
-
95
4
AM4
AM5
√
VREF_4
62
2
N2
P5
NA
-
96
4
AK7
AL6
1
-
63
2
P4
P3
√
D3
97
4
AM6
AN6
√
-
64
2
P2
R5
2
-
98
4
AL7
AJ9
√
VREF_4
65
2
R4
R3
NA
-
99
4
AN7
AL8
NA
-
66
2
R1
T4
NA
VREF_2
100
4
AM8
AJ10
1
-
67
2
T5
T3
NA
-
101
4
AL9
AM9
1
VREF_4
68
2
T2
U3
√
IRDY
102
4
AK10
AN9
1
-
69
3
U1
U2
NA
-
103
4
AL10
AM10
√
VREF_4
70
3
V2
V4
NA
VREF_3
104
4
AL11
AJ12
√
-
71
3
V5
V3
NA
-
105
4
AN11
AK12
NA
-
72
3
W1
W3
2
-
106
4
AL12
AM12
√
-
73
3
W4
W5
√
VREF_3
107
4
AK13
AL13
√
VREF_4
74
3
Y3
Y4
NA
-
108
4
AM13
AN13
1
-
75
3
AA1
Y5
1
-
109
4
AJ14
AK14
√
-
76
3
AA3
AA4
1
VREF_3
110
4
AM14
AN15
√
VREF_4
77
3
AB3
AA5
NA
-
111
4
AJ15
AK15
NA
-
78
3
AC1
AB4
2
-
112
4
AL15
AM16
1
-
79
3
AC3
AB5
√
D5
113
4
AL16
AJ16
1
VREF_4
80
3
AC4
AD3
√
VREF_3
114
4
AK16
AN17
1
-
81
3
AE1
AC5
1
-
115
5
AM17
AM18
NA
GCLK LVDS 1/0
82
3
AD4
AF1
NA
VREF_3
116
5
AK18
AJ18
1
VREF_5
83
3
AF2
AD5
NA
-
117
5
AN19
AL19
1
-
DS025-4 (v1.6) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 4 of 4
11
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 2:
BG560 Package Differential Pin Pair Summary
XCV405E and XCV812E
Table 2:
BG560 Package Differential Pin Pair Summary
XCV405E and XCV812E
118
5
AK19
AM20
NA
-
152
6
AA31
AA30
1
VREF_6
119
5
AJ19
AL20
√
VREF_5
153
6
Y29
AA32
1
-
120
5
AN21
AL21
√
-
154
6
Y30
AA33
NA
-
121
5
AJ20
AM22
1
-
155
6
W29
Y32
√
VREF_6
122
5
AK21
AN23
√
VREF_5
156
6
W31
W30
2
-
123
5
AJ21
AM23
√
-
157
6
V30
W33
NA
-
124
5
AK22
AM24
NA
-
158
6
V31
V29
NA
VREF_6
125
5
AL23
AJ22
√
-
159
6
U33
V32
NA
-
126
5
AK23
AL24
√
VREF_5
160
7
U32
U31
√
IRDY
127
5
AN26
AJ23
2
-
161
7
T30
T32
NA
-
128
5
AK24
AM26
1
VREF_5
162
7
T31
T29
NA
VREF_7
129
5
AM27
AJ24
1
-
163
7
R31
R33
NA
-
130
5
AL26
AK25
NA
-
164
7
R29
R30
2
-
131
5
AN29
AJ25
√
VREF_5
165
7
P31
P32
√
VREF_7
132
5
AK26
AM29
√
-
166
7
P29
P30
NA
-
133
5
AM30
AJ26
2
-
167
7
N31
M32
1
-
134
5
AK27
AL29
√
VREF_5
168
7
L33
N30
1
VREF_7
135
5
AN31
AJ27
√
-
169
7
L32
M31
NA
-
136
5
AM31
AK28
NA
-
170
7
L31
M30
2
-
137
6
AJ30
AH29
√
-
171
7
J33
M29
√
-
138
6
AH30
AK31
2
-
172
7
K31
L30
√
VREF_7
139
6
AJ31
AG29
NA
-
173
7
H33
L29
1
-
140
6
AG30
AK32
1
VREF_6
174
7
H32
J31
NA
VREF_7
141
6
AF29
AH31
1
-
175
7
H31
K29
NA
-
142
6
AF30
AH32
NA
-
176
7
G32
J30
NA
-
143
6
AH33
AE29
√
VREF_6
177
7
G31
J29
√
VREF_7
144
6
AE30
AG33
2
-
178
7
E32
E33
NA
-
145
6
AF32
AD29
NA
-
179
7
F31
H29
2
-
146
6
AD30
AE31
NA
VREF_6
180
7
E31
D32
1
VREF_7
147
6
AC29
AE32
NA
-
181
7
C33
G29
NA
-
148
6
AC30
AD31
√
VREF_6
182
7
D31
F30
NA
-
149
6
AC31
AB29
√
-
150
6
AB30
AC33
2
-
151
6
AA29
AB31
NA
-
Module 4 of 4
12
Notes:
1. AO in the XCV812E
2. AO in the XCV405E
www.xilinx.com
1-800-255-7778
DS025-4 (v1.6) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
FG676 Fine-Pitch Ball Grid Array Package
XCV405E Virtex-E Extended Memory devices are available
in the FG676 fine-pitch BGA package. Pins labeled
I0_VREF can be used as either. If the pin is not used as
VREF, it can be used as general I/O. Immediately following
Table 3, see Table 4 for FG676 package Differential Pair
information.
Table 3:
Table 3:
FG676 Fine-Pitch BGA — XCV405E
Bank
Pin Description
Pin #
0
IO_L11N_YY
C9
0
IO_L11P_YY
F10
0
IO_L12N_Y
A8
0
IO_L12P_Y
E10
0
IO_L13N_YY
G11
0
IO_L13P_YY
D10
0
IO_L14N_YY
B10
0
IO_L14P_YY
F11
0
IO_L15N
C10
0
IO_L15P
E11
0
IO_L16N_YY
G12
0
IO_L16P_YY
D11
0
IO_VREF_L17N_YY
C11
0
IO_L17P_YY
F12
0
IO_L18N_YY
A11
0
IO_L18P_YY
E12
0
IO_L19N_Y
D12
0
IO_L19P_Y
C12
0
IO_VREF_L20N_Y
A12
0
IO_L20P_Y
H13
0
IO_LVDS_DLL_L21N
B13
1
GCK2
C13
1
IO
A19
1
IO
A20
1
IO
A22
1
IO
B23
1
IO_LVDS_DLL_L21P
F14
1
IO_L22N
E14
1
IO_L22P
F13
1
IO_L23N_Y
D14
1
IO_VREF_L23P_Y
A14
1
IO_L24N_Y
C14
1
IO_L24P_Y
H14
1
IO_L25N_YY
G14
FG676 Fine-Pitch BGA — XCV405E
Bank
Pin Description
Pin #
0
GCK3
E13
0
IO
A6
0
IO
B3
0
IO
C6
0
IO
C8
0
IO
D5
0
IO
G13
0
IO_L0N_Y
C4
0
IO_L0P_Y
F7
0
IO_L1N_YY
G8
0
IO_L1P_YY
C5
0
IO_VREF_L2N_YY
D6
0
IO_L2P_YY
E7
0
IO_L3N
A4
0
IO_L3P
F8
0
IO_L4N
B5
0
IO_L4P
D7
0
IO_VREF_L5N_YY
E8
0
IO_L5P_YY
G9
0
IO_L6N_YY
A5
0
IO_L6P_YY
F9
0
IO_L7N_Y
D8
0
IO_L7P_Y
C7
0
IO_L8N_Y
B7
0
IO_L8P_Y
E9
0
IO_L9N
A7
0
IO_L9P
D9
0
IO_L10N
B8
0
IO_VREF_L10P
G10
DS025-4 (v1.6) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 4 of 4
13
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 3:
FG676 Fine-Pitch BGA — XCV405E
Table 3:
FG676 Fine-Pitch BGA — XCV405E
Bank
Pin Description
Pin #
Bank
Pin Description
Pin #
1
IO_L25P_YY
C15
1
IO_L43N_Y
A23
1
IO_L26N_YY
E15
1
IO_L43P_Y
D21
1
IO_VREF_L26P_YY
D15
1
IO_WRITE_L44N_YY
C22
1
IO_L27N_YY
C16
1
IO_CS_L44P_YY
E21
1
IO_L27P_YY
F15
1
IO_L28N
G15
2
IO
D26
1
IO_L28P
D16
2
IO
E26
1
IO_L29N_YY
E16
2
IO
F26
1
IO_L29P_YY
A17
2
IO_D1
K24
1
IO_L30N_YY
C17
2
IO_DOUT_BUSY_L45P_YY
E23
1
IO_L30P_YY
E17
2
IO_DIN_D0_L45N_YY
F22
1
IO_L31N_Y
F16
2
IO_L46P_YY
E24
1
IO_L31P_Y
D17
2
IO_L46N_YY
F20
1
IO_L32N_YY
F17
2
IO_L47P_Y
G21
1
IO_L32P_YY
C18
2
IO_L47N_Y
G22
1
IO_L33N_YY
A18
2
IO_VREF_L48P_Y
F24
1
IO_VREF_L33P_YY
G16
2
IO_L48N_Y
H20
1
IO_L34N_YY
C19
2
IO_L49P_Y
E25
1
IO_L34P_YY
G17
2
IO_L49N_Y
H21
1
IO_L35N_Y
D18
2
IO_L50P_YY
F23
1
IO_L35P_Y
B19
2
IO_L50N_YY
G23
1
IO_L36N_Y
D19
2
IO_VREF_L51P_YY
H23
1
IO_L36P_Y
E18
2
IO_L51N_YY
J20
1
IO_L37N_YY
F18
2
IO_L52P_YY
G24
1
IO_L37P_YY
B20
2
IO_L52N_YY
H22
1
IO_L38N_YY
G19
2
IO_L53P_Y
J21
1
IO_VREF_L38P_YY
C20
2
IO_L53N_Y
G25
1
IO_L39N_YY
G18
2
IO_L54P_Y
G26
1
IO_L39P_YY
E19
2
IO_L54N_Y
J22
1
IO_L40N_YY
A21
2
IO_L55P_YY
H24
1
IO_L40P_YY
D20
2
IO_L55N_YY
J23
1
IO_L41N_YY
F19
2
IO_L56P_YY
J24
1
IO_VREF_L41P_YY
C21
2
IO_VREF_L56N_YY
K20
1
IO_L42N_YY
B22
2
IO_D2_L57P_YY
K22
1
IO_L42P_YY
E20
2
IO_L57N_YY
K21
Module 4 of 4
14
www.xilinx.com
1-800-255-7778
DS025-4 (v1.6) July 17, 2002
R
Table 3:
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 3:
FG676 Fine-Pitch BGA — XCV405E
FG676 Fine-Pitch BGA — XCV405E
Bank
Pin Description
Pin #
Bank
Pin Description
Pin #
2
IO_L58P_YY
H25
3
IO_L72N_YY
R22
2
IO_L58N_YY
K23
3
IO_D4_L73P_YY
R24
2
IO_L59P_Y
L20
3
IO_VREF_L73N_YY
R23
2
IO_L59N_Y
J26
3
IO_L74P_Y
T24
2
IO_L60P_Y
K25
3
IO_L74N_Y
R20
2
IO_L60N_Y
L22
3
IO_L75P_Y
T22
2
IO_L61P_Y
L21
3
IO_L75N_Y
U24
2
IO_L61N_Y
L23
3
IO_L76P_Y
T23
2
IO_L62P_Y
M20
3
IO_L76N_Y
U25
2
IO_L62N_Y
L24
3
IO_L77P_Y
T21
2
IO_VREF_L63P_YY
M23
3
IO_L77N_Y
U20
2
IO_D3_L63N_YY
M22
3
IO_L78P_YY
U22
2
IO_L64P_YY
L26
3
IO_L78N_YY
V26
2
IO_L64N_YY
M21
3
IO_L79P_YY
T20
2
IO_L65P_Y
N19
3
IO_D5_L79N_YY
U23
2
IO_L65N_Y
M24
3
IO_D6_L80P_YY
V24
2
IO_VREF_L66P_Y
M26
3
IO_VREF_L80N_YY
U21
2
IO_L66N_Y
N20
3
IO_L81P_YY
V23
2
IO_L67P_YY
N24
3
IO_L81N_YY
W24
2
IO_L67N_YY
N21
3
IO_L82P_Y
V22
2
IO_L68P_YY
N23
3
IO_L82N_Y
W26
2
IO_L68N_YY
N22
3
IO_L83P_Y
Y25
3
IO_L83N_Y
V21
3
IO
P24
3
IO_L84P_YY
V20
3
IO
W25
3
IO_L84N_YY
AA26
3
IO
Y26
3
IO_L85P_YY
Y24
3
IO
AB25
3
IO_VREF_L85N_YY
W23
3
IO
AC26
3
IO_L86P_Y
AA24
3
IO_L69P_YY
P21
3
IO_L86N_Y
Y23
3
IO_L69N_YY
P23
3
IO_L87P_Y
AB26
3
IO_L70P_Y
P22
3
IO_L87N_Y
W21
3
IO_VREF_L70N_Y
R25
3
IO_L88P_Y
Y22
3
IO_L71P_Y
P19
3
IO_VREF_L88N_Y
W22
3
IO_L71N_Y
P20
3
IO_L89P_Y
AA23
3
IO_L72P_YY
R21
3
IO_L89N_Y
AB24
DS025-4 (v1.6) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 4 of 4
15
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 3:
FG676 Fine-Pitch BGA — XCV405E
Table 3:
FG676 Fine-Pitch BGA — XCV405E
Bank
Pin Description
Pin #
Bank
Pin Description
Pin #
3
IO_L90P_YY
W20
4
IO_L104N_YY
AA17
3
IO_L90N_YY
AC24
4
IO_L105P_Y
AC17
3
IO_D7_L91P_YY
AB23
4
IO_L105N_Y
AB17
3
IO_INIT_L91N_YY
Y21
4
IO_L106P_YY
Y16
4
IO_L106N_YY
AE17
4
GCK0
AA14
4
IO_L107P_YY
AF17
4
IO
AC18
4
IO_L107N_YY
AA16
4
IO
AE20
4
IO_L108P
AD17
4
IO
AE23
4
IO_L108N
AB16
4
IO
AF21
4
IO_L109P_YY
AC16
4
IO_L92P_YY
AC22
4
IO_L109N_YY
AD16
4
IO_L92N_YY
AD26
4
IO_VREF_L110P_YY
AC15
4
IO_L93P_Y
AD23
4
IO_L110N_YY
Y15
4
IO_L93N_Y
AA20
4
IO_L111P_YY
AD15
4
IO_L94P_YY
Y19
4
IO_L111N_YY
AA15
4
IO_L94N_YY
AC21
4
IO_L112P_Y
W14
4
IO_VREF_L95P_YY
AD22
4
IO_L112N_Y
AB15
4
IO_L95N_YY
AB20
4
IO_VREF_L113P_Y
AF15
4
IO_L96P
AE22
4
IO_L113N_Y
Y14
4
IO_L96N
Y18
4
IO_L114P
AD14
4
IO_L97P
AF22
4
IO_L114N
AB14
4
IO_L97N
AA19
4
IO_LVDS_DLL_L115P
AC14
4
IO_VREF_L98P_YY
AD21
4
IO_L98N_YY
AB19
5
GCK1
AB13
4
IO_L99P_YY
AC20
5
IO
AD7
4
IO_L99N_YY
AA18
5
IO
AD13
4
IO_L100P_Y
AC19
5
IO
AE4
4
IO_L100N_Y
AD20
5
IO
AE7
4
IO_L101P_Y
AF20
5
IO
AF5
4
IO_L101N_Y
AB18
5
IO_LVDS_DLL_L115N
AF13
4
IO_L102P
AD19
5
IO_L116P_Y
AA13
4
IO_L102N
Y17
5
IO_VREF_L116N_Y
AF12
4
IO_L103P
AE19
5
IO_L117P_Y
AC13
4
IO_VREF_L103N
AD18
5
IO_L117N_Y
W13
4
IO_L104P_YY
AF19
5
IO_L118P_YY
AA12
Module 4 of 4
16
www.xilinx.com
1-800-255-7778
DS025-4 (v1.6) July 17, 2002
R
Table 3:
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
FG676 Fine-Pitch BGA — XCV405E
Table 3:
FG676 Fine-Pitch BGA — XCV405E
Bank
Pin Description
Pin #
Bank
Pin Description
Pin #
5
IO_L118N_YY
AD12
5
IO_L136P_Y
AF4
5
IO_L119P_YY
AC12
5
IO_L136N_Y
AC5
5
IO_VREF_L119N_YY
AB12
5
IO_L120P_YY
AD11
6
IO
P3
5
IO_L120N_YY
Y12
6
IO
AA3
5
IO_L121P
AB11
6
IO
W3
5
IO_L121N
AD10
6
IO
Y2
5
IO_L122P_YY
AC11
6
IO
Y6
5
IO_L122N_YY
AE10
6
IO_L137N_YY
AA5
5
IO_L123P_YY
AC10
6
IO_L137P_YY
AC3
5
IO_L123N_YY
AA11
6
IO_L138N_YY
AC2
5
IO_L124P_Y
Y11
6
IO_L138P_YY
AB4
5
IO_L124N_Y
AD9
6
IO_L139N_Y
W6
5
IO_L125P_YY
AB10
6
IO_L139P_Y
AA4
5
IO_L125N_YY
AF9
6
IO_VREF_L140N_Y
AB3
5
IO_L126P_YY
AD8
6
IO_L140P_Y
Y5
5
IO_VREF_L126N_YY
AA10
6
IO_L141N_Y
AB2
5
IO_L127P_YY
AE8
6
IO_L141P_Y
V7
5
IO_L127N_YY
Y10
6
IO_L142N_YY
AB1
5
IO_L128P_Y
AC9
6
IO_L142P_YY
Y4
5
IO_L128N_Y
AF8
6
IO_VREF_L143N_YY
V5
5
IO_L129P_Y
AF7
6
IO_L143P_YY
W5
5
IO_L129N_Y
AB9
6
IO_L144N_YY
AA1
5
IO_L130P_YY
AA9
6
IO_L144P_YY
V6
5
IO_L130N_YY
AF6
6
IO_L145N_Y
W4
5
IO_L131P_YY
AC8
6
IO_L145P_Y
Y3
5
IO_VREF_L131N_YY
AC7
6
IO_L146N_Y
Y1
5
IO_L132P_YY
AD6
6
IO_L146P_Y
U7
5
IO_L132N_YY
Y9
6
IO_L147N_YY
W1
5
IO_L133P_YY
AE5
6
IO_L147P_YY
V4
5
IO_L133N_YY
AA8
6
IO_L148N_YY
W2
5
IO_L134P_YY
AC6
6
IO_VREF_L148P_YY
U6
5
IO_VREF_L134N_YY
AB8
6
IO_L149N_YY
V3
5
IO_L135P_YY
AD5
6
IO_L149P_YY
T5
5
IO_L135N_YY
AA7
6
IO_L150N_YY
U5
DS025-4 (v1.6) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 4 of 4
17
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 3:
Table 3:
FG676 Fine-Pitch BGA — XCV405E
FG676 Fine-Pitch BGA — XCV405E
Bank
Pin Description
Pin #
Bank
Pin Description
Pin #
6
IO_L150P_YY
U4
7
IO_L165N_YY
M4
6
IO_L151N_Y
T7
7
IO_VREF_L165P_YY
M5
6
IO_L151P_Y
U3
7
IO_L166N_Y
L3
6
IO_L152N_Y
U2
7
IO_L166P_Y
L7
6
IO_L152P_Y
T6
7
IO_L167N_Y
L6
6
IO_L153N_Y
U1
7
IO_L167P_Y
K2
6
IO_L153P_Y
T4
7
IO_L168N_Y
L4
6
IO_L154N_Y
R7
7
IO_L168P_Y
K1
6
IO_L154P_Y
T3
7
IO_L169N_Y
K3
6
IO_VREF_L155N_YY
R4
7
IO_L169P_Y
L5
6
IO_L155P_YY
R6
7
IO_L170N_YY
K5
6
IO_L156N_YY
R3
7
IO_L170P_YY
J3
6
IO_L156P_YY
R5
7
IO_L171N_YY
K4
6
IO_L157N_Y
P8
7
IO_L171P_YY
J4
6
IO_L157P_Y
P7
7
IO_L172N_YY
H3
6
IO_VREF_L158N_Y
R1
7
IO_VREF_L172P_YY
K6
6
IO_L158P_Y
P6
7
IO_L173N_YY
K7
6
IO_L159N_YY
P5
7
IO_L173P_YY
G3
6
IO_L159P_YY
P4
7
IO_L174N_Y
J5
7
IO_L174P_Y
H1
7
IO
D2
7
IO_L175N_Y
G2
7
IO
D3
7
IO_L175P_Y
J6
7
IO
E1
7
IO_L176N_YY
J7
7
IO
G1
7
IO_L176P_YY
F1
7
IO
H2
7
IO_L177N_YY
H4
7
IO_L160N_YY
N5
7
IO_VREF_L177P_YY
G4
7
IO_L160P_YY
N8
7
IO_L178N_Y
F3
7
IO_L161N_YY
N6
7
IO_L178P_Y
H5
7
IO_L161P_YY
N3
7
IO_L179N_Y
E2
7
IO_L162N_Y
N4
7
IO_L179P_Y
H6
7
IO_VREF_L162P_Y
M2
7
IO_L180N_Y
G5
7
IO_L163N_Y
N7
7
IO_VREF_L180P_Y
F4
7
IO_L163P_Y
M7
7
IO_L181N_Y
H7
7
IO_L164N_YY
M6
7
IO_L181P_Y
G6
7
IO_L164P_YY
M3
7
IO_L182N_YY
E3
Module 4 of 4
18
www.xilinx.com
1-800-255-7778
DS025-4 (v1.6) July 17, 2002
R
Table 3:
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 3:
FG676 Fine-Pitch BGA — XCV405E
FG676 Fine-Pitch BGA — XCV405E
Bank
Pin Description
Pin #
Bank
Pin Description
Pin #
7
IO_L182P_YY
E4
4
NC
AE15
4
NC
AF14
2
CCLK
D24
4
NC
AF16
3
DONE
AB21
4
NC
AF18
NA
DXN
AB7
4
NC
AF23
NA
DXP
Y8
5
NC
AE12
NA
M0
AD4
5
NC
AF3
NA
M1
W7
5
NC
AF10
NA
M2
AB6
5
NC
AF11
NA
PROGRAM
AA22
5
NC
Y13
NA
TCK
E6
6
NC
AC1
NA
TDI
D22
6
NC
P1
2
TDO
C23
6
NC
R2
NA
TMS
F5
6
NC
T1
6
NC
V1
0
NC
A9
7
NC
D1
0
NC
A10
7
NC
J1
0
NC
B4
7
NC
L1
0
NC
B12
7
NC
M1
0
NC
D13
7
NC
N1
1
NC
A13
NA
NC
T25
1
NC
A16
NA
NC
T2
1
NC
A24
NA
NC
P2
1
NC
B15
NA
NC
N25
1
NC
B17
NA
NC
L25
2
NC
D25
NA
NC
L2
2
NC
H26
NA
NC
F6
2
NC
K26
NA
NC
F25
2
NC
M25
NA
NC
F21
2
NC
N26
NA
NC
F2
3
NC
AC25
NA
NC
C26
3
NC
P26
NA
NC
C25
3
NC
R26
NA
NC
C2
3
NC
T26
NA
NC
C1
3
NC
U26
NA
NC
B6
DS025-4 (v1.6) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 4 of 4
19
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 3:
Table 3:
FG676 Fine-Pitch BGA — XCV405E
FG676 Fine-Pitch BGA — XCV405E
Bank
Pin Description
Pin #
Bank
Pin Description
Pin #
NA
NC
B26
NA
VCCINT
J10
NA
NC
B24
NA
VCCINT
J11
NA
NC
B21
NA
VCCINT
J16
NA
NC
B16
NA
VCCINT
J17
NA
NC
B11
NA
VCCINT
J18
NA
NC
B1
NA
VCCINT
K9
NA
NC
AF25
NA
VCCINT
K18
NA
NC
AF24
NA
VCCINT
L9
NA
NC
AF2
NA
VCCINT
L18
NA
NC
AE6
NA
VCCINT
T9
NA
NC
AE3
NA
VCCINT
T18
NA
NC
AE26
NA
VCCINT
U9
NA
NC
AE24
NA
VCCINT
U18
NA
NC
AE21
NA
VCCINT
V9
NA
NC
AE16
NA
VCCINT
V10
NA
NC
AE14
NA
VCCINT
V11
NA
NC
AE11
NA
VCCINT
V16
NA
NC
AE1
NA
VCCINT
V17
NA
NC
AD25
NA
VCCINT
V18
NA
NC
AD2
NA
VCCINT
Y7
NA
NC
AD1
NA
VCCINT
Y20
NA
NC
AA6
NA
VCCINT
W8
NA
NC
AA25
NA
VCCINT
W19
NA
NC
AA21
NA
NC
AA2
0
VCCO
J13
NA
NC
A3
0
VCCO
J12
NA
NC
A25
0
VCCO
H9
NA
NC
A2
0
VCCO
H12
NA
NC
A15
0
VCCO
H11
0
VCCO
H10
NA
VCCINT
G7
1
VCCO
J15
NA
VCCINT
G20
1
VCCO
J14
NA
VCCINT
H8
1
VCCO
H18
NA
VCCINT
H19
1
VCCO
H17
NA
VCCINT
J9
1
VCCO
H16
Module 4 of 4
20
www.xilinx.com
1-800-255-7778
DS025-4 (v1.6) July 17, 2002
R
Table 3:
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
FG676 Fine-Pitch BGA — XCV405E
Table 3:
FG676 Fine-Pitch BGA — XCV405E
Bank
Pin Description
Pin #
Bank
Pin Description
Pin #
1
VCCO
H15
7
VCCO
K8
2
VCCO
N18
7
VCCO
J8
2
VCCO
M19
2
VCCO
M18
NA
GND
V25
2
VCCO
L19
NA
GND
V2
2
VCCO
K19
NA
GND
U17
2
VCCO
J19
NA
GND
U16
3
VCCO
V19
NA
GND
U15
3
VCCO
U19
NA
GND
U14
3
VCCO
T19
NA
GND
U13
3
VCCO
R19
NA
GND
U12
3
VCCO
R18
NA
GND
U11
3
VCCO
P18
NA
GND
U10
4
VCCO
W18
NA
GND
T17
4
VCCO
W17
NA
GND
T16
4
VCCO
W16
NA
GND
T15
4
VCCO
W15
NA
GND
T14
4
VCCO
V15
NA
GND
T13
4
VCCO
V14
NA
GND
T12
5
VCCO
W9
NA
GND
T11
5
VCCO
W12
NA
GND
T10
5
VCCO
W11
NA
GND
R17
5
VCCO
W10
NA
GND
R16
5
VCCO
V13
NA
GND
R15
5
VCCO
V12
NA
GND
R14
6
VCCO
V8
NA
GND
R13
6
VCCO
U8
NA
GND
R12
6
VCCO
T8
NA
GND
R11
6
VCCO
R9
NA
GND
R10
6
VCCO
R8
NA
GND
P25
6
VCCO
P9
NA
GND
P17
7
VCCO
N9
NA
GND
P16
7
VCCO
M9
NA
GND
P15
7
VCCO
M8
NA
GND
P14
7
VCCO
L8
NA
GND
P13
DS025-4 (v1.6) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 4 of 4
21
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 3:
FG676 Fine-Pitch BGA — XCV405E
Table 3:
FG676 Fine-Pitch BGA — XCV405E
Bank
Pin Description
Pin #
Bank
Pin Description
Pin #
NA
GND
P12
NA
GND
K10
NA
GND
P11
NA
GND
J25
NA
GND
P10
NA
GND
J2
NA
GND
N2
NA
GND
E5
NA
GND
N17
NA
GND
E22
NA
GND
N16
NA
GND
D4
NA
GND
N15
NA
GND
D23
NA
GND
N14
NA
GND
C3
NA
GND
N13
NA
GND
C24
NA
GND
N12
NA
GND
B9
NA
GND
N11
NA
GND
B25
NA
GND
N10
NA
GND
B2
NA
GND
M17
NA
GND
B18
NA
GND
M16
NA
GND
B14
NA
GND
M15
NA
GND
AF26
NA
GND
M14
NA
GND
AF1
NA
GND
M13
NA
GND
AE9
NA
GND
M12
NA
GND
AE25
NA
GND
M11
NA
GND
AE2
NA
GND
M10
NA
GND
AE18
NA
GND
L17
NA
GND
AE13
NA
GND
L16
NA
GND
AD3
NA
GND
L15
NA
GND
AD24
NA
GND
L14
NA
GND
AC4
NA
GND
L13
NA
GND
AC23
NA
GND
L12
NA
GND
AB5
NA
GND
L11
NA
GND
AB22
NA
GND
L10
NA
GND
A26
NA
GND
K17
NA
GND
A1
NA
GND
K16
NA
GND
K15
NA
GND
K14
NA
GND
K13
NA
GND
K12
NA
GND
K11
Module 4 of 4
22
www.xilinx.com
1-800-255-7778
DS025-4 (v1.6) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
FG676 Differential Pin Pairs
Table 4:
Virtex-E Extended Memory devices have differential pin
pairs that can also provide other functions when not used as
a differential pair. A √ in the AO column indicates that the pin
pair can be used as an asynchronous output for all devices
provided in this package.
FG676 Fine-Pitch BGA Differential Pin Pair
Summary — XCV405E
P
N
Other
Pair
Bank
Pin
Pin
AO
Functions
16
0
D11
G12
√
-
Pairs with a note number in the AO column are device
dependent. They can have asynchronous outputs if the pin
pair is in the same CLB row and column in the device. Numbers in this column refer to footnotes that indicate which
devices have pin pairs that can be asynchronous outputs.
The Other Functions column indicates alternative function(s) not available when the pair is used as a differential
pair or differential clock.
17
0
F12
C11
√
VREF
18
0
E12
A11
√
-
19
0
C12
D12
NA
-
20
0
H13
A12
NA
VREF
21
1
F14
B13
NA
IO_LVDS_DLL
22
1
F13
E14
NA
-
Table 4:
23
1
A14
D14
NA
VREF
24
1
H14
C14
NA
-
25
1
C15
G14
√
-
26
1
D15
E15
√
VREF
27
1
F15
C16
√
-
28
1
D16
G15
-
-
29
1
A17
E16
√
-
30
1
E17
C17
√
-
31
1
D17
F16
NA
-
32
1
C18
F17
√
-
33
1
G16
A18
√
VREF
Pair
FG676 Fine-Pitch BGA Differential Pin Pair
Summary — XCV405E
Bank
P
N
Pin
Pin
Other
AO
Functions
Global Differential Clock
3
0
E13
B13
NA
IO_DLL_L21N
2
1
C13
F14
NA
IO_DLL_L21P
1
5
AB13
AF13
NA
IO_DLL_L115
N
0
4
AA14
AC14
NA
IO_DLL_L115P
IOLVDS
Total Pairs: 183, Asynchronous Output Pairs: 97
0
0
F7
C4
NA
-
34
1
G17
C19
√
-
1
0
C5
G8
√
-
35
1
B19
D18
NA
-
2
0
E7
D6
√
VREF
36
1
E18
D19
NA
-
3
0
F8
A4
NA
-
37
1
B20
F18
√
-
4
0
D7
B5
NA
-
38
1
C20
G19
√
VREF
5
0
G9
E8
√
VREF
39
1
E19
G18
√
-
6
0
F9
A5
√
-
40
1
D20
A21
√
-
7
0
C7
D8
NA
-
41
1
C21
F19
√
VREF
8
0
E9
B7
NA
-
42
1
E20
B22
√
-
9
0
D9
A7
NA
-
43
1
D21
A23
2
-
10
0
G10
B8
NA
VREF
44
1
E21
C22
√
CS
11
0
F10
C9
√
-
45
2
E23
F22
√
DIN, D0
12
0
E10
A8
NA
-
46
2
E24
F20
√
-
13
0
D10
G11
√
-
47
2
G21
G22
2
-
14
0
F11
B10
√
-
48
2
F24
H20
1
VREF
15
0
E11
C10
NA
-
49
2
E25
H21
1
-
DS025-4 (v1.6) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 4 of 4
23
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 4:
FG676 Fine-Pitch BGA Differential Pin Pair
Summary — XCV405E
P
N
Table 4:
FG676 Fine-Pitch BGA Differential Pin Pair
Summary — XCV405E
Other
P
N
Other
Pair
Bank
Pin
Pin
AO
Functions
Pair
Bank
Pin
Pin
AO
Functions
50
2
F23
G23
√
-
84
3
V20
AA26
√
-
51
2
H23
J20
√
VREF
85
3
Y24
W23
√
VREF
52
2
G24
H22
√
-
86
3
AA24
Y23
NA
-
53
2
J21
G25
2
-
87
3
AB26
W21
NA
-
54
2
G26
J22
1
-
88
3
Y22
W22
NA
VREF
55
2
H24
J23
√
-
89
3
AA23
AB24
NA
-
56
2
J24
K20
√
VREF
90
3
W20
AC24
√
-
57
2
K22
K21
√
D2
91
3
AB23
Y21
√
INIT
58
2
H25
K23
√
-
92
4
AC22
AD26
√
-
59
2
L20
J26
2
-
93
4
AD23
AA20
NA1
-
60
2
K25
L22
1
-
94
4
Y19
AC21
√
-
61
2
L21
L23
1
-
95
4
AD22
AB20
√
VREF
62
2
M20
L24
1
-
96
4
AE22
Y18
NA
-
63
2
M23
M22
√
D3
97
4
AF22
AA19
NA
-
64
2
L26
M21
√
-
98
4
AD21
AB19
√
VREF
65
2
N19
M24
2
-
99
4
AC20
AA18
√
-
66
2
M26
N20
1
VREF
100
4
AC19
AD20
NA
-
67
2
N24
N21
√
-
101
4
AF20
AB18
NA
-
68
2
N23
N22
√
-
102
4
AD19
Y17
NA
-
69
3
P21
P23
√
-
103
4
AE19
AD18
NA
VREF
70
3
P22
R25
1
VREF
104
4
AF19
AA17
√
-
71
3
P19
P20
2
-
105
4
AC17
AB17
NA
-
72
3
R21
R22
√
-
106
4
Y16
AE17
√
-
73
3
R24
R23
√
VREF
107
4
AF17
AA16
√
-
74
3
T24
R20
1
-
108
4
AD17
AB16
NA
-
75
3
T22
U24
1
-
109
4
AC16
AD16
√
-
76
3
T23
U25
1
-
110
4
AC15
Y15
√
VREF
77
3
T21
U20
2
-
111
4
AD15
AA15
√
-
78
3
U22
V26
√
-
112
4
W14
AB15
NA
-
79
3
T20
U23
√
D5
113
4
AF15
Y14
NA
VREF
80
3
V24
U21
√
VREF
114
4
AD14
AB14
NA
-
81
3
V23
W24
√
-
115
5
AC14
AF13
NA
IO_LVDS_DLL
82
3
V22
W26
NA
-
116
5
AA13
AF12
NA
VREF
83
3
Y25
V21
NA
-
117
5
AC13
W13
NA
-
Module 4 of 4
24
www.xilinx.com
1-800-255-7778
DS025-4 (v1.6) July 17, 2002
R
Table 4:
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
FG676 Fine-Pitch BGA Differential Pin Pair
Summary — XCV405E
P
N
Table 4:
FG676 Fine-Pitch BGA Differential Pin Pair
Summary — XCV405E
Other
P
N
Other
Pair
Bank
Pin
Pin
AO
Functions
Pair
Bank
Pin
Pin
AO
Functions
118
5
AA12
AD12
√
-
152
6
T6
U2
NA
-
119
5
AC12
AB12
√
VREF
153
6
T4
U1
NA
-
120
5
AD11
Y12
√
-
154
6
T3
R7
NA
-
121
5
AB11
AD10
NA
-
155
6
R6
R4
√
VREF
122
5
AC11
AE10
√
-
156
6
R5
R3
√
-
123
5
AC10
AA11
√
-
157
6
P7
P8
NA
-
124
5
Y11
AD9
NA
-
158
6
P6
R1
NA
VREF
125
5
AB10
AF9
√
-
159
6
P4
P5
√
-
126
5
AD8
AA10
√
VREF
160
7
N8
N5
√
-
127
5
AE8
Y10
√
-
161
7
N3
N6
√
-
128
5
AC9
AF8
NA
-
162
7
M2
N4
NA
VREF
129
5
AF7
AB9
NA
-
163
7
M7
N7
NA
-
130
5
AA9
AF6
√
-
164
7
M3
M6
√
-
131
5
AC8
AC7
√
VREF
165
7
M5
M4
√
VREF
132
5
AD6
Y9
√
-
166
7
L7
L3
NA
-
133
5
AE5
AA8
√
-
167
7
K2
L6
NA
-
134
5
AC6
AB8
√
VREF
168
7
K1
L4
NA
-
135
5
AD5
AA7
√
-
169
7
L5
K3
NA
-
136
5
AF4
AC5
NA
-
170
7
J3
K5
√
-
137
6
AC3
AA5
√
-
171
7
J4
K4
√
-
138
6
AB4
AC2
√
-
172
7
K6
H3
√
VREF
139
6
AA4
W6
NA
-
173
7
G3
K7
√
-
140
6
Y5
AB3
NA
VREF
174
7
H1
J5
NA
-
141
6
V7
AB2
NA
-
175
7
J6
G2
NA
-
142
6
Y4
AB1
√
-
176
7
F1
J7
√
-
143
6
W5
V5
√
VREF
177
7
G4
H4
√
VREF
144
6
V6
AA1
√
-
178
7
H5
F3
NA
-
145
6
Y3
W4
NA
-
179
7
H6
E2
NA
-
146
6
U7
Y1
NA
-
180
7
F4
G5
NA
VREF
147
6
V4
W1
√
-
181
7
G6
H7
NA
-
148
6
U6
W2
√
VREF
182
7
E4
E3
√
-
149
6
T5
V3
√
-
150
6
U4
U5
√
-
151
6
U3
T7
NA
-
DS025-4 (v1.6) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 4 of 4
25
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
FG900 Fine-Pitch Ball Grid Array Package
The XCV812E Virtex-E Extended Memory devices are
available in the FG900 fine-pitch BGA package. Pins
labeled I0_VREF can be used as either. If the pin is not
used as VREF, it can be used as general I/O. Immediately
following Table 5, see Table 6 for FG900 package Differential Pair information.
Table 5:
Table 5:
Bank
Description
Pin
0
IO_L8N_YY
G9
0
IO_L8P_YY
E8
0
IO_VREF_L9N_YY
A6
0
IO_L9P_YY
J11
0
IO_L10N
C7
0
IO_L10P
B7
0
IO_L11N
C8
0
IO_L11P
H10
0
IO_L12N_YY
G10
0
IO_L12P_YY
F10
0
IO_VREF_L13N_YY
A8
0
IO_L13P_YY
H11
0
IO_L15N
B9
0
IO_L15P
J12
0
IO_L17N
G11
0
IO_L17P
B10
0
IO_L19N_Y
H13
0
IO_L19P_Y
F11
0
IO_L20N_Y
E11
0
IO_L20P_Y
D11
0
IO_L22N_YY
F12
0
IO_L22P_YY
C11
0
IO_VREF_L23N_YY
A10
0
IO_L23P_YY
D12
0
IO_L24N
E12
0
IO_L24P
A11
0
IO_L25N
G13
0
IO_L25P
B12
0
IO_L26N_YY
A12
0
IO_L26P_YY
K13
0
IO_VREF_L27N_YY
F13
0
IO_L27P_YY
B13
0
IO_L28N
G14
0
IO_L28P
E13
FG900 Fine-Pitch BGA Package — XCV812E
Bank
Description
Pin
0
GCK3
C15
0
IO
A7
0
IO
A13
0
IO
C9
0
IO
C10
0
IO
D10
0
IO
E6
0
IO
F7
0
IO
F9
0
IO
F15
0
IO
G12
0
IO
G15
0
IO
H15
0
IO
J10
0
IO
K12
0
IO_VREF
A9
0
IO_L1N_Y
D5
0
IO_L1P_Y
G8
0
IO_L2N_Y
A3
0
IO_L2P_Y
H9
0
IO_L4N_YY
A4
0
IO_L4P_YY
D6
0
IO_VREF_L5N_YY
E7
0
IO_L5P_YY
B5
0
IO_L6N
A5
0
IO_L6P
F8
0
IO_L7N
D7
0
IO_L7P
N11
Module 4 of 4
26
FG900 Fine-Pitch BGA Package — XCV812E
www.xilinx.com
1-800-255-7778
DS025-4 (v1.6) July 17, 2002
R
Table 5:
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
FG900 Fine-Pitch BGA Package — XCV812E
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Bank
Description
Pin
Bank
Description
Pin
0
IO_L29N
D14
1
IO_L43P
G18
0
IO_L29P
B14
1
IO_L44N
D19
0
IO_L30N_YY
A14
1
IO_L44P
H18
0
IO_L30P_YY
J14
1
IO_L45N_YY
F18
0
IO_VREF_L31N_YY
K14
1
IO_VREF_L45P_YY
F19
0
IO_L31P_YY
J15
1
IO_L46N_YY
B20
0
IO_LVDS_DLL_L34N
A15
1
IO_L46P_YY
K17
1
IO_L48N_Y
G19
1
GCk2
E15
1
IO_L48P_Y
C20
1
IO
B18
1
IO_L49N_Y
K18
1
IO
B21
1
IO_L49P_Y
E20
1
IO
B28
1
IO_L51N_YY
F20
1
IO
C23
1
IO_L51P_YY
A21
1
IO
C26
1
IO_L52N_YY
C21
1
IO
D20
1
IO_VREF_L52P_YY
A22
1
IO
D23
1
IO_L53N
H19
1
IO_LVDS_DLL_L34P
E16
1
IO_L53P
B22
1
IO_L35N
B16
1
IO_L54N
E21
1
IO_L35P
F16
1
IO_L54P
D22
1
IO_L36N
A16
1
IO_L55N_YY
F21
1
IO_L36P
H16
1
IO_VREF_L55P_YY
C22
1
IO_L37N_YY
C16
1
IO_L56N_YY
H20
1
IO_VREF_L37P_YY
K15
1
IO_L56P_YY
E22
1
IO_L38N_YY
K16
1
IO_L57N
G21
1
IO_L38P_YY
G16
1
IO_L57P
A23
1
IO_L39N
A17
1
IO_L58N
A24
1
IO_L39P
E17
1
IO_L58P
K19
1
IO_L40N
F17
1
IO_L59N_YY
C24
1
IO_L40P
C17
1
IO_VREF_L59P_YY
B24
1
IO_L41N_YY
E18
1
IO_L60N_YY
H21
1
IO_VREF_L41P_YY
A18
1
IO_L60P_YY
G22
1
IO_L42N_YY
D18
1
IO_L61N
E23
1
IO_L42P_YY
A19
1
IO_L61P
C25
1
IO_L43N
B19
1
IO_L62N
D24
DS025-4 (v1.6) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 4 of 4
27
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Bank
Description
Pin
Bank
Description
Pin
1
IO_L62P
A26
2
IO_L76N_Y
F28
1
IO_L63N_YY
B26
2
IO_L77P_YY
G28
1
IO_VREF_L63P_YY
K20
2
IO_L77N_YY
E30
1
IO_L64N_YY
D25
2
IO_L78P
G27
1
IO_L64P_YY
J21
2
IO_L78N
E29
1
IO_L66N_Y
B27
2
IO_L79P
K23
1
IO_L66P_Y
G23
2
IO_L79N
H26
1
IO_L67N_Y
A27
2
IO_VREF_L80P_YY
F30
1
IO_L67P_Y
F24
2
IO_L80N_YY
L22
1
IO_WRITE_L69N_YY
K21
2
IO_L81P_YY
H27
1
IO_CS_L69P_YY
C27
2
IO_L81N_YY
G29
2
IO_L82P_Y
G30
2
IO
D28
2
IO_L82N_Y
M21
2
IO
F27
2
IO_L83P
J24
2
IO
H25
2
IO_L83N
J26
2
IO
J25
2
IO_VREF_L84P
H30
2
IO
J28
2
IO_L84N
L23
2
IO
K28
2
IO_L86P
J29
2
IO
K30
2
IO_L86N
K24
2
IO
M23
2
IO_VREF
J30
2
IO
N20
2
IO_D1_L88P
M22
2
IO
N23
2
IO_D2_L88N
K29
2
IO
R27
2
IO_L90P_Y
N21
2
IO
R28
2
IO_L90N_Y
K25
2
IO
R30
2
IO_L91P
L24
2
IO_DOUT_BUSY_L70P_YY
J22
2
IO_L91N
L27
2
IO_DIN_D0_L70N_YY
E27
2
IO_L93P
L26
2
IO_L72P_Y
G25
2
IO_L93N
L28
2
IO_L72N_Y
E25
2
IO_VREF_L94P_Y
L30
2
IO_L73P
E28
2
IO_L94N_Y
M27
2
IO_L73N
C30
2
IO_L95P_YY
M26
2
IO_L75P
D30
2
IO_L95N_YY
M29
2
IO_L75N
J23
2
IO_L96P
N29
2
IO_VREF_L76P_Y
L21
2
IO_L96N
M30
Module 4 of 4
28
www.xilinx.com
1-800-255-7778
DS025-4 (v1.6) July 17, 2002
R
Table 5:
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
FG900 Fine-Pitch BGA Package — XCV812E
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Bank
Description
Pin
Bank
Description
Pin
2
IO_L97P
N25
3
IO_L112P_YY
U25
2
IO_L97N
N27
3
IO_L112N_YY
V27
2
IO_VREF_L98P_YY
N30
3
IO_D4_L113P_YY
U24
2
IO_D3_L98N_YY
P21
3
IO_VREF_L113N_YY
V29
2
IO_L99P_YY
N26
3
IO_L114P
W30
2
IO_L99N_YY
P28
3
IO_L114N
U22
2
IO_L100P_Y
P29
3
IO_L115P
U21
2
IO_L100N_Y
N24
3
IO_L115N
W29
2
IO_L101P
P22
3
IO_L116P_YY
V26
2
IO_L101N
R26
3
IO_L116N_YY
W27
2
IO_VREF_2_L102P
P25
3
IO_L117P_Y
W26
2
IO_L102N
R29
3
IO_VREF_L117N_Y
Y29
2
IO_L104P
R25
3
IO_L118P
W25
2
IO_L104N
T30
3
IO_L118N
Y30
2
IO_L106P
R24
3
IO_L120P
AA30
3
IO_L120N
W24
3
IO
T24
3
IO_L121P_Y
AA29
3
IO
V24
3
IO_L121N_Y
V20
3
IO
Y21
3
IO_L123P_YY
Y26
3
IO
Y27
3
IO_D5_L123N_YY
AB30
3
IO
AB27
3
IO_D6_L124P_YY
V21
3
IO
AF28
3
IO_VREF_L124N_YY
AA28
3
IO
AG30
3
IO_L125P
Y25
3
IO_L106N
U29
3
IO_L125N
AA27
3
IO_L107P
R22
3
IO_L126P
W22
3
IO_L107N
T27
3
IO_L126N
Y23
3
IO_L108P
R23
3
IO_L127P
Y24
3
IO_L108N
T28
3
IO_VREF_L127N
AB28
3
IO_L109P
T21
3
IO_L128P
AC30
3
IO_VREF_L109N
T25
3
IO_L128N
AA25
3
IO_L110P
U28
3
IO_L129P_Y
W21
3
IO_L110N
U30
3
IO_L129N_Y
AA24
3
IO_L111P_Y
T23
3
IO_L130P_YY
AB26
3
IO_L111N_Y
U27
3
IO_L130N_YY
AD30
DS025-4 (v1.6) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 4 of 4
29
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Bank
Description
Pin
Bank
Description
Pin
3
IO_L131P_YY
Y22
4
IO_L142N_YY
AK28
3
IO_VREF_L131N_YY
AC27
4
IO_L144P_Y
AD23
3
IO_L132P
AD28
4
IO_L144N_Y
AJ27
3
IO_L132N
AB25
4
IO_L145P_Y
AB21
3
IO_L133P
AC26
4
IO_L145N_Y
AF25
3
IO_L133N
AE30
4
IO_L147P_YY
AA21
3
IO_L134P_YY
AD27
4
IO_L147N_YY
AG25
3
IO_L134N_YY
AF30
4
IO_VREF_4_L148P_YY
AJ26
3
IO_L135P_Y
AF29
4
IO_L148N_YY
AD22
3
IO_VREF_L135N_Y
AB24
4
IO_L149P
AA20
3
IO_L136P
AB23
4
IO_L149N
AH25
3
IO_L136N
AE28
4
IO_L150P
AC21
3
IO_L138P
AE26
4
IO_L150N
AF24
3
IO_L138N
AG29
4
IO_L151P_YY
AG24
3
IO_L139P_Y
AH30
4
IO_L151N_YY
AK26
3
IO_L139N_Y
AC24
4
IO_VREF_4_L152P_YY
AJ24
3
IO_D7_L141P_YY
AH29
4
IO_L152N_YY
AF23
3
IO_INIT_L141N_YY
AA22
4
IO_L153P
AE23
4
IO_L153N
AB20
4
GCK0
AJ16
4
IO_L154P
AC20
4
IO
AB19
4
IO_L154N
AG23
4
IO
AC16
4
IO_L155P_YY
AF22
4
IO
AC19
4
IO_L155N_YY
AE22
4
IO
AD19
4
IO_VREF_4_L156P_YY
AJ22
4
IO
AD20
4
IO_L156N_YY
AG22
4
IO
AE21
4
IO_L158P
AA19
4
IO
AF19
4
IO_L158N
AF21
4
IO
AH17
4
IO_L160P
AG21
4
IO
AH23
4
IO_L160N
AK23
4
IO
AH26
4
IO_L162P_Y
AE20
4
IO
AH27
4
IO_L162N_Y
AJ21
4
IO
AK18
4
IO_L163P_Y
AG20
4
IO_VREF_4
AA18
4
IO_L163N_Y
AF20
4
IO_L142P_YY
AF27
4
IO_L165P_YY
AJ20
Module 4 of 4
30
www.xilinx.com
1-800-255-7778
DS025-4 (v1.6) July 17, 2002
R
Table 5:
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
FG900 Fine-Pitch BGA Package — XCV812E
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Bank
Description
Pin
Bank
Description
Pin
4
IO_L165N_YY
AE19
5
IO_L179N
AF15
4
IO_VREF_4_L166P_YY
AK22
5
IO_L180P_YY
AA15
4
IO_L166N_YY
AH20
5
IO_VREF_5_L180N_YY
AF14
4
IO_L167P
AG19
5
IO_L181P_YY
AH15
4
IO_L167N
AB17
5
IO_L181N_YY
AK15
4
IO_L168P
AJ19
5
IO_L182P
AB14
4
IO_L168N
AD17
5
IO_L182N
AF13
4
IO_L169P_YY
AA16
5
IO_L183P
AH14
4
IO_L169N_YY
AA17
5
IO_L183N
AJ14
4
IO_VREF_4_L170P_YY
AK21
5
IO_L184P_YY
AE14
4
IO_L170N_YY
AB16
5
IO_VREF_5_L184N_YY
AG13
4
IO_L171P
AG18
5
IO_L185P_YY
AK13
4
IO_L171N
AK20
5
IO_L185N_YY
AD13
4
IO_L172P
AK19
5
IO_L186P
AE13
4
IO_L172N
AD16
5
IO_L186N
AF12
4
IO_L173P_YY
AE16
5
IO_L187P
AC13
4
IO_L173N_YY
AE17
5
IO_L187N
AA13
4
IO_VREF_4_L174P_YY
AG17
5
IO_L188P_YY
AA12
4
IO_L174N_YY
AJ17
5
IO_VREF_5_L188N_YY
AJ12
4
IO_L176P
AG16
5
IO_L189P_YY
AB12
4
IO_L176N
AK17
5
IO_L189N_YY
AE11
4
IO_LVDS_DLL_L177P
AF16
5
IO_L191P_Y
AG11
5
IO_L191N_Y
AF11
5
GCK1
AK16
5
IO_L192P_Y
AH11
5
IO
AD8
5
IO_L192N_Y
AJ11
5
IO
AD14
5
IO_L194P_YY
AD12
5
IO
AE10
5
IO_L194N_YY
AK11
5
IO
AE12
5
IO_L195P_YY
AJ10
5
IO
AG15
5
IO_VREF_5_L195N_YY
AC12
5
IO
AH5
5
IO_L196P
AK10
5
IO
AH8
5
IO_L196N
AD11
5
IO
AK12
5
IO_L197P
AJ9
5
IO_LVDS_DLL_L177N
AH16
5
IO_L197N
AE9
5
IO_L179P
AB15
5
IO_L198P_YY
AH10
DS025-4 (v1.6) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 4 of 4
31
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Bank
Description
Pin
Bank
Description
Pin
5
IO_VREF_5_L198N_YY
AF9
6
IO
AD6
5
IO_L199P_YY
AH9
6
IO
AG2
5
IO_L199N_YY
AK9
6
IO_L212N_YY
AF3
5
IO_L200P
AF8
6
IO_L212P_YY
AC6
5
IO_L200N
AB11
6
IO_L214N_Y
AB9
5
IO_L201P
AC11
6
IO_L214P_Y
AE4
5
IO_L201N
AG8
6
IO_L215N
AE3
5
IO_L202P_YY
AK8
6
IO_L215P
AH1
5
IO_VREF_5_L202N_YY
AF7
6
IO_L217N
AG1
5
IO_L203P_YY
AG7
6
IO_L217P
AA10
5
IO_L203N_YY
AK7
6
IO_VREF_L218N_Y
AA9
5
IO_L204P
AJ7
6
IO_L218P_Y
AD4
5
IO_L204N
AD10
6
IO_L219N_YY
AD5
5
IO_L205P
AH6
6
IO_L219P_YY
AD2
5
IO_L205N
AC10
6
IO_L220N
AD3
5
IO_L206P_YY
AD9
6
IO_L220P
AF2
5
IO_VREF_5_L206N_YY
AG6
6
IO_L221N
AA8
5
IO_L207P_YY
AB10
6
IO_L221P
AA7
5
IO_L207N_YY
AJ5
6
IO_VREF_L222N_YY
AF1
5
IO_L209P_Y
AC9
6
IO_L222P_YY
Y9
5
IO_L209N_Y
AJ4
6
IO_L223N_YY
AB6
5
IO_L210P_Y
AG5
6
IO_L223P_YY
AC4
5
IO_L210N_Y
AK4
6
IO_L224N_Y
AE1
6
IO_L224P_Y
W8
6
IO
T6
6
IO_L225N
Y8
6
IO
U1
6
IO_L225P
AB4
6
IO
U6
6
IO_VREF_L226N
AB3
6
IO
V7
6
IO_L226P
W9
6
IO
V8
6
IO_L228N
AB1
6
IO
W10
6
IO_L228P
V10
6
IO
Y10
6
IO_VREF
AC1
6
IO
AA2
6
IO_L230N
V11
6
IO
AA4
6
IO_L230P
AA3
6
IO
AD1
6
IO_L232N_Y
W7
Module 4 of 4
32
www.xilinx.com
1-800-255-7778
DS025-4 (v1.6) July 17, 2002
R
Table 5:
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
FG900 Fine-Pitch BGA Package — XCV812E
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Bank
Description
Pin
Bank
Description
Pin
6
IO_L232P_Y
AA6
7
IO
N8
6
IO_L233N
Y6
7
IO
R5
6
IO_L233P
Y4
7
IO_L247P
R10
6
IO_L235N
Y3
7
IO_L249N
R8
6
IO_L235P
Y2
7
IO_L249P
R4
6
IO_VREF_L236N_Y
Y5
7
IO_L250N
R7
6
IO_L236P_Y
W5
7
IO_L250P
R3
6
IO_L237N_YY
W4
7
IO_L251N
P10
6
IO_L237P_YY
W6
7
IO_VREF_L251P
P6
6
IO_L238N
V6
7
IO_L252N
P5
6
IO_L238P
W2
7
IO_L252P
P2
6
IO_L239N
U9
7
IO_L253N_Y
P7
6
IO_L239P
V4
7
IO_L253P_Y
P4
6
IO_VREF_L240N_YY
AB2
7
IO_L254N_YY
N4
6
IO_L240P_YY
T8
7
IO_L254P_YY
R2
6
IO_L241N_YY
U5
7
IO_L255N_YY
N7
6
IO_L241P_YY
W1
7
IO_VREF_L255P_YY
P1
6
IO_L242N_Y
Y1
7
IO_L256N
M6
6
IO_L242P_Y
T9
7
IO_L256P
N6
6
IO_L243N
T7
7
IO_L257N
N5
6
IO_L243P
U3
7
IO_L257P
N1
6
IO_VREF_L244N
T5
7
IO_L258N_YY
M4
6
IO_L244P
V2
7
IO_L258P_YY
M5
6
IO_L246N
T4
7
IO_L259N_Y
M2
6
IO_L246P
U2
7
IO_VREF_L259P_Y
M1
6
IO_L247N
T1
7
IO_L260N
L4
7
IO_L260P
L2
7
IO
D1
7
IO_L262N
L1
7
IO
E3
7
IO_L262P
M8
7
IO
J4
7
IO_L263N_Y
K2
7
IO
J6
7
IO_L263P_Y
M9
7
IO
K10
7
IO_L265N_YY
K5
7
IO
L3
7
IO_L265P_YY
K1
7
IO
M7
7
IO_L266N_YY
L6
DS025-4 (v1.6) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 4 of 4
33
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Bank
Description
Pin
Bank
Description
Pin
7
IO_VREF_L266P_YY
K3
NA
M0
AF4
7
IO_L267N
L7
NA
M1
AC7
7
IO_L267P
K4
NA
M2
AK3
7
IO_L268N
L8
NA
PROGRAM
AG28
7
IO_L268P
J5
NA
TCK
B3
7
IO_L269N
K6
NA
TDI
H22
7
IO_VREF_L269P
H4
2
TDO
D26
7
IO_L270N
H1
NA
TMS
C1
7
IO_L270P
K7
7
IO_L271N_Y
J7
NA
VCCINT
L11
7
IO_L271P_Y
J2
NA
VCCINT
L12
7
IO_L272N_YY
H5
NA
VCCINT
L19
7
IO_L272P_YY
G2
NA
VCCINT
L20
7
IO_L273N_YY
L9
NA
VCCINT
M11
7
IO_VREF_L273P_YY
G5
NA
VCCINT
M12
7
IO_L274N
F3
NA
VCCINT
M19
7
IO_L274P
K8
NA
VCCINT
M20
7
IO_L275N
G3
NA
VCCINT
N13
7
IO_L275P
E1
NA
VCCINT
N14
7
IO_L276N_YY
H6
NA
VCCINT
N15
7
IO_L276P_YY
E2
NA
VCCINT
N16
7
IO_L277N_Y
E4
NA
VCCINT
N17
7
IO_VREF_L277P_Y
K9
NA
VCCINT
N18
7
IO_L278N
J8
NA
VCCINT
P13
7
IO_L278P
F4
NA
VCCINT
P18
7
IO_L280N
G6
NA
VCCINT
R13
7
IO_L280P
C2
NA
VCCINT
R18
7
IO_L281N_Y
D2
NA
VCCINT
T13
7
IO_L281P_Y
F5
NA
VCCINT
T18
NA
VCCINT
U18
2
DONE
AJ28
NA
VCCINT
U13
NA
DXN
AJ3
NA
VCCINT
V13
NA
DXP
AH4
NA
VCCINT
V14
3
CCLK
F26
NA
VCCINT
V15
Module 4 of 4
34
www.xilinx.com
1-800-255-7778
DS025-4 (v1.6) July 17, 2002
R
Table 5:
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
FG900 Fine-Pitch BGA Package — XCV812E
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Bank
Description
Pin
Bank
Description
Pin
NA
VCCINT
V16
NA
VCCO_2
N19
NA
VCCINT
V17
NA
VCCO_2
P19
NA
VCCINT
V18
NA
VCCO_3
AE29
NA
VCCINT
W11
NA
VCCO_3
W28
NA
VCCINT
W12
NA
VCCO_3
U23
NA
VCCINT
W19
NA
VCCO_3
U20
NA
VCCINT
W20
NA
VCCO_3
T20
NA
VCCINT
Y11
NA
VCCO_3
V19
NA
VCCINT
Y12
NA
VCCO_3
T19
NA
VCCINT
Y19
NA
VCCO_3
U19
NA
VCCINT
Y20
NA
VCCO_4
AJ25
NA
VCCO_4
AH19
NA
VCCO_0
B6
NA
VCCO_4
W18
NA
VCCO_0
M15
NA
VCCO_4
AC17
NA
VCCO_0
M14
NA
VCCO_4
Y17
NA
VCCO_0
L15
NA
VCCO_4
W17
NA
VCCO_0
L14
NA
VCCO_4
W16
NA
VCCO_0
H14
NA
VCCO_4
Y16
NA
VCCO_0
M13
NA
VCCO_5
AJ6
NA
VCCO_0
C12
NA
VCCO_5
Y15
NA
VCCO_1
B25
NA
VCCO_5
W15
NA
VCCO_1
C19
NA
VCCO_5
AC14
NA
VCCO_1
M18
NA
VCCO_5
Y14
NA
VCCO_1
M17
NA
VCCO_5
W14
NA
VCCO_1
L17
NA
VCCO_5
W13
NA
VCCO_1
H17
NA
VCCO_5
AH12
NA
VCCO_1
L16
NA
VCCO_6
AE2
NA
VCCO_1
M16
NA
VCCO_6
V12
NA
VCCO_2
F29
NA
VCCO_6
U12
NA
VCCO_2
M28
NA
VCCO_6
T12
NA
VCCO_2
P23
NA
VCCO_6
U11
NA
VCCO_2
R20
NA
VCCO_6
T11
NA
VCCO_2
P20
NA
VCCO_6
U8
NA
VCCO_2
R19
NA
VCCO_6
W3
DS025-4 (v1.6) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 4 of 4
35
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Bank
Description
Pin
Bank
Description
Pin
NA
VCCO_7
F2
NA
GND
H23
NA
VCCO_7
R12
NA
GND
B23
NA
VCCO_7
P12
NA
GND
AC23
NA
VCCO_7
N12
NA
GND
AB22
NA
VCCO_7
R11
NA
GND
V22
NA
VCCO_7
P11
NA
GND
N22
NA
VCCO_7
P8
NA
GND
AH18
NA
VCCO_7
M3
NA
GND
AB18
NA
GND
J18
NA
GND
Y18
NA
GND
C18
NA
GND
AH7
NA
GND
U17
NA
GND
AK30
NA
GND
T17
NA
GND
AJ30
NA
GND
R17
NA
GND
B30
NA
GND
P17
NA
GND
A30
NA
GND
U16
NA
GND
AK29
NA
GND
T16
NA
GND
AJ29
NA
GND
R16
NA
GND
AC29
NA
GND
P16
NA
GND
H29
NA
GND
U15
NA
GND
B29
NA
GND
T15
NA
GND
A29
NA
GND
R15
NA
GND
AH28
NA
GND
P15
NA
GND
V28
NA
GND
U14
NA
GND
N28
NA
GND
T14
NA
GND
C28
NA
GND
R14
NA
GND
AG27
NA
GND
P14
NA
GND
D27
NA
GND
AH13
NA
GND
AF26
NA
GND
AB13
NA
GND
E26
NA
GND
J13
NA
GND
F25
NA
GND
C13
NA
GND
AE25
NA
GND
V9
NA
GND
G24
NA
GND
N9
NA
GND
AJ23
NA
GND
J9
NA
GND
AD24
NA
GND
AJ8
Module 4 of 4
36
www.xilinx.com
1-800-255-7778
DS025-4 (v1.6) July 17, 2002
R
Table 5:
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
FG900 Fine-Pitch BGA Package — XCV812E
FG900 Differential Pin Pairs
Bank
Description
Pin
NA
GND
AC8
NA
GND
H8
NA
GND
AD7
NA
GND
B8
NA
GND
AE6
NA
GND
G7
NA
GND
F6
NA
GND
AF5
Pairs with a note number in the AO column are device
dependent. They can have asynchronous outputs if the pin
pair is in the same CLB row and column in the device. Numbers in this column refer to footnotes that indicate which
devices have pin pairs that can be asynchronous outputs.
The Other Functions column indicates alternative function(s) not available when the pair is used as a differential
pair or differential clock.
NA
GND
E5
Table 6:
NA
GND
AG4
NA
GND
D4
NA
GND
V3
NA
GND
N3
3
0
C15
A15
NA
IO LVDS 34
NA
GND
C3
2
1
E15
E16
NA
IO LVDS 34
NA
GND
AK2
1
5
AK16
AH16
NA
IO LVDS 177
NA
GND
AH3
0
4
AJ16
AF16
NA
IO LVDS 177
NA
GND
AC2
NA
GND
H2
1
0
G8
D5
√
-
NA
GND
B2
2
0
H9
A3
√
-
NA
GND
A2
4
0
D6
A4
√
-
NA
GND
AK1
5
0
B5
E7
√
VREF
NA
GND
AJ2
6
0
F8
A5
-
-
NA
GND
AJ1
7
0
N11
D7
-
-
8
0
E8
G9
GND
A1
√
-
NA
9
0
J11
A6
√
VREF
NA
GND
B1
10
0
B7
C7
-
-
11
0
H10
C8
-
-
12
0
F10
G10
√
-
13
0
H11
A8
√
VREF
15
0
J12
B9
-
-
17
0
B10
G11
-
-
19
0
F11
H13
√
-
20
0
D11
E11
√
-
22
0
C11
F12
√
-
23
0
D12
A10
√
VREF
24
0
A11
E12
-
-
DS025-4 (v1.6) July 17, 2002
Virtex-E Extended Memory devices have differential pin
pairs that can also provide other functions when not used as
a differential pair. A √ in the AO column indicates that the pin
pair can be used as an asynchronous output for all devices
provided in this package.
Pair
FG900 Differential Pin Pair Summary —
XCV812E
Bank
P
N
Pin
Pin
Other
AO
Functions
GCLK LVDS
IO LVDS
Total Pairs: 235, Asynchronous Output Pairs: 85
www.xilinx.com
1-800-255-7778
Module 4 of 4
37
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 6:
FG900 Differential Pin Pair Summary —
XCV812E
P
N
Table 6:
FG900 Differential Pin Pair Summary —
XCV812E
Other
P
N
Other
Pair
Bank
Pin
Pin
AO
Functions
Pair
Bank
Pin
Pin
AO
Functions
25
0
B12
G13
-
-
67
1
F24
A27
√
-
26
0
K13
A12
√
-
69
1
C27
K21
√
CS
27
0
B13
F13
√
VREF
70
2
J22
E27
√
DIN_D0
28
0
E13
G14
-
-
72
2
G25
E25
√
-
29
0
B14
D14
-
-
73
2
E28
C30
-
-
30
0
J14
A14
√
-
75
2
D30
J23
-
-
31
0
J15
K14
√
VREF
76
2
L21
F28
√
VREF
34
1
E16
A15
-
GCLK LVDS 3/2
77
2
G28
E30
√
-
35
1
F16
B16
-
-
78
2
G27
E29
-
-
36
1
H16
A16
-
-
79
2
K23
H26
-
-
37
1
K15
C16
√
VREF
80
2
F30
L22
√
VREF
38
1
G16
K16
√
-
81
2
H27
G29
√
-
39
1
E17
A17
-
-
82
2
G30
M21
√
-
40
1
C17
F17
-
-
83
2
J24
J26
-
-
41
1
A18
E18
√
VREF
84
2
H30
L23
-
VREF
42
1
A19
D18
√
-
86
2
J29
K24
-
-
43
1
G18
B19
-
-
88
2
M22
K29
-
D2
44
1
H18
D19
-
-
90
2
N21
K25
√
-
45
1
F19
F18
√
VREF
91
2
L24
L27
-
-
46
1
K17
B20
√
-
93
2
L26
L28
-
-
48
1
C20
G19
√
-
94
2
L30
M27
√
VREF
49
1
E20
K18
√
-
95
2
M26
M29
√
-
51
1
A21
F20
√
-
96
2
N29
M30
-
-
52
1
A22
C21
√
VREF
97
2
N25
N27
-
-
53
1
B22
H19
-
-
98
2
N30
P21
√
D3
54
1
D22
E21
-
-
99
2
N26
P28
√
-
55
1
C22
F21
√
VREF
100
2
P29
N24
√
-
56
1
E22
H20
√
-
101
2
P22
R26
-
-
57
1
A23
G21
-
-
102
2
P25
R29
-
VREF
58
1
K19
A24
-
-
104
2
R25
T30
-
-
59
1
B24
C24
√
VREF
106
3
R24
U29
-
TRDY
60
1
G22
H21
√
-
107
3
R22
T27
-
-
61
1
C25
E23
-
-
108
3
R23
T28
-
-
62
1
A26
D24
-
-
109
3
T21
T25
-
VREF
63
1
K20
B26
√
VREF
110
3
U28
U30
-
-
64
1
J21
D25
√
-
111
3
T23
U27
√
-
66
1
G23
B27
√
-
112
3
U25
V27
√
-
Module 4 of 4
38
www.xilinx.com
1-800-255-7778
DS025-4 (v1.6) July 17, 2002
R
Table 6:
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
FG900 Differential Pin Pair Summary —
XCV812E
P
N
Table 6:
FG900 Differential Pin Pair Summary —
XCV812E
Other
P
N
Other
Pair
Bank
Pin
Pin
AO
Functions
Pair
Bank
Pin
Pin
AO
Functions
113
3
U24
V29
√
VREF
156
4
AJ22
AG22
√
VREF
114
3
W30
U22
-
-
158
4
AA19
AF21
-
-
115
3
U21
W29
-
-
160
4
AG21
AK23
-
-
116
3
V26
W27
√
-
162
4
AE20
AJ21
√
-
117
3
W26
Y29
√
VREF
163
4
AG20
AF20
√
-
118
3
W25
Y30
-
-
165
4
AJ20
AE19
√
-
120
3
AA30
W24
-
-
166
4
AK22
AH20
√
VREF
121
3
AA29
V20
√
-
167
4
AG19
AB17
-
-
123
3
Y26
AB30
√
D5
168
4
AJ19
AD17
-
-
124
3
V21
AA28
√
VREF
169
4
AA16
AA17
√
-
125
3
Y25
AA27
-
-
170
4
AK21
AB16
√
VREF
126
3
W22
Y23
-
-
171
4
AG18
AK20
-
-
127
3
Y24
AB28
-
VREF
172
4
AK19
AD16
-
-
128
3
AC30
AA25
-
-
173
4
AE16
AE17
√
-
129
3
W21
AA24
√
-
174
4
AG17
AJ17
√
VREF
130
3
AB26
AD30
√
-
176
4
AG16
AK17
-
-
131
3
Y22
AC27
√
VREF
177
5
AF16
AH16
-
GCLK LVDS 1/0
132
3
AD28
AB25
-
-
179
5
AB15
AF15
-
-
133
3
AC26
AE30
-
-
180
5
AA15
AF14
√
VREF
134
3
AD27
AF30
√
-
181
5
AH15
AK15
√
-
135
3
AF29
AB24
√
VREF
182
5
AB14
AF13
-
-
136
3
AB23
AE28
-
-
183
5
AH14
AJ14
-
-
138
3
AE26
AG29
-
-
184
5
AE14
AG13
√
VREF
139
3
AH30
AC24
√
-
185
5
AK13
AD13
√
-
141
3
AH29
AA22
√
INIT
186
5
AE13
AF12
-
-
142
4
AF27
AK28
√
-
187
5
AC13
AA13
-
-
144
4
AD23
AJ27
√
-
188
5
AA12
AJ12
√
VREF
145
4
AB21
AF25
√
-
189
5
AB12
AE11
√
-
147
4
AA21
AG25
√
-
191
5
AG11
AF11
√
-
148
4
AJ26
AD22
√
VREF
192
5
AH11
AJ11
√
-
149
4
AA20
AH25
-
-
194
5
AD12
AK11
√
-
150
4
AC21
AF24
-
-
195
5
AJ10
AC12
√
VREF
151
4
AG24
AK26
√
-
196
5
AK10
AD11
-
-
152
4
AJ24
AF23
√
VREF
197
5
AJ9
AE9
-
-
153
4
AE23
AB20
-
-
198
5
AH10
AF9
√
VREF
154
4
AC20
AG23
-
-
199
5
AH9
AK9
√
-
155
4
AF22
AE22
√
-
200
5
AF8
AB11
-
-
DS025-4 (v1.6) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 4 of 4
39
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 6:
FG900 Differential Pin Pair Summary —
XCV812E
P
N
Table 6:
FG900 Differential Pin Pair Summary —
XCV812E
Other
P
N
Other
Pair
Bank
Pin
Pin
AO
Functions
Pair
Bank
Pin
Pin
AO
Functions
201
5
AC11
AG8
-
-
247
7
R10
T1
-
IRDY
202
5
AK8
AF7
√
VREF
249
7
R4
R8
-
-
203
5
AG7
AK7
√
-
250
7
R3
R7
-
-
204
5
AJ7
AD10
-
-
251
7
P6
P10
-
VREF
205
5
AH6
AC10
-
-
252
7
P2
P5
-
-
206
5
AD9
AG6
√
VREF
253
7
P4
P7
√
-
207
5
AB10
AJ5
√
-
254
7
R2
N4
√
-
209
5
AC9
AJ4
√
-
255
7
P1
N7
√
VREF
210
5
AG5
AK4
√
-
256
7
N6
M6
-
-
212
6
AC6
AF3
√
-
257
7
N1
N5
-
-
214
6
AE4
AB9
√
-
258
7
M5
M4
√
-
215
6
AH1
AE3
-
-
259
7
M1
M2
√
VREF
217
6
AA10
AG1
-
-
260
7
L2
L4
-
-
218
6
AD4
AA9
√
VREF
262
7
M8
L1
-
-
219
6
AD2
AD5
√
-
263
7
M9
K2
√
-
220
6
AF2
AD3
-
-
265
7
K1
K5
√
-
221
6
AA7
AA8
-
-
266
7
K3
L6
√
VREF
222
6
Y9
AF1
√
VREF
267
7
K4
L7
-
-
223
6
AC4
AB6
√
-
268
7
J5
L8
-
-
224
6
W8
AE1
√
-
269
7
H4
K6
-
VREF
225
6
AB4
Y8
-
-
270
7
K7
H1
-
-
226
6
W9
AB3
-
VREF
271
7
J2
J7
√
-
228
6
V10
AB1
-
-
272
7
G2
H5
√
-
230
6
AA3
V11
-
-
273
7
G5
L9
√
VREF
232
6
AA6
W7
√
-
274
7
K8
F3
-
-
233
6
Y4
Y6
-
-
275
7
E1
G3
-
-
235
6
Y2
Y3
-
-
276
7
E2
H6
√
-
236
6
W5
Y5
√
VREF
277
7
K9
E4
√
VREF
237
6
W6
W4
√
-
278
7
F4
J8
-
-
238
6
W2
V6
-
-
280
7
C2
G6
-
-
239
6
V4
U9
-
-
281
7
F5
D2
-
-
240
6
T8
AB2
√
VREF
241
6
W1
U5
√
-
242
6
T9
Y1
√
-
243
6
U3
T7
-
-
244
6
V2
T5
-
VREF
246
6
U2
T4
-
-
Module 4 of 4
40
www.xilinx.com
1-800-255-7778
DS025-4 (v1.6) July 17, 2002
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Virtex-E Extended Memory Device/Package Combinations and Maximum I/O
Virtex-E Extended Memory Series Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins)
Package
XCV405E
XCV812E
BG560
404
404
FG676
404
FG900
556
Virtex-E Ordering Information
Virtex-II ordering information is shown in Figure 1
Example: XCV405E-6BG560C
Device Type
Speed Grade
(-6, -7, -8)
Temperature Range
C = Commercial (TJ = 0˚C to +85˚C)
I = Industrial (TJ = −40˚C to +100˚C)
Number of Pins
Package Type
BG = Ball Grid Array
FG = Fine Pitch Ball Grid Array
DS025_001_112000
Figure 1: Virtex Ordering Information
DS025-4 (v1.6) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 4 of 4
41
R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Revision History
The following table shows the revision history for this document.
Date
Version
03/23/00
1.0
Initial Xilinx release.
08/01/00
1.1
Accumulated edits and fixes. Upgrade to Preliminary. Preview -8 numbers added. Reformatted
to adhere to corporate documentation style guidelines. Minor changes in BG560 pin-out table.
09/19/00
1.2
11/20/00
1.3
Revision
•
•
•
•
•
•
•
07/23/01
1.5
•
In Table 4, FG676 Fine-Pitch BGA — XCV405E, pin B19 is no longer labeled as VREF, and
pin G16 is now labeled as VREF.
Updated values in Virtex-E Switching Characteristics tables.
Converted data sheet to modularized format. See the Virtex-E Extended Memory Data
Sheet section.
Changed definition of T31 and T32 pins in Table 1 for XCV405E and the XCV812E devices.
07/17/02
1.6
•
Data sheet designation upgraded from Preliminary to Production.
04/02/01
1.4
•
In Table 3 (Module 4), FG676 Fine-Pitch BGA — XCV405E, the following pins are no longer
labeled as VREF: B7, G16, G26, W26, AF20, AF8, Y1, H1.
Min values added to Virtex-E Electrical Characteristics tables.
Updated speed grade -8 numbers in Virtex-E Electrical Characteristics tables (Module 3).
Updated minimums in Table 11 (Module 2), and added notes to Table 12 (Module 2).
Added to note 2 of Absolute Maximum Ratings (Module 3).
Changed all minimum hold times to –0.4 for Global Clock Set-Up and Hold for LVTTL
Standard, with DLL (Module 3).
Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters (Module 3).
•
•
Virtex-E Extended Memory Data Sheet
The Virtex-E Extended Memory Data Sheet contains the following modules:
•
DS025-1, Virtex-E 1.8V Extended Memory FPGAs:
•
Introduction and Ordering Information (Module 1)
•
DS025-2, Virtex-E 1.8V Extended Memory FPGAs:
Functional Description (Module 2)
Module 4 of 4
42
DS025-3, Virtex-E 1.8V Extended Memory FPGAs:
DC and Switching Characteristics (Module 3)
•
DS025-4, Virtex-E 1.8V Extended Memory FPGAs:
Pinout Tables (Module 4)
www.xilinx.com
1-800-255-7778
DS025-4 (v1.6) July 17, 2002