0 Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics R DS077-3 (v2.0) November 18, 2002 0 0 Product Specification Definition of Terms In this document, some specifications may be designated as Advance or Preliminary. These designations are based on the more detailed timing information used by the development system and reported in the output files. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families. Values are subject to change. Use as estimates, not for production. Preliminary: Based on characterization. Further changes are not expected. Except for pin-to-pin input and output parameters, the AC parameter delay specifications included in this document are derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters included are common to popular designs and typical applications. All specifications are subject to change without notice. DC Specifications Absolute Maximum Ratings (1) Symbol Description Min Max Units VCCINT Supply voltage relative to GND –0.5 2.0 V VCCO Supply voltage relative to GND –0.5 4.0 V VREF Input reference voltage –0.5 4.0 V –0.5 4.0 V GND (2,3) VIN Input voltage relative to VTS Voltage applied to 3-state output(3) –0.5 4.0 V TSTG Storage temperature (ambient) –65 +150 °C - +125 °C TJ Junction temperature Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 2. VIN should not exceed VCCO by more than 3.6V over extended periods of time (e.g., longer than a day). 3. Maximum DC overshoot must be limited to either VCCO + 0.5V or 10 mA, and undershoot must be limited to –0.5V or 10 mA, whichever is easier to achieve. The Maximum AC conditions are as follows: The device pins may undershoot to –2.0V or overshoot to VCCO + 2.0V, provided this over/undershoot lasts no more than 11 ns with a forcing current no greater than 100 mA. 4. For soldering guidelines, see the Packaging Information on the Xilinx website. © 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS077-3 (v2.0) November 18, 2002 Product Specification www.xilinx.com 1-800-255-7778 1 R Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics Recommended Operating Conditions Symbol TJ Description Junction temperature Min VCCINT VCCO TIN Supply voltage relative to Supply voltage relative to GND (2) Input signal transition Units 0 85 °C –40 100 °C Commercial 1.8 – 5% 1.8 + 5% V Industrial 1.8 – 5% 1.8 + 5% V Commercial 1.2 3.6 V Industrial 1.2 3.6 V - 250 ns Commercial Industrial GND (1) Max time (3) Notes: 1. Functional operation is guaranteed down to a minimum V CCINT of 1.62V (Nominal V CCINT –10%). For every 50 mV reduction in VCCINT below 1.71V (nominal VCCINT –5%), all delay parameters increase by 3%. 2. Minimum and maximum values for VCCO vary according to the I/O standard selected. 3. Input and output measurement threshold is ~50% of VCCO. DC Characteristics Over Operating Conditions Symbol Description Min Typ Max Units VDRINT Data retention VCCINT voltage (below which configuration data may be lost) 1.5 - - V VDRIO Data retention VCCO voltage (below which configuration data may be lost) 1.2 - - V - - 200 mA ICCINTQ Quiescent VCCINT supply current (1) XC2S50E XC2S100E XC2S150E XC2S200E XC2S300E XC2S400E XC2S600E Commercial Industrial - - 200 mA Commercial - - 200 mA Industrial - - 200 mA Commercial - - 300 mA Industrial - - 300 mA Commercial - - 300 mA Industrial - - 300 mA Commercial - - 300 mA Industrial - - 300 mA Commercial - - 300 mA Industrial - - 300 mA Commercial - - 400 mA Industrial ICCOQ IREF IL - - 400 mA Quiescent VCCO supply current (1) - - 2 mA VREF current per VREF pin - - 20 µA –10 - +10 µA Input or output leakage current(2) CIN Input capacitance (sample tested) - - 8 pF IRPU Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V (sample tested) (3) TQ, PQ, FG, FT packages - - 0.25 mA IRPD Pad pull-down (when selected) @ VIN = 3.6V (sample tested) (3) - - 0.25 mA Notes: 1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating. 2. The I/O leakage current specification applies only when the VCCINT and VCCO supply voltages have reached their respective minimum Recommended Operating Conditions. 3. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors do not provide valid logic levels when input pins are connected to other circuits. 2 www.xilinx.com 1-800-255-7778 DS077-3 (v2.0) November 18, 2002 Product Specification R Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics Power-On Requirements A maximum limit for ICCPO is not specified. Be careful when using foldback/crowbar supplies and fuses. It is possible to control the magnitude of ICCPO by limiting the supply current available to the FPGA. A current limit below the trip level will avoid inadvertently activating over-current protection circuits. Spartan-IIE FPGAs require that a minimum supply current ICCPO be provided to the VCCINT lines for a successful power-on. If more current is available, the FPGA can consume more than ICCPO min., though this cannot adversely affect reliability. Symbol I CCPO TCCPO Description Total VCCINT supply current required during power-on VCCINT (2,3) Commercial Industrial ramp time Min(1) Max Units 500 - mA 2 - A 2 50 ms Notes: 1. The ICCPO requirement applies for a brief time (commonly only a few milliseconds) when VCCINT ramps from 0 to 1.8V. 2. The ramp time is measured from GND to 1.8V on a fully loaded board. 3. VCCINT must not dip in the negative direction during power on. 4. Power-on current is measured with VCCINT and VCCO powering up simultaneously. 5. I/Os are not guaranteed to be disabled until VCCINT is applied. 6. For more information on designing to meet the power-on specifications, refer to the application note XAPP450 "Power-On Current Requirements for the Spartan-II and Spartan-IIE Families". DC Input and Output Levels Values for VIL and VIH are recommended input voltages. Values for VOL and VOH are guaranteed output voltages over the recommended operating conditions. Only selected standards are tested. These are chosen to ensure that all Input/Output Standard VIL standards meet their specifications. The selected standards are tested at minimum VCCO with the respective IOL and IOH currents shown. Other standards are sample tested. VIH VOL VOH IOL IOH V, Min V, Max V, Min V, Max V, Max V, Min mA mA LVTTL(1) –0.5 0.8 2.0 3.6 0.4 2.4 24 –24 LVCMOS2 –0.5 0.7 1.7 2.7 0.4 1.9 12 –12 LVCMOS18 –0.5 35% VCCO 1.95 0.4 VCCO – 0.4 8 –8 PCI, 3.3V –0.5 30% VCCO 65% VCCO 50% VCCO VCCO + 0.5 Note (2) –0.5 VREF – 0.05 VREF + 0.05 3.6 90% VCCO - Note (2) GTL 10% VCCO 0.4 40 - GTL+ –0.5 VREF – 0.1 VREF + 0.1 3.6 0.6 - 36 - HSTL I –0.5 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCO – 0.4 8 –8 HSTL III –0.5 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCO – 0.4 24 –8 HSTL IV –0.5 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCO – 0.4 48 –8 SSTL3 I –0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.6 VREF + 0.6 8 –8 SSTL3 II –0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.8 VREF + 0.8 16 –16 SSTL2 I –0.5 VREF – 0.2 VREF + 0.2 3.6 7.6 –7.6 SSTL2 II –0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.61 VREF + 0.61 VREF – 0.8 VREF + 0.8 15.2 –15.2 CTT –0.5 VREF – 0.2 VREF + 0.2 3.6 VREF – 0.4 VREF + 0.4 8 –8 AGP –0.5 VREF – 0.2 VREF + 0.2 3.6 10% VCCO 90% VCCO Note (2) Note (2) Notes: 1. VOL and VOH for lower drive currents are sample tested. 2. Tested according to the relevant specifications. DS077-3 (v2.0) November 18, 2002 Product Specification www.xilinx.com 1-800-255-7778 3 R Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics LVDS DC Specifications Symbol VCCO Description Conditions Supply voltage Min Typ Max Units 2.375 2.5 2.625 V VOH Output High voltage for Q and Q RT = 100Ω across Q and Q signals 1.25 1.425 1.6 V VOL Output Low voltage for Q and Q RT = 100Ω across Q and Q signals 0.9 1.075 1.25 V VODIFF Differential output voltage (Q – Q), Q = High or (Q – Q), Q = High RT = 100Ω across Q and Q signals 250 350 450 mV VOCM Output common-mode voltage RT = 100Ω across Q and Q signals 1.125 1.25 1.375 V VIDIFF Differential input voltage (Q – Q), Q = High or (Q – Q), Q = High Common-mode input voltage = 1.25 V 100 350 - mV VICM Input common-mode voltage Differential input voltage = ±350 mV 0.2 1.25 2.2 V Notes: 1. Refer to Application Note XAPP179 for termination schematics. LVPECL DC Specifications These values are valid at the output of the source termination pack shown under LVPECL, with a 100Ω differential load only. The VOH levels are 200 mV below standard DC Parameter Min Max Min 3.0 VCCO 4 LVPECL levels and are compatible with devices tolerant of lower common-mode ranges. The following table summarizes the DC output specifications of LVPECL. Max Min 3.3 Max 3.6 Units V VOH 1.8 2.11 1.92 2.28 2.13 2.41 V VOL 0.96 1.27 1.06 1.43 1.30 1.57 V VIH 1.49 2.72 1.49 2.72 1.49 2.72 V VIL 0.86 2.125 0.86 2.125 0.86 2.125 V Differential input voltage 0.3 - 0.3 - 0.3 - V www.xilinx.com 1-800-255-7778 DS077-3 (v2.0) November 18, 2002 Product Specification R Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics Switching Characteristics Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRACE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Spartan-IIE devices unless otherwise noted. Global Clock Input to Output Delay for LVTTL, with DLL (Pin-to-Pin)(1) Speed Grade All -7 -6 Symbol Description Min Max Max Units TICKOFDLL LVTTL global clock input to output delay using output flip-flop for LVTTL, 12 mA, fast slew rate, with DLL. 1.0 3.1 3.1 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values. For other I/O standards and different loads, see the tables Constants for Calculating TIOOP and Delay Measurement Methodology, page 11. 3. DLL output jitter is already included in the timing calculation. 4. For data output with different standards, adjust delays with the values shown in IOB Output Delay Adjustments for Different Standards(1), page 10. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard Global Clock Input Adjustments, page 12. Global Clock Input to Output Delay for LVTTL, without DLL (Pin-to-Pin)(1) Speed Grade All -7 -6 Symbol Description Device Min Max Max Units TICKOF LVTTL global clock input to output delay using output flip-flop for LVTTL, 12 mA, fast slew rate, without DLL. XC2S50E 1.5 4.4 4.6 ns XC2S100E 1.5 4.4 4.6 ns XC2S150E 1.5 4.5 4.7 ns XC2S200E 1.5 4.5 4.7 ns XC2S300E 1.5 4.5 4.7 ns XC2S400E 1.5 4.6 4.8 ns XC2S600E 1.6 4.7 4.9 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values. For other I/O standards and different loads, see the tables Constants for Calculating TIOOP and Delay Measurement Methodology, page 11. 3. For data output with different standards, adjust delays with the values shown in IOB Output Delay Adjustments for Different Standards(1), page 10. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard Global Clock Input Adjustments, page 12. DS077-3 (v2.0) November 18, 2002 Product Specification www.xilinx.com 1-800-255-7778 5 R Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics Global Clock Setup and Hold for LVTTL Standard, with DLL (Pin-to-Pin) Speed Grade -7 -6 Symbol Description Min Min Units TPSDLL / TPHDLL Input setup and hold time relative to global clock input signal for LVTTL standard, no delay, IFF,(1) with DLL 1.6 / 0 1.7 / 0 ns Notes: 1. IFF = Input Flip-Flop or Latch 2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 3. DLL output jitter is already included in the timing calculation. 4. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Delay Adjustments for Different Standards, page 8. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard Global Clock Input Adjustments, page 12. 5. A zero hold time listing indicates no hold time or a negative hold time. Global Clock Setup and Hold for LVTTL Standard, without DLL (Pin-to-Pin) Speed Grade -7 -6 Symbol Description Device Min Min Units TPSFD / TPHFD Input setup and hold time relative to global clock input signal for LVTTL standard, no delay, IFF,(1) without DLL XC2S50E 1.8 / 0 1.8 / 0 ns XC2S100E 1.8 / 0 1.8 / 0 ns XC2S150E 1.9 / 0 1.9 / 0 ns XC2S200E 1.9 / 0 1.9 / 0 ns XC2S300E 2.0 / 0 2.0 / 0 ns XC2S400E 2.0 / 0 2.0 / 0 ns XC2S600E 2.1 / 0 2.1 / 0 ns Notes: 1. IFF = Input Flip-Flop or Latch 2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. 3. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Delay Adjustments for Different Standards, page 8. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard Global Clock Input Adjustments, page 12. 6 www.xilinx.com 1-800-255-7778 DS077-3 (v2.0) November 18, 2002 Product Specification R Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics IOB Input Switching Characteristics (1) Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values shown in IOB Input Delay Adjustments for Different Standards, page 8. Speed Grade -7 Symbol Description -6 Device Min Max Min Max Units Propagation Delays TIOPI Pad to I output, no delay All 0.4 0.8 0.4 0.8 ns TIOPID Pad to I output, with delay All 0.5 1.0 0.5 1.0 ns TIOPLI Pad to output IQ via transparent latch, no delay All 0.7 1.5 0.7 1.6 ns TIOPLID Pad to output IQ via transparent latch, with delay XC2S50E 1.3 3.0 1.3 3.1 ns XC2S100E 1.3 3.0 1.3 3.1 ns XC2S150E 1.3 3.2 1.3 3.3 ns XC2S200E 1.3 3.2 1.3 3.3 ns XC2S300E 1.3 3.2 1.3 3.3 ns XC2S400E 1.4 3.2 1.4 3.4 ns XC2S600E 1.5 3.5 1.5 3.7 ns All 0.1 0.7 0.1 0.7 ns All 1.4 / 0 - 1.5 / 0 - ns XC2S50E 2.9 / 0 - 2.9 / 0 - ns XC2S100E 2.9 / 0 - 2.9 / 0 - ns XC2S150E 3.1 / 0 - 3.1 / 0 - ns XC2S200E 3.1 / 0 - 3.1 / 0 - ns XC2S300E 3.1 / 0 - 3.1 / 0 - ns XC2S400E 3.2 / 0 - 3.2 / 0 - ns XC2S600E 3.5 / 0 - 3.5 / 0 - ns All 0.7 / 0.01 - 0.7 / 0.01 - ns Sequential Delays TIOCKIQ Clock CLK to output IQ Setup/Hold Times with Respect to Clock CLK TIOPICK / TIOICKP Pad, no delay TIOPICKD / TIOICKPD Pad, with delay TIOICECK / TIOCKICE ICE input Set/Reset Delays TIOSRCKI SR input (IFF, synchronous) All 0.9 - 1.0 - ns TIOSRIQ SR input to IQ (asynchronous) All 0.5 1.2 0.5 1.4 ns TGSRQ GSR to output IQ All 3.8 8.5 3.8 9.7 ns Notes: 1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see the table Delay Measurement Methodology, page 11. DS077-3 (v2.0) November 18, 2002 Product Specification www.xilinx.com 1-800-255-7778 7 R Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics IOB Input Delay Adjustments for Different Standards Input delays associated with the pad are specified for LVTTL. For other standards, adjust the delays by the values shown. A delay adjusted in this way constitutes a worst-case limit. Speed Grade Symbol Description Standard -7 -6 Units LVTTL 0 0 ns LVCMOS2 0 0 ns LVCMOS18 0.20 0.20 ns LVDS 0.15 0.15 ns TILVPECL LVPECL 0.15 0.15 ns TIPCI33_3 PCI, 33 MHz, 3.3V 0.08 0.08 ns TIPCI66_3 PCI, 66 MHz, 3.3V –0.11 –0.11 ns TIGTL GTL 0.14 0.14 ns TIGTLP GTL+ 0.14 0.14 ns TIHSTL HSTL 0.04 0.04 ns TISSTL2 SSTL2 0.04 0.04 ns TISSTL3 SSTL3 0.04 0.04 ns TICTT CTT 0.10 0.10 ns TIAGP AGP 0.04 0.04 ns Data Input Delay Adjustments TILVTTL TILVCMOS2 TILVCMOS18 TILVDS 8 Standard-specific data input delay adjustments www.xilinx.com 1-800-255-7778 DS077-3 (v2.0) November 18, 2002 Product Specification R Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics IOB Output Switching Characteristics Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays with the values shown in IOB Output Delay Adjustments for Different Standards(1), page 10. Speed Grade -7 Symbol Description -6 Min Max Min Max Units Propagation Delays TIOOP O input to pad 1.0 2.7 1.0 2.9 ns TIOOLP O input to pad via transparent latch 1.2 3.1 1.2 3.4 ns TIOTHZ T input to pad high impedance (1) 0.7 1.7 0.7 1.9 ns TIOTON T input to valid data on pad 1.1 2.9 1.1 3.1 ns 0.8 2.0 0.8 2.2 ns 3-state Delays latch (1) TIOTLPHZ T input to pad high mpedance via transparent TIOTLPON T input to valid data on pad via transparent latch 1.2 3.2 1.2 3.4 ns TGTS impedance (1) 1.9 4.6 1.9 4.9 ns GTS to pad high Sequential Delays TIOCKP Clock CLK to pad 0.9 2.8 0.9 2.9 ns TIOCKHZ Clock CLK to pad high impedance (synchronous) (1) 0.7 2.0 0.7 2.2 ns TIOCKON Clock CLK to valid data on pad (synchronous) 1.1 3.2 1.1 3.4 ns 1.0 / 0 - 1.1 / 0 - ns TIOOCECK / TIOCKOCE OCE input 0.7 / 0 - 0.7 / 0 - ns TIOSRCKO / TIOCKOSR SR input (OFF) 0.9 / 0 - 1.0 / 0 - ns 0.6 / 0 - 0.7 / 0 - ns TIOTCECK / TIOCKTCE 3-state setup times, TCE input 0.6 / 0 - 0.8 / 0 - ns TIOSRCKT / TIOCKTSR 3-state setup times, SR input (TFF) 0.9 / 0 - 1.0 / 0 - ns 1.2 3.3 1.2 3.5 ns 1.0 2.4 1.0 2.7 ns Setup/Hold Times with Respect to Clock CLK TIOOCK / TIOCKO TIOTCK / TIOCKT O input 3-state setup times, T input Set/Reset Delays TIOSRP SR input to pad (asynchronous) (asynchronous) (1) TIOSRHZ SR input to pad high impedance TIOSRON SR input to valid data on pad (asynchronous) 1.4 3.7 1.4 3.9 ns TIOGSRQ GSR to pad 3.8 8.5 3.8 9.7 ns Notes: 1. Three-state turn-off delays should not be adjusted. DS077-3 (v2.0) November 18, 2002 Product Specification www.xilinx.com 1-800-255-7778 9 R Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics IOB Output Delay Adjustments for Different Standards(1) Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays by the values shown. A delay adjusted in this way constitutes a worst-case limit. Speed Grade Symbol Description Standard -7 -6 Units LVTTL, Slow, 2 mA 14.7 14.7 ns 4 mA 7.5 7.5 ns 6 mA 4.8 4.8 ns Output Delay Adjustments (Adj) TOLVTTL_S2 TOLVTTL_S4 TOLVTTL_S6 Standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, C SL) 8 mA 3.0 3.0 ns TOLVTTL_S12 12 mA 1.9 1.9 ns TOLVTTL_S16 16 mA 1.7 1.7 ns TOLVTTL_S24 24 mA 1.3 1.3 ns 13.1 13.1 ns TOLVTTL_S8 TOLVTTL_F2 LVTTL, Fast, 2 mA TOLVTTL_F4 4 mA 5.3 5.3 ns TOLVTTL_F6 6 mA 3.1 3.1 ns TOLVTTL_F8 8 mA 1.0 1.0 ns TOLVTTL_F12 12 mA 0 0 ns TOLVTTL_F16 16 mA –0.05 –0.05 ns TOLVTTL_F24 24 mA –0.20 –0.20 ns TOLVCMOS2 LVCMOS2 0.09 0.09 ns TOLVCMOS18 LVCMOS18 0.7 0.7 ns LVDS –1.2 –1.2 ns TOLVPECL LVPECL –0.41 –0.41 ns TOPCI33_3 PCI, 33 MHz, 3.3V 2.3 2.3 ns TOPCI66_3 TOLVDS PCI, 66 MHz, 3.3V –0.41 –0.41 ns TOGTL GTL 0.49 0.49 ns TOGTLP GTL+ 0.8 0.8 ns TOHSTL_I HSTL I –0.51 –0.51 ns TOHSTL_III HSTL III –0.91 –0.91 ns TOHSTL_IV HSTL IV –1.01 –1.01 ns TOSSTL2_I SSTL2 I –0.51 –0.51 ns TOSSLT2_II SSTL2 II –0.91 –0.91 ns TOSSTL3_I SSTL3 I –0.51 –0.51 ns TOSSTL3_II SSTL3 II –1.01 –1.01 ns TOCTT CTT –0.61 –0.61 ns TOAGP AGP –0.91 –0.91 ns Notes: 1. Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. For other I/O standards and different loads, see the tables Constants for Calculating TIOOP and Delay Measurement Methodology, page 11. 10 www.xilinx.com 1-800-255-7778 DS077-3 (v2.0) November 18, 2002 Product Specification R Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics Calculation of TIOOP as a Function of Capacitance Constants for Calculating TIOOP CSL(1) (pF) FL (ns/pF) TIOOP is the propagation delay from the O Input of the IOB to the pad. The values for TIOOP are based on the standard capacitive load (C SL) for each I/O standard as listed in the table Constants for Calculating TIOOP, below. LVTTL Fast Slew Rate, 2 mA drive 35 0.41 LVTTL Fast Slew Rate, 4 mA drive 35 0.20 For other capacitive loads, use the formulas below to calculate an adjusted propagation delay, TIOOP1. LVTTL Fast Slew Rate, 6 mA drive 35 0.13 LVTTL Fast Slew Rate, 8 mA drive 35 0.079 LVTTL Fast Slew Rate, 12 mA drive 35 0.044 LVTTL Fast Slew Rate, 16 mA drive 35 0.043 LVTTL Fast Slew Rate, 24 mA drive 35 0.033 LVTTL Slow Slew Rate, 2 mA drive 35 0.41 LVTTL Slow Slew Rate, 4 mA drive 35 0.20 LVTTL Slow Slew Rate, 6 mA drive 35 0.100 LVTTL Slow Slew Rate, 8 mA drive 35 0.086 LVTTL Slow Slew Rate, 12 mA drive 35 0.058 LVTTL Slow Slew Rate, 16 mA drive 35 0.050 LVTTL Slow Slew Rate, 24 mA drive 35 0.048 LVCMOS2 35 0.041 LVCMOS18 35 0.050 PCI 33 MHz 3.3V 10 0.050 PCI 66 MHz 3.3V 10 0.033 GTL 0 0.014 GTL+ 0 0.017 HSTL Class I 20 0.022 HSTL Class III 20 0.016 HSTL Class IV 20 0.014 SSTL2 Class I 30 0.028 SSTL2 Class II 30 0.016 SSTL3 Class I 30 0.029 SSTL3 Class II 30 0.016 TIOOP1 = TIOOP + Adj + (CLOAD – CSL) * FL Where: Adj is selected from IOB Output Delay Adjustments for Different Standards(1), page 10, according to the I/O standard used CLOAD is the capacitive load for the design FL is the capacitance scaling factor Delay Measurement Methodology Meas. VREF Point Typ (2) VL(1) VH (1) LVTTL 0 3 1.4 - LVCMOS2 0 2.5 1.125 - Standard PCI33_3 Per PCI Spec - PCI66_3 Per PCI Spec - GTL VREF – 0.2 VREF + 0.2 VREF 0.80 GTL+ VREF – 0.2 VREF + 0.2 VREF 1.0 HSTL Class I VREF – 0.5 VREF + 0.5 VREF 0.75 HSTL Class III VREF – 0.5 VREF + 0.5 VREF 0.90 HSTL Class IV VREF – 0.5 VREF + 0.5 VREF 0.90 SSTL3 I and II VREF – 1.0 VREF + 1.0 VREF 1.5 SSTL2 I and II VREF – 0.75 VREF + 0.75 VREF 1.25 Standard CTT VREF – 0.2 VREF + 0.2 VREF 1.5 AGP VREF + VREF – (0.2xVCCO) (0.2xVCCO) VREF Per AGP Spec LVDS 1.2 – 0.125 1.2 + 0.125 1.2 CTT 20 0.035 1.6 AGP 10 0.037 LVPECL 1.6 – 0.3 1.6 + 0.3 Notes: 1. Input waveform switches between VL and VH. 2. Measurements are made at VREF Typ, Maximum, and Minimum. Worst-case values are reported. 3. I/O parameter measurements are made with the capacitance values shown in the following table, Constants for Calculating TIOOP. Refer to Application Note XAPP179 for appropriate terminations. 4. I/O standard measurements are reflected in the IBIS model information except where the IBIS format precludes it. DS077-3 (v2.0) November 18, 2002 Product Specification Notes: 1. I/O parameter measurements are made with the capacitance values shown above. Refer to Application Note XAPP179 for appropriate terminations. 2. I/O standard measurements are reflected in the IBIS model information except where the IBIS format precludes it. www.xilinx.com 1-800-255-7778 11 R Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics Clock Distribution Switching Characteristics TGPIO is specified for LVTTL levels. For other standards, adjust TGPIO with the values shown in I/O Standard Global Clock Input Adjustments. Speed Grade Symbol Description -7 -6 Max Max Units GCLK IOB and Buffer TGPIO Global clock pad to output 0.7 0.7 ns TGIO Global clock buffer I input to O output 0.45 0.5 ns I/O Standard Global Clock Input Adjustments Delays associated with a global clock input pad are specified for LVTTL levels. For other standards, adjust the delays by the values shown. A delay adjusted in this way constitutes a worst-case limit. Speed Grade Symbol Description Standard -7 -6 Units LVTTL 0 0 ns LVCMOS2 0 0 ns TGPLVCMOS18 LVCMOS18 0.2 0.2 ns TGPLVCDS LVDS 0.38 0.38 ns TGPLVPECL LVCPECL 0.38 0.38 ns TGPPCI33_3 PCI, 33 MHz, 3.3V 0.08 0.08 ns TGPPCI66_3 PCI, 66 MHz, 3.3V –0.11 –0.11 ns TGPGTL GTL 0.37 0.37 ns TGPGTLP GTL+ 0.37 0.37 ns TGPHSTL HSTL 0.27 0.27 ns TGPSSTL2 SSTL2 0.27 0.27 ns TGPSSTL3 SSTL3 0.27 0.27 ns TGPCTT CTT 0.33 0.33 ns TGPAGP AGP 0.27 0.27 ns Data Input Delay Adjustments TGPLVTTL TGPLVCMOS2 Standard-specific global clock input delay adjustments Notes: 1. Input timing for GPLVTTL is measured at 1.4V. For other I/O standards, see the table Delay Measurement Methodology, page 11. 12 www.xilinx.com 1-800-255-7778 DS077-3 (v2.0) November 18, 2002 Product Specification R Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics DLL Timing Parameters Because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case values across the recommended operating conditions. Speed Grade -7 Symbol Description -6 FCLKIN Min Max Min Max Units FCLKINHF Input clock frequency (CLKDLLHF) - 60 320 60 275 MHz FCLKINLF Input clock frequency (CLKDLL) - 25 160 25 135 MHz TDLLPW Input clock pulse width ≥25 MHz 5.0 - 5.0 - ns ≥50 MHz 3.0 - 3.0 - ns ≥100 MHz 2.4 - 2.4 - ns ≥150 MHz 2.0 - 2.0 - ns ≥200 MHz 1.8 - 1.8 - ns ≥250 MHz 1.5 - 1.5 - ns ≥300 MHz 1.3 - NA - DLL Clock Tolerance, Jitter, and Phase Information All DLL output jitter and phase specifications were determined through statistical measurement at the package pins using a clock mirror configuration and matched drivers. Figure 1, page 14, provides definitions for various parameters in the table below. CLKDLLHF Symbol Description FCLKIN Min Max CLKDLL Min Max Units TIPTOL Input clock period tolerance - 1.0 - 1.0 ns TIJITCC Input clock jitter tolerance (cycle-to-cycle) - ±150 - ±300 ps TLOCK Time required for DLL to acquire lock(1) > 60 MHz - 20 - 20 µs 50-60 MHz - - - 25 µs TOJITCC Output jitter (cycle-to-cycle) for any DLL clock - - 50 µs - - 90 µs 25-30 MHz - - - 120 µs - ±60 - ±60 ps - ±100 - ±100 ps - ±140 - ±140 ps - ±160 - ±160 ps - ±200 - ±200 ps CLKO (3) TPHIO Phase offset between CLKIN and Phase offset between clock outputs on the DLL(4) TPHOOM - output (2) TPHOO TPHIOM 40-50 MHz 30-40 MHz Phase difference between CLKIN and CLKO (5) Phase difference between clock outputs on the DLL(6) Notes: 1. Commercial operating conditions. Add 30% for Industrial operating conditions. 2. Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter. 3. Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO, excluding output jitter and input clock jitter. 4. Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL outputs, excluding output jitter and input clock jitter. 5. Maximum Phase Difference between CLKIN and CLKO is the sum of output jitter and phase offset between CLKIN and CLKO, or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter). 6. Maximum Phase Difference between Clock Outputs on the DLL is the sum of output jitter and phase offset between any DLL clock outputs, or the greatest difference between any two DLL output rising edges due to DLL alone (excluding input clock jitter). DS077-3 (v2.0) November 18, 2002 Product Specification www.xilinx.com 1-800-255-7778 13 R Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics Period Tolerance: the allowed input clock period change in nanoseconds. T CLKIN = 1 FCLKIN TCLKIN +_ TIPTOL Output Jitter: the difference between an ideal reference clock edge and the actual design. Phase Offset and Maximum Phase Difference Ideal Period Actual Period + Jitter +/- Jitter + Maximum Phase Difference + Phase Offset DS077_52_071201 Figure 1: Period Tolerance and Clock Jitter 14 www.xilinx.com 1-800-255-7778 DS077-3 (v2.0) November 18, 2002 Product Specification R Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics CLB Switching Characteristics Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise values are provided by the timing analyzer. Speed Grade -7 Symbol Description -6 Min Max Min Max Units Combinatorial Delays TILO 4-input function: F/G inputs to X/Y outputs 0.18 0.42 0.18 0.47 ns TIF5 5-input function: F/G inputs to F5 output 0.3 0.8 0.3 0.9 ns TIF5X 5-input function: F/G inputs to X output 0.3 0.8 0.3 0.9 ns TIF6Y 6-input function: F/G inputs to Y output via F6 MUX 0.3 0.9 0.3 1.0 ns TF5INY 6-input function: F5IN input to Y output 0.04 0.2 0.04 0.22 ns TIFNCTL Incremental delay routing through transparent latch to XQ/YQ outputs - 0.7 - 0.8 ns BY input to YB output 0.18 0.46 0.18 0.51 ns TCKO FF clock CLK to XQ/YQ outputs 0.3 0.9 0.3 1.0 ns TCKLO Latch clock CLK to XQ/YQ outputs 0.3 0.9 0.3 1.0 ns TBYYB Sequential Delays Setup/Hold Times with Respect to Clock CLK TICK / TCKI 4-input function: F/G inputs 1.0 / 0 - 1.1 / 0 - ns TIF5CK / TCKIF5 5-input function: F/G inputs 1.4 / 0 - 1.5 / 0 - ns TF5INCK / TCKF5IN 6-input function: F5IN input 0.8 / 0 - 0.8 / 0 - ns 6-input function: F/G inputs via F6 MUX 1.5 / 0 - 1.6 / 0 - ns BX/BY inputs 0.7 / 0 - 0.8 / 0 - ns CE input 0.7 / 0 - 0.7 / 0 - ns SR/BY inputs (synchronous) 0.52 / 0 - 0.6 / 0 - ns TIF6CK / TCKIF6 TDICK / TCKDI TCECK / TCKCE TRCK / TCKR Clock CLK TCH Pulse width, High 1.3 - 1.4 - ns TCL Pulse width, Low 1.3 - 1.4 - ns Pulse width, SR/BY inputs 2.1 - 2.4 - ns TRQ Delay from SR/BY inputs to XQ/YQ outputs (asynchronous) 0.3 0.9 0.3 1.0 ns FTOG Toggle frequency (for export control) - 400 - 357 MHz Set/Reset TRPW DS077-3 (v2.0) November 18, 2002 Product Specification www.xilinx.com 1-800-255-7778 15 R Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics CLB Arithmetic Switching Characteristics Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment listed. Precise values are provided by the timing analyzer. Speed Grade -7 Symbol Description -6 Min Max Min Max Units Combinatorial Delays TOPX F operand inputs to X via XOR - 0.8 - 0.8 ns TOPXB F operand input to XB output - 0.8 - 0.9 ns TOPY F operand input to Y via XOR - 1.4 - 1.5 ns TOPYB F operand input to YB output - 1.1 - 1.3 ns TOPCYF F operand input to COUT output - 0.9 - 1.0 ns TOPGY G operand inputs to Y via XOR - 0.8 - 0.9 ns TOPGYB G operand input to YB output - 1.2 - 1.3 ns TOPCYG G operand input to COUT output - 0.9 - 1.0 ns TBXCY BX initialization input to COUT - 0.51 - 0.6 ns TCINX CIN input to X output via XOR - 0.6 - 0.7 ns TCINXB CIN input to XB - 0.07 - 0.1 ns TCINY CIN input to Y via XOR - 0.7 - 0.7 ns TCINYB CIN input to YB - 0.4 - 0.5 ns CIN input to COUT output - 0.14 - 0.15 ns TFANDXB F1/2 operand inputs to XB output via AND - 0.35 - 0.4 ns TFANDYB F1/2 operand inputs to YB output via AND - 0.7 - 0.8 ns TFANDCY F1/2 operand inputs to COUT output via AND - 0.5 - 0.6 ns TGANDYB G1/2 operand inputs to YB output via AND - 0.6 - 0.7 ns TGANDCY G1/2 operand inputs to COUT output via AND - 0.3 - 0.4 ns TBYP Multiplier Operation Setup/Hold Times with Respect to Clock CLK 16 TCCKX / TCKCX CIN input to FFX 1.2 / 0 - 1.3 / 0 - ns TCCKY / TCKCY CIN input to FFY 1.2 / 0 - 1.3 / 0 - ns www.xilinx.com 1-800-255-7778 DS077-3 (v2.0) November 18, 2002 Product Specification R Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics CLB Distributed RAM Switching Characteristics Speed Grade -7 Symbol Sequential Delays Description -6 Min Max Min Max Units TSHCKO16 Clock CLK to X/Y outputs (WE active, 16 x 1 mode) 0.6 1.5 0.6 1.7 ns TSHCKO32 Clock CLK to X/Y outputs (WE active, 32 x 1 mode) 0.8 1.9 0.8 2.1 ns - 0.5 / 0 - ns Setup/Hold Times with Respect to Clock CLK TAS / TAH F/G address inputs 0.42 / 0 TDS / TDH BX/BY data inputs (DIN) 0.53 / 0 - 0.6 / 0 - ns CE input (WS) 0.7 / 0 - 0.8 / 0 - ns 2.1 - 2.4 - ns TWS / TWH Clock CLK TWPH Pulse width, High TWPL Pulse width, Low 2.1 - 2.4 - ns TWC Clock period to meet address write cycle time 4.2 - 4.8 - ns CLB Shift Register Switching Characteristics Speed Grade -7 Symbol Description -6 Min Max Min Max Units 1.2 2.9 1.2 3.2 ns BX/BY data inputs (DIN) 0.53 / 0 - 0.6 / 0 - ns CE input (WS) 0.7 / 0 - 0.8 / 0 - ns Sequential Delays TREG Clock CLK to X/Y outputs Setup/Hold Times with Respect to Clock CLK TSHDICK TSHCECK Clock CLK TSRPH Pulse width, High 2.1 - 2.4 - ns TSRPL Pulse width, Low 2.1 - 2.4 - ns Block RAM Switching Characteristics Speed Grade -7 Symbol Sequential Delays TBCKO Description Clock CLK to DOUT output -6 Min Max Min Max Units 0.6 3.1 0.6 3.5 ns Setup/Hold Times with Respect to Clock CLK TBACK / TBCKA ADDR inputs 1.0 / 0 - 1.1 / 0 - ns TBDCK/ TBCKD DIN inputs 1.0 / 0 - 1.1 / 0 - ns TBECK/ TBCKE EN inputs 2.2 / 0 - 2.5 / 0 - ns TBRCK/ TBCKR RST input 2.1 / 0 - 2.3 / 0 - ns WEN input 2.0 / 0 - 2.2 / 0 - ns TBWCK/ TBCKW Clock CLK TBPWH Pulse width, High 1.4 - 1.5 - ns TBPWL Pulse width, Low 1.4 - 1.5 - ns TBCCS CLKA -> CLKB setup time for different ports 2.7 - 3.0 - ns DS077-3 (v2.0) November 18, 2002 Product Specification www.xilinx.com 1-800-255-7778 17 R Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics TBUF Switching Characteristics Speed Grade Symbol Description -7 -6 Max Max Units 0 0 ns IN input to OUT output TIO TOFF TRI input to OUT output high impedance 0.1 0.11 ns TON TRI input to valid data on OUT output 0.1 0.11 ns JTAG Test Access Port Switching Characteristics Speed Grade -7 Symbol Description Setup/Hold Times with Respect to TCK TTAPTCK / TTCKTAP Sequential Delays TTCKTDO Min Max Min Max Units 4.0 / 2.0 - 4.0 / 2.0 - ns Output delay from clock TCK to output TDO - 11.0 - 11.0 ns TCK clock frequency - 33 - 33 MHz TMS and TDI setup times and hold times FTCK -6 Configuration Switching Characteristics VCC(1) TPOR PROGRAM TPL INIT TICCK CCLK Output or Input M0, M1, M2 (Required) Valid DS077_02_110101 . All Devices Symbol Description Min Max Units TPOR Power-on reset - 2 ms TPL Program latency - 100 µs TICCK CCLK output delay (Master serial mode only) 0.5 4 µs TPROGRAM Program pulse width 300 - ns Notes: 1. Before configuration can begin, VCCINT and VCCO Bank 2 must reach the recommended operating voltage. Figure 2: Configuration Timing on Power-Up 18 www.xilinx.com 1-800-255-7778 DS077-3 (v2.0) November 18, 2002 Product Specification R Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics DIN TCCD TDCC TCCL CCLK TCCH TCCO DOUT (Output) DS001_16_032300 . All Devices Symbol Description TDCC / TCCD TCCO DIN setup/hold DOUT CCLK Min Max Units 5/0 - ns - 12 ns High time 5 - ns TCCL Low time 5 - ns FCC Maximum frequency - 66 MHz TCCH Figure 3: Slave Serial Mode Timing CCLK (Output) TCKDS TDSCK Serial Data In Serial DOUT (Output) DS001_17_032300 . All Devices Symbol Description DIN setup/hold TDSCK / TCKDS TCCO CCLK FCC Min Max 5/0 - ns - 12 ns –30% +45% - DOUT Frequency tolerance with respect to nominal Units Figure 4: Master Serial Mode Timing DS077-3 (v2.0) November 18, 2002 Product Specification www.xilinx.com 1-800-255-7778 19 R Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics CCLK CS WRITE TSMCCCS TSMCSCC TSMWCC TSMCCW TSMDCC TSMCCD DATA[7:0] TSMCKBY BUSY No Write Write No Write Write DS001_20_061200 All Devices Symbol Description Min Max Units TSMDCC / TSMCCD D0-D7 setup/hold 5/1 - ns TSMCSCC / TSMCCCS CS setup/hold 7/1 - ns WRITE setup/hold 7/1 - ns TSMCCW / TSMWCC CCLK TSMCKBY BUSY propagation delay - 12 ns FCC Frequency - 66 MHz FCCNH Frequency with no handshake - 50 MHz Figure 5: Slave Parallel (SelectMAP) Mode Write Timing CCLK CS WRITE DATA[7:0] BUSY Abort DS001_21_032300 Figure 6: Slave Parallel (SelectMAP) Mode Write Abort Waveforms 20 www.xilinx.com 1-800-255-7778 DS077-3 (v2.0) November 18, 2002 Product Specification R Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics Revision History Version No. Date Description 1.0 11/15/01 Initial Xilinx release. 1.1 06/28/02 Added -7 speed grade and extended DLL specs to Industrial. 2.0 11/18/02 Added XC2S400E and XC2S600E. Added minimum specifications. Added note to I/O leakage spec. Added reference to XAPP450 for Power-On Requirements. Removed Preliminary designation. The Spartan-IIE Family Data Sheet DS077-1, Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information (Module 1) DS077-2, Spartan-IIE 1.8V FPGA Family: Functional Description (Module 2) DS077-3, Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics (Module 3) DS077-4, Spartan-IIE 1.8V FPGA Family: Pinout Tables (Module 4) DS077-3 (v2.0) November 18, 2002 Product Specification www.xilinx.com 1-800-255-7778 21