ZARLINK SL1461MPAS

SL1461SA
Wideband PLL FM Demodulator
Advance Information
FEATURES
■ Single chip PLL system for wideband FM
demodulation
■ Simple low component count application
■ Allows for application of threshold extension
■ Fully balanced low radiation design
■ High operating input sensivity
■ Improved VCO stability with variations in supply or
temperature
■ AGC detect and bias adjust
■ 75Ω video output drive with low distortion levels
■ Dynamic self biasing analog AFC
■ Full ESD Protection*
* Normal ESD handling procedures should be observed
DS4358
ISSUE 1.3
SL1461SA/KG/MPAS
1
16
AFC WINDOW ADJUST
2
15
V CC
V EE
3
14
VIDEO FEEDBACK +
13
VIDEO –
OSCILLATOR +
4
OSCILLATOR –
5
VIDEO +
12
AGC BIAS
6
11
AGC OUTPUT
7
10
RF INPUT
8
9
VIDEO FEEDBACK –
VIDEO OUTPUT
RF INPUT
MP16
Fig.1 Pin connections - top view
APPLICATIONS
■ Satellite receiver systems
■ Data communications Systems
6
14
RF INPUTS
8
9
12
13
AGC OUTPUT
7
11
10
1
AFC WINDOW
ADJUST
AFC OUTPUT
AFC PUMP
AGC BIAS
LOCAL
OSCILLATOR
September 1999
Ordering Information
SL1461SA
The SL1461SA is a wideband PLL FM demodulator,
intended primarily for application in satellite tuners.
The device contains all elements necessary, with the
exception of external oscillator sustaining network and loop
feedback components, to form a complete PLL system
operating at frequencies up to 800MHz.
An AFC with window adjust is provided, whose output
signal can be used to correct for any frequency drift at the head
end local oscillator.
4
16
5
2
Fig.2 SL1461SA block diagram
VIDEO
FEEDBACK +
VIDEO +
VIDEO –
VIDEO
FEEDBACK –
VIDEO
OUTPUT
AFC PUMP
AFC OUTPUT
SP1461SA
Advance Information
ELECTRICAL CHARACTERISTICS
Tamb = -20°C to +80°C, VCC = +4.5V to +5.5V. The electrical characteristics are guaranteed by either production test or design.
They apply within the specified ambient temperature and supply voltage unless otherwise stated.
Value
Characteristics
Min.
Supply current
Operating frequency
Typ.
36
300
Input sensitivity
Units
40
mA
800
MHz
-40
Input overload
0
VCO sensitivity (dF/dV)
25
dBm
Preamp limiting
dBm
32
39
25
VCO linearity
Conditions
Max.
MHz/V
%
Refer to application in Fig. 3
Refer to application in Fig. 3; with
13.5MHz p-p deviation
VCO supply stability
2.0
MHz/V
See note 5
VCO temperature stability
20
KHz/°C
See note 5
Phase detector gain
0.5
V/rad
Differential loop filter
0.25
V/rad
Single ended loop filter
Ω
Single ended
Loop amplifier output impedance
25
Ω
Single ended
Loop amplifier open loop gain
38
dB
Single ended
Loop amplifier gain bandwidth product
240
Loop amplifier input impedance
450
570
700
MHz
Single ended
1.2
Vp-p
Single ended
95
Ω
1.9
5
%
1KΩ load, See note 3 and 4
- differential gain
0.5
2.5
%
75KΩ load, See note 3 and 4
- differential phase
1.0
3
Degree
75KΩ load, See note 3 and 4
-40
dB
See notes 1, 3 and 4
dB
1KΩ load, See note 2 and 4
Loop amplifier output swing
Video drive output impedance
55
75
Video drive:
Luminance nonlinearity
- intermodulation
- signal/noise
66
- Tilt
- baseline distortion
72
0.3
3
%
1KΩ load, See note 3 and 4
0.4
2
%
1KΩ load, See note 3 and 4
AGC output current
10
400
µA
Maximum load voltage drop 2V
AGC bias current
0
250
µA
AFC window current
0
400
µA
AFC charge pump current
400µA gives 1.5V deadband window
µA
50
AFC leakage current
10
µA
With charge pump disabled
AFC output saturation voltage
0.4
V
AFC output enabled
Note 1. Product of input modulation f 1 at 4.43MHz, 13.5MHz p–p deviation and f 2 at 6MHz p–p deviation, (PAL chroma and sound
subcarriers).
Note 2. Ratio of output video signal with input modulation at 1MHz, 13.5MHz p–p deviation, to output rms noise in 6MHz bandwidth
with no input modulation.
Note 3. Input test signal pre–emphasised video 13.5MHz p–p deviation. Output voltage 600mV pk–pk.
Note 4. See page 3
Note 5. Assuming operating frequency of 479.5MHz set with VCC @ 5.0V and ambient temperature of +20°C. Only applies to Application
shown in Fig. 3. also refer to Fig. 8.
2
Advance Information
TEST CONFIGURATION
SL1461SA
BASE BAND VIDEO 1V p–p
VIDEO GENERATOR
ROHDE & SCHWARZ SGPF
TV SAT TEST TX
ROHDE & SCHWARZ SFZ
RF CARRIER FREQ 479.5MHz
FM MODULATION 13.5MHz P–P
PRE–EMPHASISED VIDEO
MONTFORD
TEST OVEN
SL1461 TEST APPLICATION BOARD
See Fig. 3 for details
PRE EMPHASISED BASE BAND VIDEO
VIDEO AMPLIFIER/
DE EMPHASISED NETWORK
DE EMPHASISED BASE BAND VIDEO 1V p–p
VIDEO ANALYSER
ROHDE & SCHWARZ UAF
The video drive characteristics measurements were made using the above test configuration. The maximum figures recorded in
the Electrical Characteristics Table coincide with high temperatures and extremes of supply voltage. No adjustment to the recorded
figures has been made to compensate for the effects of temperature on the external components of the application test board, in
particular the varactor diodes. If operation of the device at high ambient temperatures is envisaged then attention to temperature
compensation of the external circuitry will result in performance figures closer to the stated typical figures.
Fig.2 SL1461SA block diagram
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to VEE at 0V
Characteristics
Supply voltage
Min.
-0.3
RF input voltage
Typ.
Max.
7
V
2.5
Vp-p
RF input DC offset
-0.3
VCC+0.3
V
Oscillator ± DC offset
-0.3
VCC+0.3
V
Video ± DC offset
-0.3
VCC+0.3
V
Video feedback ± DC offset
-0.3
VCC+0.3
V
Video output DC offset
-0.3
VCC+0.3
V
AFC pump DC offset
-0.3
VCC+0.3
V
AFC disable DC offset
-0.3
VCC+0.3
V
AFC deadband DC offset
-0.3
VCC+0.3
V
AGC bias DC offset
-0.3
VCC+0.3
V
AGC output DC offset
-0.3
VCC+0.3
V
Storage temperature
-55
125
°C
Junction temperature
150
°C
MP16 package thermal resistance,
chip to ambient
111
°C/W
Conditions
3
SP1461SA
Advance Information
ABSOLUTE MAXIMUM RATINGS cont.
All voltages are referred to VEE at 0V
Characteristics
Min.
Conditions
Typ.
Max.
MP16 package thermal resistance,
chip to case
41
°C/W
Power consumption at 5.5V
250
mW
ESD protection - pins 1 to 15
2K
AGC BIAS
50K
RV1
kV
Mil-std-883 method 3015 class 1
1.7
kV
Mil-std-883 method 3015 class 1
27K
RV2
C1
C2
47nF
100nF
R1
C5
4n7
C6
16
2
15
4
5
R2
TP3
1
3
BB515 470nF
D2
100nF
AFC WINDOW ADJUST
4K7
D1
BB515
2
5K1
4K7
R3
C7
1nF
SL1461SA
ESD protection - Pin 16
R6
C3
47 F
+5V
1nF
C4
C12
TP4
R5
100pF
TP1
14
13
12
6
11
7
10
8
9
1K2
C11
R4
C10
TP2
100pF
1K2
C9
47 F
C8
VIDEO OUTPUT
1nF
RF INPUT
Fig.3 Standard application circuit
FUNCTIONAL DESCRIPTION
The SL1461SA is a wideband PLL FM demodulator,
optimised for application in satellite receiver systems and
requiring a minimum external component count. It contains all
the elements required for construction of a phase locked loop
circuit, with the exception of tuning components for the local
oscillator, and an AFC detector circuit for generation of error
signal to correct for any frequency drift in the outdoor unit local
oscillator. A block diagram is contained in Fig. 2 and the
typical application in Fig. 3.
The internal pin connections are contained in Fig.6/6a
In normal applications the second satellite IF frequency
of typically 402 or 479.5MHz is fed to the RF preamplifier,
which has a working sensitivity of typically -40 dBm,
depending on application and layout. The preamplifier
contains an RF level detect circuit, which generates an AGC
signal that can be used for controlling the gain of the IF
amplifier stages, so maintaining a fixed level to the RF input
of the SL1461SA, for optimum threshold performance. The
bias point of the AGC circuit can be adjusted to cater for
variation in AGC line voltage requirement and device input
power. The typical AGC curves are shown in Fig. 9. It is
recommended that the device is operated with an input signal
between -30 and -35dBm. This ensures optimum linearity and
4
threshold performance, and gives a good safety margin over
the typical sensitivity of
-40dBm.
The output of the preamplifier is fed to the mixer section
which is of balanced design for low radiation. In this stage the
RF signal is mixed with the local oscillator frequency, which
is generatedby an on–board oscillator. The oscillator block
uses an external varactor tuned sustaining network and is
optimised for high linearity over the normal deviation range.
A typical frequency versus voltage characteristic for the
oscillator is contained in Fig. 7. The loop output is designed
to compensate for first order temperature variation effects;
the typical stability is shown in Fig. 8
The output of the mixer is then fed to the loop amplifier
around which feedback is applied to determine loop transfer
characteristic . Feedback can be applied either in differential
or single ended mode; if the appropriate phase detector gains
are assumed in calculating loop filters, both modes should
give the same loop response.
The loop amplifier drives a 75Ω output impedance buffer
amplifier, which can either be connected to a 75Ω load or used
to drive a high input impedance stage giving greater linearity
and approximately 6dB higher demodulated signal output
level.
Advance Information
SL1461SA
DESIGN OF PLL LOOP PARAMETERS
R2
GAIN = KD VOLT/RAD
RF INPUT
C1
R1
BASEBAND OUTPUT
GAIN = K0 RAD SEC/VOLT
VCO
Fig.4
The SL1461SA is normally used as a type 1 second order
loop and can be represented by the above diagram. For such
a system the following parameters apply;
1
where:
K0 is the VCO gain in radian seconds per volt
KD is the phase detector gain in volts per radian
n is the natural loop bandwidth
is the loop damping factor
R1 is loop amplifier input impedance
Note:
2
and
K 0K D
1
K0 is dependant on sensitivity of VCO used.
KD = 0.25V/rad single ended, 0.5V/rad differential
From these factors the loop 3dB bandwidth can be determined
from the following expression;
2
n
2
2
n
AFC FACILITY
The SL1461SA contains an analog frequency error
detect circuit, which generates DC voltage proportional to the
integral of frequency error. If the incident RF is high then the
AFC voltage increases, if low then the voltage decreases. The
AFC voltage can then be converted by an ADC to be read by
the micro controller for frequency fine tuning; if used in an I2C
system it is recommended the device is used with either the
SP5055 or SP5056 frequency synthesiser which contains an
internal ADC readable via the I2C bus.
The voltage corresponding to frequency alignment is
arbitrary and user defined; if used with the SP5055 it is
suggested the aligned voltage is 0.375 VCC , corresponding to
the centre code of the ADC on port 6.
The AFC detect circuit contains a deadband centre
around the aligned frequency. The deadband can be adjusted
from zero window to approximately 25MHz width assuming an
oscillator dF/dV of 15MHz/V. If the incident RF is within this
window the AFC voltage does not integrate, except by
component leakage.
With reference to Fig.5; in normal operation the
demodulated video is fed to a dual comparator where it is
compared with two reference voltages, corresponding to the
extremes of the deadband, or window. These voltages are
variable and set by the window adjust input.
The comparators produce two digital outputs
corresponding to voltages above or below the voltage
window, or frequency above or below deadband. These digital
control signals are used to control a complimentary current
source pump. The current signals are then fed to the input of
an amplifier which is arranged as an integrator, so integrating
the
pulses into a DC voltage.
If the frequency is correctly aligned both the current
source and sink are disabled, therefore the DC output voltage
remains constant. There will be a small drift due to component
leakage; the maximum drift can be calculated from;
5
SP1461SA
Advance Information
WINDOW
ADJUST
V HI
V ALIGN
V LO
FREQ
VCC
VCC
+
–
REXT
CEXT
BASEBAND
VIDEO
V AFC
+
–
VEE
Fig.5 AFC system block diagram
6
Advance Information
VCC
SL1461SA
AGC BIAS
VREF; 2.7V
VREF; 2V
AGC OUTPUT
AGC output
AGC bias adjust
VREF; 3V
AFC WINDOW
2x1500
RF INPUTS
VREF; 1.6V
RF inputs
AFC window adjust
VCC
AFC PUMP
VIDEO +
10K
AFC OUTPUT
330
2mA
AFC output stage
VIDEO –
330
2mA
Video amp outputs
Fig.6 SL1461SA I/O port internal circuitry
7
SP1461SA
Advance Information
VREF; 1.2V
2 x 5k
OSCILLATOR +
OSCILLATOR –
Local oscillator
FROM PHASE DETECTOR
VCC
2x570
68
105
VIDEO
FEEDBACK +
VIDEO
FEEDBACK –
4mA
Video output drive
Video amp feedback inputs
Fig.6a SL1461SA I/O port internal circuitry
FREQ MHz
520
500
480
460
440
420
400
360
1
1.5
2
2.5
3
3.5
4
4.5
5
DC VOLTAGE
Fig.7 Typical VCO frequency vs DC control voltage
8
VIDEO
OUTPUT
SL1461SA
Advance Information
VCO STABILITY vs TEMP and SUPPLY
480
479.5
FREQUENCY (MHz)
479
SUPPLY (V)
4.5
478.5
4.75
478
5
477.5
5.25
477
5.5
476.5
476
475.5
–20
5
55
30
80
TEMP/°C
Fig.8 SL1461SA VCO centre frequency uncompensated temperature stability
2.0
1.5
AGC
OUTPUT 1.0
VOLTAGE
AGC BIAS RESISTOR 5.1K
AGC BIAS CURRENT 297 A
AGC LOAD RESISTOR 3.9K
0.5
AGC BIAS RESISTOR 10.5K
AGC BIAS CURRENT 150 A
AGC LOAD RESISTOR 4.7K
AGC BIAS RESISTOR 32K
AGC BIAS CURRENT 52 A
AGC LOAD RESISTOR 10K
–70
–60
–50
–40
–30
–20
–10
0
RF INPUT LEVEL (dBm) UNMODULATED
VCC = 5.0 VOLTS
Fig.9 SL1461SA AGC output voltage for differing values of AGC bias resistor
APPLICATION NOTES
Capture range
Under conditions when there is no RF input signal
present, the SL1461SA may react to spurious radiation from
the free running oscillator coupling into the RF inputs.
Because of the constant phase error between the VCO input
to the phase detector and the spuriously coupled signal via the
RF input, the phase comparator will drive the control voltage
to either the bottom or the top of the range.
In such a case, the capture range will be asymmetrical
about the VCO free running frequency, since any control
voltage will only be able to tune the VCO in one direction if the
tuning voltage is already at the max or min.
This effect can be avoided by driving the RF input
differentially or achieving good common mode rejection to the
VCO signal.
The lock range is independant of the above effects and
will be symmetric about the centre of the phase detector Scurve provided the VCO is correctly aligned.
EXAMPLE
Loop out of lock
Tuning voltage =4.3V (maximum)
frequency =520MHz (maximum
It is only possible to capture signals below this frequency since
the VCO is already at its maximum frequency.
Testing of capture range should be done with the device
operating under normal conditions. An input signal of between
-35dBm to -10dBm is suitable for such a measurement.
9
SP1461SA
Advance Information
Lock range
Lock range should be symmetric about the centre of the
S-curve. When the oscillator is sitting in the centre of the
S-curve, the two video outputs will be at the same DC voltage.
RF oscillator design
The standard application circuit for the SL1461SA is
shown in Fig.3 The layout of the VCO tank should follow
normal good RF techniques - ie as compact as possible. This
will minimise parasitics, thus giving improved VCO linearity
and stability. The PCB layout used for testing purpose is
shown in Fig. 10.
Setting up of oscillator
The VCO should be set up so that the desired input RF
frequency is at the centre of the lock range. This will coincide
with the centre of the S-curve and the point at which the AFC
toggles when set to zero deadband.
10
The easiest way to centralise the VCO is to input an RF
carrier which is being modulated by a low frequency
squarewave. The tuning coil(s) should be adjusted until the
AFC voltage toggles between 0.2V and VCC-0.7V. The smaller
the FM deviation of the squarewave used, the more accurate
the setting will be.
A pre-emphasised video input containing black to white
transitions can also be used for this setting, since the DC
content in a pre-emphased video is much less than that in non
pre–emphasised video. This is important as any dc content in
the input waveform will introduce an offset in the AFC transition point.
The setting can be confirmed by measuring the DC
voltage on the two video outputs, the voltages should be the
same when the oscillator is centred around the incoming
frequency. This DC measurement must be carried out with an
unmodulated carrier of the required frequency. Modulation
must not be present, since by definition, the dc voltages would
be changing, thus making accurate measurement difficult.
Advance Information
SL1461SA
Fig.10 Layout of demo board with component locations
11
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