SP5655 2·7GHz Bidirectional I2C Bus Controlled Synthesiser Advance Information Supersedes July 1996 version, DS3743-4.3 DS3743 - 5.0 June 1998 The SP5655 is a single chip frequency synthesiser designed for TV tuning systems. Control data is entered in the standard I2C BUS format. The device contains 2 addressable current limited outputs and 4 addressable bidirectional open-collector ports, one of which is a 3-bit ADC. The information on these ports can be read via the I2C BUS. the device has one fixed I 2 C BUS address and 3 programmable addresses, programmed by applying a specific input voltage to one of the current limited outputs. This enables two or more synthesisers to be used in a system. FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ CHARGE PUMP 1 16 DRIVE OUTPUT CRYSTAL Q1 2 15 VEE CRYSTAL Q2 3 14 RF INPUT SDA 4 13 RF INPUT SCL 5 12 VCC † I/O PORT P7 6 11 * I/O PORT P6 7 10 † I/O PORT P5 8 9 P0 OUTPUT PORT P3 OUTPUT PORT/ ADD SELECT I/O PORT P4 † SP5655 MP16 Complete 2·7GHz Single Chip System † = Logic level I/O port * = 3-bit ADC input High Sensitivity RF Inputs Programmable via I2C BUS Low Power Consumption (5V, 30mA) Fig. 1 Pin connections – top view Low Radiation Phase Lock Detector Varactor Drive Amp Disable 6 Controllable Outputs, 4 Bidirectional 5-Level ADC Variable I2C BUS Address for Multi-tuner Applications ESD Protection: 4kV, Mil-Std-883C, Method 3015 (1) ■ High IF Cable Tuning Systems THERMAL DATA Switchable 4512/1024 Reference Divider Pin and Function Compatible with SP5055S APPLICATIONS ■ Satellite TV (2) uJC = 41°C/W uJA = 111°C/W (1) Normal ESD handling precautions should be observed. ORDERING INFORMATION (2) The SP5055S does not have a switchable reference division ratio. SP5655 KG/MPAS (Tubes) SP5655S KG/MPAD (Tape and reel) SP5655 ELECTRICAL CHARACTERISTICS TAMB = 220°C to 180°C, VCC = 14·5V to 15·5V, reference frequency = 4MHz. These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Value Characteristic Units Pin Min. Supply current Prescaler input voltage 12 13,14 Prescaler input impedance Prescaler input capacitance 13,14 13, 14 SDA, SCL Input high voltage Input low voltage Input high current Input low current Leakage current SDA Output voltage Charge pump current low Charge pump current high Charge pump output leakage current Charge pump drive output current Charge pump amplifier gain Recommended crystal series resistance Crystal oscillator drive level Crystal oscillator negative resistance External reference input frequency External reference input amplitude 4,5 4,5 4,5 4,5 4,5 Typ. Max. 30 40 300 50 4 1 1 1 16 5·5 1·5 10 210 10 V V µA µA µA Input voltage = VCC Input voltage = 0V When VCC = 0V 0·4 V Sink current = 3mA µA µA nA µA Byte 4, bit 2 = 0, pin 1 = 2V Byte 4, bit 2 = 1, pin 1 = 2V Byte 4, bit 4 = 1, pin 1 = 2V V pin 16 = 0·7V 650 6170 65 500 6400 10 2 2 2 2 Output Ports P0, P3 sink current P0, P3 leakage current P4-P7 sink current P4-P7 leakage current 11, 10 11, 10 9-6 9-6 Input Ports P3 input current high P3 input current low P4, P5, P7 input voltage low P4, P5, P7 input voltage high P6 input current high P6 input current low 10 10 9,8,6 9,8,6 7 7 750 2 70 0·7 200 80 1000 8 200 1 1·5 10 10 10 110 210 0·8 2·7 NOTES 1. Maximum power consumption is 220mW with VCC = 5·5V and all ports off. 2. Resistance specified is maximum under all conditions. 2 VCC = 4·5V to 5·5V (note 1) mA mVrms 120MHz to 2·7GHz sinewave, see Fig. 5 Ω pF 50 2 3 0 Conditions 110 210 Ω Parallel resonant crystal (note 2) mV p-p Ω MHz AC coupled sinewave mVrms AC coupled sinewave mA µA mA µA VOUT = 12V VOUT = 13·2V VOUT = 0·7V VOUT = 13·2V µA µA V V µA µA V pin 10 = VCC V pin 10 = 0V See Table 3 for ADC levels SP5655 ABSOLUTE MAXIMUM RATINGS All voltages are referred to VEE and pin 3 at 0V Value Pin Parameter Supply voltage 12 Units Min. Max. 20·3 7 V 2·5 V p-p Conditions RF input voltage 13,14 Port voltage 6-11 20·3 14 V Port in off state 6-9 20·3 6 V Port in on state 10, 11 20·3 14 V Port in on state 50 mA Total port output current 6-9 Address select voltage 10 20·3 VCC10·3 V 13-14 20·3 VCC10·3 V Charge pump DC offset 1 20·3 VCC10·3 V Drive output DC offset 16 20·3 VCC10·3 V Crystal oscillator DC offset 2 20·3 VCC10·3 V 4,5 20·3 6 V 255 1150 °C 1150 °C RF input DC offset SDA, SCL input voltage Storage temperature Junction temperature 13 RF IN OSC PREAMP PRESCALER 416 14 FPD 15-BIT PROGRAMMABLE DIVIDER PHASE COMP FCOMP F DIVIDER 4512/1024 LOCK DET CHARGE PUMP SDA 4 I 2C BUS TRANSCEIVER ADDRESS SELECT 3-BIT ADC CONTROL DATA LATCHES AND CONTROL LOGIC LEVEL 3 TTL COMP 6-BIT LATCH PORT INFO 16 CP TO DRIVE/ VARICAP OUT OS 4 PORT OUTPUT DRIVERS VCC 15 11 CHARGE PUMP 4 2 P0 CRYSTAL UP FL 5 Q2 DN POR SCL Q1 3 1 15-BIT LATCH DIVIDE RATIO POWER ON DET 2 10 P3 9 8 7 6 P4 P5 P6 P7 VEE Fig. 2 Block diagram 3 SP5655 FUNCTIONAL DESCRIPTION The SP5655 is programmed from an I2C Bus. Data and Clock are fed in on the SDA and SCL lines respectively, as defined by the I2C Bus format. The synthesiser can either accept new data (write mode) or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is low and read mode if it is high. The Tables in Fig. 3 illustrate the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one synthesiser in an I2C Bus system. Table 4 shows how the address is selected by applying a voltage to P3. When the device receives a correct address byte, it pulls the SDA line low during the acknowledge period, and during following acknowledge periods after further data bytes are programmed. When the device is programmed into the read mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an internal STOP condition, which inhibits further reading. WRITE Mode (Frequency Synthesis) When the device is in write mode bytes 2 and 3 select the synthesised frequency, while bytes 4 and 5 control the output port states, charge pump, reference divider ratio and various test modes. Once the correct address is received and acknowledged, the first bit of the next byte determines whether that byte is interpreted as byte 2 or 4; a logic 0 for frequency information and a logic 1 for control and output port information. When byte 2 is received the device always expects byte 3 next. Similarly, when byte 4 is received the device expects byte 5 next. Additional data bytes can be entered without the need to readdress the device until an I2C stop condition is recognised. This allows a smooth frequency sweep for fine tuning or AFC purposes. If the transmission of data is stopped mid-byte (for example, by another device on the bus) then the previously programmed byte is maintained. Frequency data from bytes 2 and 3 are stored in a 15-bit register and used to control the division ratio of the 15-bit programmable divider. This is preceded by a divide-by-16 prescaler and amplifier to give excellent sensitivity at the local oscillator input, see Fig. 5. The input impedance is shown in Fig. 7. The programmed frequency can be calculated by multiplying the programmed division ratio by 16 times the comparison frequency FCOMP. When frequency data is entered, the phase comparator, via a charge pump and varicap drive amplifier, adjusts the local oscillator control voltage until the output of the programmable divider is frequency and phased locked to the comparison frequency. The reference frequency may be generated by an external source capacitively coupled into pin 2, or provided by an onchip crystal controlled oscillator. The comparison frequency FCOMP is derived from the reference frequency via the reference divider. The reference divider division ratio is switchable 4 from 512 to 1024, and is controlled by bit 7 of byte 4 (TS0); a logic 1 to 512, a logic 0 for 1024. The SP5655 differs from the SP5055 in this respect, only 512 being available on the SP5055. Note that the comparison frequency is 7·8125kHz when a 4MHz reference is used, and divide by 512 is selected. Bit 2 of byte 4 of the programming data (CP) controls the current in the charge pump circuit, a logic 1 for ±170µA and a logic 0 for ±50µA, allowing compensation for the variable tuning slope of the tuner and also to enable fast channel changes over the full band. When the device is frequency locked, the charge pump current is internally set to ±50µA regardless of CP. Bit 4 of byte 4 (T0) disables the charge pump when it is set to a logic 1. Bit 8 of byte 4 (OS) switches the charge pump drive amplifier’s output off when it is set to a logic 1. Bit 3 of byte 4 (T1) enables various test modes when set high. These modes are selected by bits 5, 6 and 7 of byte 4 (TS2, and TS1, TS0) as detailed in Table 5. When T1 is set low, TS2 and TS1 are assigned a ‘don’t care’ condition, and TS0 selects the reference divider ratio as previously described. Byte 5 programs the output ports P0 and P3 to P7; a logic 0 for a high impedance output and a logic 1 for low impedance (on). READ Mode When the device is in read mode the status byte read from the device on the SDA line takes the form shown in Table 2. Bit 1 (POR) is the power-on reset indicator and is set to a logic 1 if the VCC supply to the device has dropped below 3V (at 25˚C), for example, when the device is initially turned on. The POR is reset to 0 when the read sequence is terminated by a stop command. When POR is set high (at low VCC), the programmed information is lost and the output ports are all set to high impedance. Bit 2 (FL) indicates whether the device is phase locked, a logic 1 is present if the device is locked, and a logic 0 if the device is unlocked. Bits 3, 4 and 5 (I2, I1, I0) show the status of the I/O Ports P7, P5 and P4 respectively. A logic 0 indicates a low level and a logic 1 a high level. If the ports are to be used as inputs they should be programmed to a high impedance state (logic 1). These inputs will then respond to data complying with TTL type voltage levels. Bits 6, 7 and 8 (A2, A1, A0) combine to give the output of the 5-level ADC. The ADC can be used to feed AFC information to the microprocessor from the IF section of the receiver, as illustrated in the typical application circuit. APPLICATION A typical application is shown in Fig. 4. All input/output interface circuits are shown in Fig. 6. The SP5655 is function and pin equivalent to the SP5055 device apart from the switchable reference divider, and has much lower power dissipation, improved RF sensitivity and better ESD performance. SP5655 MSB Address LSB 1 1 0 0 0 Programmable divider 0 14 13 12 11 Programmable divider 2 7 26 25 24 Charge pump and test bits 1 CP T1 T0 P7 P6 P5 P4 I/O port control bits 2 2 2 2 23 0 A Byte 1 2 8 A Byte 2 2 0 A Byte 3 A Byte 4 P0 A Byte 5 1 A Byte 1 A0 A Byte 2 MA1 MA0 2 10 22 2 9 21 TS2 TS1 TS0 OS P3 X X Table 1 Write data format (MSB transmitted first) Address 1 Status byte 1 POR FL 0 0 0 I2 I1 I0 MA1 MA0 A2 A1 Table 2 Read data format A2 A1 A0 Voltage input to P6 1 0 0 0·6VCC to 13·2V 0 1 1 0·45VCC to 0·6VCC 0 0 0V to 0·2VCC 0 1 0 0·3VCC to 0·45VCC 0 1 Always valid 0 0 1 0·15VCC to 0·3VCC 1 0 0·3VCC to 0·7VCC 0 0 0 0V to 0·15VCC 1 1 0·8VCC to 13·2V Table 3 ADC levels T1 MA1 MA0 Address select input voltage Table 4 Address selection TS2 TS1 TS0 Operation mode description 0 X X 0 Normal operation, test modes disabled, reference divider ratio = 1024 0 X X 1 Normal operation, test modes disabled, reference divider ratio = 512 1 0 0 X Charge pump source (down). Status bit FL set to 0 1 0 1 X Charge pump sink (up). Status bit FL set to 1 1 1 0 0 Ports P4, P5, P6, P7set to state X 1 1 0 1 Port P7 = FPD/2; P4, P5, P6 set to state X 1 1 1 X Port P7 = FPD; P6 = FCOMP; P4, P5 set to state X Table 5 Operation modes NOTES X = don’t care For further details of test modes, see Table 6 A MA1, MA0 CP T1 T0 TS2, TS1, TS0 OS P7, P6, P5, P4, P3, P0 POR FL I2, I1, I0 A2, A1, A0 X : : : : : : : : : : : : : Acknowledge bit Variable address bits (see Table 4) Charge Pump current select Test mode selection Charge pump disable Operation mode control bits (see Table 5) Varactor drive Output disable Switch Control output port states Power On Reset indicator Phase lock detect flag Digital information from ports P7, P5 and P4 respectively 5-level ADC data from P6 (see Table 3) Don’t care Fig. 3 Data formats 5 SP5655 112V 112V IF SECTION IF SIGNAL AFC OUT P4 SATELLITE TUNER 9 8 P3 10 7 P0 11 6 P5 P6 15V P7 15V SP5655 0·1µ OSCILLATOR OUTPUT SCL 5 12 1n 13 4 14 3 15 2 16 1 I 2C BUS SDA 4MHz CRYSTAL 1n 130V 47k 10k 18p 39n 22k VARICAP INPUT CONTROL MICRO 180n VT 22k 10n BCW31 Fig. 4 Typical application VIN (mV RMS INTO 50 Ω ) 300 150 OPERATING WINDOW 100 50 120 1000 2000 FREQUENCY (MHz) Fig. 5 Typical input sensitivity 6 2700 3000 3500 SP5655 VCC VREF 400 CHARGE PUMP 400 RF INPUTS 150 DRIVE OUTPUT OS (O/P DISABLE) Loop amplifier RF input VCC VCC 67k 3k SCL/SDA CRYSTAL Q1 * ACK CRYSTAL Q2 * ON SDA ONLY SCL and SDA inputs Reference oscillator VCC VCC PORT P3 ONLY 3k PORT 3k 12k PORT Ports P0-P3 Ports P7-P4 Fig. 6 SP5655 input/output interface circuits 7 SP5655 j1 j 0.5 j2 j 0.2 j5 0.5 0.2 0 1 5 2 2·6GHz 2j 5 2j 0.2 S11:ZO = 50Ω NORMALISED TO 50Ω 2j 2 2j 0.5 FREQUENCY MARKER STEP = 500MHz 2j 1 Fig. 7 Typical input impedance, APPLICATION NOTES The board can be used for the following purposes: (A) Measuring RF sensitivity perfomance (B) Indicating port function (C) Synthesising a voltage controlled oscillator (D)Testing external reference sources The programming codes relevant to these tests are given in Table 6. An application note, AN168, is available for designing with synthesisers such as the SP5655. It covers aspects such as loop filter design, decoupling and I2C bus radiation problems. The application note is published in the Mitel Semiconductor Media IC Handbook. A generic test/demonstration board has been produced, which can be used for the SP5655. A circuit diagram and layout for the board are shown in Figs. 8 and 9. EXTERNAL REFERENCE 15V SK2 15V R11 3k S1 C7 100n 112V C8 100n C9 100n C3 47n C6 10n (NOT FITTED, SEE NOTE) S2 130V P2 C2 220n R8 22k R9 10k R10 47k P3 R7 22k X1 4MHz R12 1k C1 18p TP1 DATA/SDA 1 16 2 15 3 14 4 13 VAR C5 1n 5 12 6 11 7 10 8 9 R14 22k 15V R13 12k C10 1n ENABLE/ADDRESS SEL P1 D3 7 D4 8 R6 4·7k R5 4·7k D2 R4 4·7k R2 4·7k D1 PIN NO. 6 R3 4·7k R1 4·7k P4 NOTE To use an external reference, capacitor C6 must be fitted and capacitor C1 removed from the board. D5 9 112V D6 10 11 C11 1n Fig. 8 Test board circuit 8 112V TR2 2N3906 CLOCK/SCL C13 100p SK1 RFINPUT C4 1n SP5655 C12 100p GND C14 10n TR1 2N3904 SP5655 TP1 = PIN 3 DC BIAS Top view (ground plane) Underside (surface mounted components side) NOTES 1. CIRCUIT SCHEMATIC IS SHOWN IN FIG. 8 2. ALL SUFACE MOUNT COMPONENTS ARE MOUNTED ON UNDERSIDE OF BOARD Fig. 9 Test board layout 9 SP5655 TEST MODES As explained in the functional description, The SP5655 can be programmed into a numb er of test modes. These are invoked by programming Hex codes into byte 4, those most commonly used being shown in Table 6. Other codes will also apply due to don’t care conditions, which are assumed to be 1 in the Table. NOTE: When looking at FPD or FCOMP signals from ports P7 and P6. byte should be sent twice, first to set the desired reference division ratio then to switch on the chosen test mode. The pulses can then be measured by simply connecting an oscilloscope or counter to the relevant output pin on the test board. Hex code (byte 4) Operation mode description CP high mode CP low mode Normal operation, reference divider ratio = 1024 CC 8C Normal operation, reference divider ratio = 512 CE 8E Charge pump source (down), FL set to 0 E2 A2 Charge pump sink (up), FL set to 1 E6 A6 Port P7 = FPD/2 EA AA Port P7 = FPD, P6 = FCOMP EE AE Charge pump disable, reference divider ratio = 512 DE 9E Varactor line disable, reference divider ratio = 512 CF 8F Charge pump and varactor line disable, reference divider ratio = 512 DF 9F Table 5 Operation modes 10 http://www.mitelsemi.com World Headquarters - Canada Tel: +1 (613) 592 2122 Fax: +1 (613) 592 6909 North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 Asia/Pacific Tel: +65 333 6193 Fax: +65 333 6192 Europe, Middle East, and Africa (EMEA) Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. However, Mitel assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Mitel or licensed from third parties by Mitel, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Mitel, or non-Mitel furnished goods or services may infringe patents or other intellectual property rights owned by Mitel. This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Mitel’s conditions of sale which are available on request. M Mitel (design) and ST-BUS are registered trademarks of MITEL Corporation Mitel Semiconductor is an ISO 9001 Registered Company Copyright 1999 MITEL Corporation All Rights Reserved Printed in CANADA TECHNICAL DOCUMENTATION - NOT FOR RESALE