Obsolescence Notice This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ SP8852D PACKAGE DETAILS Dimensions are shown thus: mm (in). For further package information please contact your local Customer Service Centre. 17.27/17.78 (0.680/0.700) 12.45/12.95 (0.490/0.510) 45° AT 3 PLACES 1.02MM/(0.040 )NOM 15.49/16.51 (0.610/0.650) 0.43MM(0.017 ″) INDEX CORNER 0.76MM(0.030 ″) 17.27/17.78 (0.680/0.700) 1.27/(0.050) NOM 16.33/16.81 (0.643/0.662) 0.51 (0.02) NOM AT 45° 12.45/12.95 (0.490/0.510) 16.33/16.81 (0.643/0.662) 0.89(0.035) 03.05/3.43 (0.120/0.135) HC44 MULTILAYER CERAMIC J LEADED CHIP CARRIER HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire United Kingdom SN2 2QW. Tel: (01793) 518000 Fax: (01793) 518411 GEC PLESSEY SEMICONDUCTORS P.O. Box 660017 1500 Green Hills Road, Scotts Valley, California 95067–0017, United States of America. Tel: (408) 438 2900 Fax: (408) 438 5576 CUSTOMER SERVICE CENTRES FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 69 18 90 00 GERMANY Munich Tel: (089) 3609 06 0 Fax: (089) 3609 06 55 ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993 JAPAN Tokyo Tel: (03) 5276–5501 Fax: (03) 5276–5510 NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023 SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872 SWEDEN Stockholm Tel: 46 8 7029770 Fax: 46 8 6404736 TAIWAN, ROC Taipei Tel: 886 2 5461260 Fax: 886 2 7190260 UK, EIRE, DENMARK, FINLAND & NORWAY Swindon Tel: (01793) 518527/518566 Fax: (01793) 518582 These are supported by Agents and Distributors in major countries world–wide. GEC Plessey Semiconductors 1995 Publication No. D.S. 3700 Issue No. 2.5 September 1995 TECHNICAL DOCUMENTATION – NOT FOR RESALE. PRINTED IN UNITED KINGDOM This publication is issued to provide information only, which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior notice the specification, design, or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company’s conditions of sale, which are available on request. C1 FROM CHARGE PUMP K K R2 TO VCO + FROM CHARGE PUMP REFERENCE t2 + w 12t n 3 t3 + 3 )w )w 1 1 n 2 – ƪ t1 + Nfw 20 1 C2 n 2 2 n * tan F ) cosF t2 2 t3 2 ƫ SP8852D Ă½ 1 0 wn 0 From equation 3: + Fig. 8 Third order loop filter circuit diagram * tan 45° ) cos145° 3 100kHz + 659 + (100kHz + 3 . 844 1 1 n n 2 2 2 ń 10MHz V [ A] 100kHz)2 2 2 ½ Ă Now 62832 39 . 48Ă 2 (659 x 10 ƪ ƫ *9) 2 ½ 6 . 833 10 12 1 . 1714 1 + 1 . 59 10*9 x 2 . 415 1 + 3 . 84 10*9 1 + C1 N C1 + 3 . 84nF 2 + R2 (C1 ) C2) 3 + C 2 R 2 ƪ)ƫN Substituting for C2 2 + R2 C1 N + * + + 829 2 R2 3 3 R2 3 . 844 C1 R2 2 + R 2 C 1 ) 3 10 * 9 . 61 6 * 659 10 * 10 9 . 4 C2 (3 . 844 x 10 *6) 2 100kHz) 3 1 + Calculate values for a loop with the following parameters 100kHz) 1 2 EXAMPLE 1000MHz 10MHz 1000MHz/10MHz = 100 100kHz 2 x 10MHz/Volt 45° 6.3mA (2 )w ) (2p ) w + 1 ) (2p mA/radian These values can now be substituted in equation 1 to obtain a value for C1 and equation 2 and 3 used to determine values for C2 and R2 *3 Where A is : K Phase comparator current setting / 2 1 x 10 100 10 *9 659 10 *6 2 1+ Using these values in equation 1: The equations are; Where; K is the phase detector gain factor in mA/radian K0 is the VCO gain factor in radian/second/Volt N is the total division ratio from VCO to reference frequency n is the natural loop bandwidth 0 is the phase margin normally set to 45° Since the phase detector is linear over a range of 2 radian, K can be calculated from The phase detector gain factor K = 6.3mA/2 = 1mA/radian 1 2 )2 2 1 = C 1 2 = R2 (C1 + C2) 3 = C2 R2 . 4142 + 0628319 From equation 2: Generally the third order filter configuration shown in Fig.8 gives better results than the more commonly used second order because the reference sidebands are reduced. Three equations are required to determine values for the three constants where; Frequency to be synthesised: Reference frequency Division ratio n natural loop frequency K0 VCO gain factor 0 phase margin Phase comparator current 10 *9 3 Loop Filter Design 2 3 + C 2ĂR 2Ă + 0 . 794 nF N + + Ă C2 3 R2 659 10 829 . 4 * 9 * 9 2 SP8852D pulses which can be directly connected to the loop amplifer. The magnitude of the current and therefore the phase detector gain can be modified when new frequency data is entered to compensate for change in the VCO gain characteristic over its frequency band. The charge pump pulse current is determined by the current fed into pin 19 and is approximately equal to pin 19 current when the programmed multiplication ratio is one. The circuit diagram Fig. 7e shows the internal components on pin 19 which mirror the input current into the charge pump. The voltage at pin 19 will be approximately 1.6V above ground due to two Vbe drops in the current mirror. This voltage will exhibit a negative temperature coefficient, causing the charge pump current to change with chip temperature by up to 10% over the full military temperature range if the current programming resistor is connected to VCC as shown in the application diagram Fig. 5. In critical applications where this change in charge pump current would be too large the resistor to pin 19 could be increased in value and connected to a higher supply to reduce the effect of Vbe variation on the current level. A suitable resistor connected to a 30V supply would reduce the variation in pin 19 current due to temperature to less than 1.5%. Alternatively a stable current source could be used to set pin 19 current. The charge pump output on pin 20 will only produce symmetrical up and down currents if the voltage is equal to that on the voltage reference pin 21. In order to ensure that this voltage relationship is maintained, an operational amplifier must be used as shown in the typical application Fig. 5. Using this configuration pin 20 voltage will be forced to be equal to that on pin 21 since the operational amplifier differential input voltage will be no more than a few millivolts (the input offset voltage of the amplifier). When the synthesiser is first switched on or when a frequency outside the VCO range is programmed the amplifier output will limit, allowing pin 20 voltage to differ from that on pin 21. As soon as an achievable frequency value is programmed and the amplifer output starts to slew the correct voltage relationship between pin 20 and 21 will be restored. Because of the importance of voltage equality between the charge pump reference and output pins, a resistor should never be connected in series with the operational amplifier inverting input and pin 20 as is the case with a phase detector giving voltage outputs. Any current drawn from the charge pump reference pin should be limited to the few micro amps input current of a typical operational amplifier. A resistor between the charge pump reference and the non inverting input could be added to provide isolation but the value should not be so high that more than a few millivolts drop are produced by the amplifier input current. When selecting a suitable amplifer for the loop filter, a number of parameters are important; input offset voltage in most designs is only a few milivolts and an offset of 5mV will produce a mismatch in the up and down currents of about 4% with the charge pump multiplication factor set at 1. The mismatch in up down currents caused by input offset voltage will be reduced in proportion to the charge pump multiplication factor in use. If the linearity of the phase detector about the normal phase locked operating point is critical, the input offset voltage of most amplifiers can be adjusted to near zero by means of a potentiometer. The charge pump reference voltage on pin 21 is about 1.3V below the positive supply and will change with temperature and with the programmed charge pump multiplication factor. In many cases it is convenient to operate the amplifier with the negative power supply pin connected to 0V as this removes the need for an additional power supply. The amplifier selected must have a common mode range to within 3.4V (minimum charge pump reference voltage) of the negative supply pin to operate correctly without a negative supply. Most popular amplifiers can be operated from a 30V positive supply to give a wide VCO voltage drive range and have adequate common mode range to operate with inputs at +3.4V with respect to the negative supply. Input bias and offset current levels to most operational amplifiers are unlikely to be high enough to significantly affect the accuracy of the charge pump circuit currents but the bias current can be important in reducing reference side bands and local oscillator drift during frequency changes. When the loop is locked, the charge pump produces only very narrow pulses of sufficient width to make up for any charge lost from the loop filter components during the reference cycle. The charge lost will be due to leakage from the charge pump output pin and to the amplifier input bias current, the latter usually being more significant. The result of the lost charge is a sawtooth ripple on the VCO control line which frequency modulates the phase locked oscillator at the reference frequency and its harmonics. A similar effect will occur whenever the strobe input is taken high during a programming sequence. In this case the charge pump is disabled when the strobe input is high and any leakage current will cause the oscillator to drift off frequency. To reduce this effect, the duration of the strobe pulse should be minimised. Fpd and Fref outputs These outputs provide access to the outputs from the RF and reference dividers and are provided for monitoring purposes during product development or test, and for connection of an external phase detector if required. The output circuit is of ECL type, the circuit diagram being shown in Fig. 7g. The outputs can be enabled or disabled under software control by the address 0 control word but are best left in the disabled state when not required as the fast edge speeds on the output can increase the level of reference sidebands on the synthesised oscillator. The emitter follower outputs have no internal down resistor to save current and if the outputs are required an external pull down resistor should be fitted.The value should be kept as high as possible to reduce supply current, about 2.2k being suitable for monitoring with a high impedance oscilloscope probe or for driving an AC coupled 50ohm load. A minimum value for the pull down resistor is 330ohms. When the Fpd and Fref outputs are disabled the output level will be at the logic low level of about 3.5V so that the additional supply current due to the load resistors will be present even when the outputs are disabled. Reference input The reference input circuit functions as an input amplifier or crystal oscillator. When an external reference signal is used this is simply AC coupled to pin 28, the base of the input emitter follower. When a low phase noise synthesiser is required the reference signal is critical since any noise present here will be multiplied by the loop. To obtain the lowest possible phase noise from the SP8852D it is best to use the highest possible reference input frequency and to divide this down internally to obtain the required frequency at the phase detector. The amplitude of the reference input is also important, and a level close to the maximum will give the lowest noise. When the use of a low reference input frequency say 4–10MHz is essential some advantage may be gained by using a limiting amplifier such as a CMOS gate to square up the reference input. In cases where a suitable reference signal is not available, it may be more convenient to use the input buffer as a crystal oscillator in this case the emitter follower input transistor is connected as a colpitts oscillator with the crystal connected from the base to ground and with the feedback necessary for oscillation provided by a capacitor tap at the emitter. The arrangement is shown inset in Fig. 5 . SP8852D VCC 296 VCC 3k 296 3k 296 24, 25 Fpd, Fref OUTPUTS 3.3mA OSCILLATOR OSCILLATOR CAPACITOR CRYSTAL 40k 40k 28 27 60k 60k 0V 50mA 100mA Fig. 7g Fpd and Fref outputs 50mA 100mA 100mA 0V Fig. 7h Reference oscillator Fig. 7 Interface circuit diagrams (cont) APPLICATIONS RF layout The SP8852D can operate with input frequencies up to 1.7GHz but to obtain optimum performance, good RF layout practices should be used. A suitable layout technique is to use double sided printed circuit board with through plated holes. Wherever possible the top surface on which the SP8852D is mounted should be left as a continuous sheet of copper to form a low impedance earth plane. The ground pins 12 and 16 should be connected directly to the earth plane. Pins such as VCC and the unused RF input should be decoupled with chip capacitors mounted as close to the device pin as possible with a direct connection to the earth plane, suitable values are 10nF for the power supplies and <1nF for the RF input pin.(a lower value should be used sufficient to give good decoupleing at the RF frequnecy of operation). A larger decoupling capacitor mounted as close as possible to pin 26 should be used to prevent modulation of VCC by the charge pump pulses. The Rset resistor should also be mounted close to the Rset pin to prevent noise pickup, and the capacitor connected from the charge pump output should be a chip component with short connections to the SP8852D. When the reference is derived from a crystal connected to pins 27 and 28 as shown in Fig. 5 the oscillator components are best mounted close to the SP8852D. All signals such as the programming inputs, RF in, reference in and the connections to the op–amp are best taken through the pc board adjacent to the SP8852D with through plated holes allowing connections to remote points without fragmenting the earth plane. Programming bus The input pins are designed to be compatible with TTL or CMOS logic with a switching threshold set at about 2.4V by three forward biased base emitter diodes. The inputs will be taken high by an internal pull up resistor if left open circuit but for best noise immunity it is better to connect unused inputs directly to VCC or ground. using a chip capacitor. The remaining input should be decoupled to ground, again using a chip capacitor. The inputs can be driven differentially but the input circuit should not provide a DC path between inputs or to ground. Lock detect circuit The lock detect circuit uses the up and down correction pulses from the phase detector to determine whether the loop is in or out of lock. When the loop is locked, both up and down pulses are very narrow compared to the reference frequency, but the pulse width in the out of lock condition continuously varies, depending on the phase difference between the outputs of the reference and RF counters. The logical AND of the up and down pulses is used to switch a 20mA current sink to pin 18 and a 50k resistor provides a load to VCC. The circuit is shown in Fig. 7c. When lock is established, the narrow pulses from the phase detector ensure that the current source is off for the majority of the time and so pin 18 will be pulled high by the 50k resistor. A voltage comparator with a switching threshold at about 4.7V monitors the voltage at pin 18 and switches pin 17 low when pin 18 is more positive than the 4.7V threshold. When the loop is unlocked, the frequency difference at the counter outputs will produce a cyclic change in pulse width from the phase detector outputs with a frequency equal to the difference in frequency at the reference and RF counter outputs. A small capacitor connected to pin 18 prevents the indication of false phase lock conditions at pin 17 for momentary phase coincidence. Because of the variable width pulse nature of the signal at pin 18 the calculation of a suitable capacitor value is complex, but if an indication with a delay amounting to several times the expected lock up time is acceptable, the delay will be approximately equal to the time constant of the capacitor on pin 18 and the internal 50k resistor. If a faster indication is required, comparable with the loop lock up time, the capacitor will need to be 2–3 times smaller than the time constant calculation suggests. The time to respond to an out of lock condition is 2–3 times less than that required to indicate lock. RF inputs The prescaler has a differential input amplifer to improve input sensitivity. Generally the input drive will be single ended and the RF signal should be AC coupled to either of the inputs Charge pump circuit The charge pump circuit converts the variable width up and down pulses from the phase detector into adjustable current SP8852D VCC VCC 4k 40k 40k 5k 5k 325 325 RF INPUT 13 500 INPUT RF INPUT 500 14 50mA 3mA 0V 3k 0V Fig. 7a 16 bit input bus, strobe and address Fig. 7b RF inputs C–LOCK DETECT (HIGH WHEN LOCKED) VCC 18 VCC 50k 3k 2k5 2k5 3k LOW WHEN LOCKED VREF 4.7V 3k 3k 17 LOCK DETECT OUTPUT 400mA 100mA 20mA 100 1k 100 11 0V 0V Fig. 7c Lock detect decouple Fig. 7d Lock detect output CHARGE PUMP OUTPUT REFERENCE Rset VCC 20 19 21 450 450 VCC CHARGE PUMP CURRENT SOURCES UP 83 83 VCC DOWN 130 2mA Fig. 7e Rset pin. Fig. 7f Charge pump circuit Fig. 7 Interface circuit diagrams SP8852D Bit 15 Bit 14 Current Multiplication Factor 0 0 1.0 0 1 1.5 1 0 2.5 1 1 4.0 Table 1 Bit 11 Bit 10 Phase Detector State 0 0 Phase detector enable Fpd/Fref outputs off 0 1 Phase detector enable Fpd/Fref outputs on 1 0 Phase detector disable by lock detect Fpd/Fref outputs on 1 1 Phase detector disabled Fpd/Fref outputs on Table 3 ] V *R 1 . 6V Phase detector gain + cc Pin 19 current set Ipin 19(mA) ń multiplication factor mA radian 2p To allow for control direction changes introduced by the design of the PLL, bit 12 on the input bus address 0 can be programmed to reverse the sense of the phase detector by transposing the Fpd and Fref connections. In order that any external phase detector will also be reversed by this programming bit, the Fpd/Fref outputs are also interchanged by bit 12 as shown in Table 2. The charge pump connections to the loop amplifier consist of the charge pump output and the charge pump reference. The matching of the charge pump up and down currents will only be maintained if the charge pump output is held at a voltage equal to the charge pump reference using an operational amplifier to produce a virtual earth condition at pin 20. The lock detect circuit can drive an LED to give visual indication of phase lock or provide an indication to the control system if a pull up resistor is used in place of the LED. A small capacitor connected from the C–lock detector pin to ground may be used to delay lock detect indication and remove glitches produced by momentary phase coincidence during lock up. PIN 40 PIN 11 BIT 15 Output for RF Phase Lag BIT 0 29 0 Sense Bit (Bit 12) Pin 20 1 Current Source 0 Current Sink ADDRESS NOT USED 27 26 25 24 23 22 21 20 TEN BIT REFERENCE COUNTER PHASE DETECTOR STATE CONTROL see Table 3 Table 2 The Fpd and Fref signals to the phase detector are available on pin 24 and 25 and may be used to monitor the frequency input to the phase detector or used in conjunction with an external phase detector. These outputs may be programmed by bits 10 and 11 of word 0 according to table 3. State 3 where the outputs are disabled by the lock detect circuit is useful where the user wishes to use an external phase detector. The internal phase/frequency detector may be used to pull the loop into lock and an automatic switch over to the external phase detector made. When the Fpd/Fref outputs are to be used at high frequencies, an external pull down resistor of minimum value 330W may be connected to ground to reduce the fall time of the output pulse. 28 PHASE DETECTOR SENSE CONTROL see Table 2 PIN 40 BIT 15 REFERENCE WORD BIT ALLOCATION 213 212 211 210 1 ADDRESS PHASE DETECTOR GAIN CONTROL see Table 1 29 28 27 26 25 PIN 11 BIT 0 24 M COUNTER RF DIVISION RATIO BIT ALLOCATION Fig. 6 Programming data format 23 22 21 20 3 BIT A COUNTER SP8852D ADDRESS STROBE 40 6 5 1k 44 43 42 41 CONTROL MICRO 4 3 2 1 +5V 7 8 9 39 38 37 36 10 11 12 13 2k2 27 31 30 29 28 * VALUES DEPEND ON APPLICATION LOOP * FILTER * * 25 26 27 28 APPLICATION USING CRYSTAL REFERENCE 21 22 23 24 1n SP8852 SP8852D 14 15 16 17 18 19 20 VCO 35 34 33 32 Fpd Fref – + 33p 100p 1n 10n 10MHz CRYSTAL * 100p 1m +30V OP27 ETC 100n 1n 10n Ref in Fig. 5 Typical application diagram DESCRIPTION Prescaler and AM counter The programmable divider chain is of A M counter construction and therefore contains a dual modulus front end prescaler, an A counter which controls the dual modulus ratio and an M counter which performs the bulk multi–modulus division. A programmable divider of this construction has a division ratio of MN+A and a minimum integer steppable division ratio of N(N–1), where N is the prescaler value. Data entry and storage Data is loaded from the 16 bit bus into one of the internal buffers by applying a positive pulse to the strobe input. The input bus can be driven from TTL or CMOS logic levels. When the strobe input is low, the inputs are isolated and the data can be changed without affecting the programmed state. The data is loaded into the RF buffer when the address input is high and into the reference buffer when low. When the strobe input is taken high, the A and M and reference counters are reset and the input data is applied to the internal storage register. When the strobe input is again taken low, the data on the input bus is stored in the selected register and the counters released. The strobe input is level triggered so that if the data is changed whilst the input is high, the final value before the strobe goes low will be stored. In order to prevent disturbances on the VCO control voltage when frequency changes are made, the strobe input disables the charge pump outputs when high. During this period the VCO control voltage will be maintained by the loop filter components around the loop amplifier, but due to the combined effects of the amplifier input current and charge pump leakage a gradual change will occur. In order to reduce the change, the duration of the strobe pulse should be minimised. Selection of a loop amplifer with low input current will reduce the VCO voltage droop during the strobe pulse and result in minimum reference sidebands from the synthesiser. Reference input The reference source can be either driven from an external sine or square wave source of up to 100MHz or a crystal can be connected as shown in Fig. 5. Phase Comparator and Charge pump The SP8852D has a digital phase/frequency comparator driving a charge pump with programmable current output. The charge pump current level at the minimum gain setting is approximately equal to the current fed into the Rset input pin 19 and can be increased by programming the bus according to Table 1 by up to 4 times. SP8852D TYPICAL OVERLOAD +20 +10 +7 GUARANTEED OPERATING WINDOW INPUT TO PIN13 (dBm) –5 –10 –20 –30 100MHz 1.7GHz 2GHz 1GHz 10GHz TYPICAL SENSITIVITY INPUT DRIVE REQUIREMENTS Fig. 3 SP8852D +j1 +j0.5 +j0.2 0 Zo=50W +j2 +j5 0.2 0.5 1 2 5 50MHz 1.1GHz 2.5GHz –j5 –j0.2 –j2 –j0.5 –j1 Fig. 4 R.F. input impedance SP8852D ELECTRICAL CHARACTERISTICS Guaranteed over the full temperature and supply voltage range (unless otherwise stated) Temperature Tamb for KG parts –55°C and +100 °C Temperature Tamb for IG parts –40°C and +85°C Supply Voltage VCC = 4.75V and 5.25V. Value Characteristics Pin Min Max 180 240 mA dBm Supply current 15, 26 RF input sensitivity 13, 14 –5.0 +7.0 13,14,24 56 16383 Reference division ratio 28, 25 1 1023 Comparison frequency 28,24,25 RF division ratio Reference input frequency 28 10 Reference input voltage 28 0 Units Typ +6 50 MHz 100 MHz +10 dBm Conditions 100MHz to 1.7GHz See Fig. 3 Reference division ratio ≥2 See Note 1 Fref/Fpd output voltage high 24, 25 –0.8 Vwrt VCC 2.2K to 0V Fref/Fpd output voltage low 24, 25 –1.4 Vwrt VCC 2.2K to 0V Lock detect output voltage 17 300 500 mV IOUT = 3mA Charge pump current at multiplication factor =1 19,20,21 "1.4 "1.5 "1.7 mA Charge pump current at multiplication factor =1.5 19,20,21 "2.0 "2.3 "2.5 Vpin 20 = Vpin 21 Ipin 19 = 1.6mA mA Charge pump current at multiplication factor =2.5 19,20,21 "3.4 "3.8 "4.1 Vpin 20 = Vpin 21 Ipin 19 = 1.6mA mA Charge pump current at multiplication factor =4.0 19,20,21 "5.4 "6.1 "6.5 Vpin 20 = Vpin 21 Ipin 19 = 1.6mA mA Vpin 20 = Vpin 21 Ipin 19 = 1.6mA Input bus high logic level 1 –11,38 39,40,44 Input bus low logic level 1–11,38 39,40–44 Input bus current source Input bus current sink 1–11,38 39,40–44 3.5 V 1 200 1–11,38 39,40–44 10 V mA VIN = 0V mA VIN = VCC % Vpin 20 = Vpin 21 Ipin 19 = 1.6mA V Ipin 19 = 1.6mA current multiplication factor 1 V Ipin 19 = 1.6mA current multiplication factor 4 Up down current matching 20 "5 Charge pump reference voltage 21 VCC – 0.5 Charge pump reference voltage 21 VCC–1.6 Rset current 19 0.5 Rset Voltage 19 1.6 V Ipin 19 = 1.6 mA C–lock detect current 18 +10 mA Vpin18=4.7V 2 mA See Note 2 Strobe pulse width 50 nS Note 3 Data set up time 100 nS Note 3 Notes: 1. lower reference frequencies may be used if slew rates are maintained. 2. Pin 19 current multiplication factor must be less than 5mA if charge pump accuracy is to be maintained.. 3. Guaranteed but not tested. SP8852D PIN DESCRIPTION PIN DESCRIPTION 1,2,3,4,5,6,7,8,9,10,11,40,41,42,43,44 These are the inputs to the 16 bit data bus. When Pin 38=HI the data goes to the buffers for the A counter, M counter and PD Gain. When Pin 38=LO the data goes to the buffers for the Ref counter and the Phase Detector State (see table 3.) Open circuit=1 (high) on these pins. Data is transparent from pins to the selected buffers when Pin 39 (strobe) is HI and frozen in buffers when Pin 39 is LO. 13, 14 (RF INPUT) Balanced inputs to the RF pre–amplifier. For single ended operation the signal is AC coupled into pin 13 with pin 14 AC decoupled to ground (or vice–versa.) Pins 13 and 14 are internally DC biased. 17 (LOCK DETECT INPUT) A current sink into this pin is enabled when the lock detect circuit indicates lock. Used to give an external indication of phase lock. 18 (C–LOCK DETECT) A capacitor connected to this point determines the lock detect integrator time constant and can be used to vary the sensitivity of the phase lock indicator. 19 (Rset) An external resistor from Pin 19 to VCC sets the charge pump output current. 20 (CP OUTPUT) The phase detector output is a single ended charge pump sourcing or sinking current to the inverting input of an external loop filter. The direction is controlled by bit 12 of the reference word. For bit 12=1 and Fpd or RF phase leads Ref phase Pin 20 will sink current. (see table 2). 21 (CP REF) Connected to the non–inverting input of the loop filter to set the optimum DC bias. 22 Not Connected. 23 Not Connected 24 =Fpd if Pin 23 is HI =Fref if Pin 23 is LO RF divider output pulses. Fpd=RF input frequency/(M.N+A). Pulse width=8 RF input cycles (1 cycle of the divide by 8 prescaler output). 25 =Fref if Pin 23 is HI =Fpd if pin 23 is LO Reference divider output pulses. Fref=Reference input frequency/R. Pulse width =high period of Ref input. 27 (Reference Oscillator. Capacitor) Leave open circuit if an external reference is used. See Fig. 5 for typical connection for use as an onboard crystal oscillator. 28 (Ref IN/XTAL) This pin is the input buffer amplifier for an external reference signal. This amplifier provides the active element if an onboard crystal oscillator is used. 29,30,31,32,33,34,35,36,37 Not Connected. 38 (Address Input) Controls which buffer the data on the input bus goes to Pin 38=HI sends data to the RF divider group of functions. Pin 38=LO sends data to the Ref divider group of functions (see Fig. 6). Open circuit = HI. 39 (Strobe) When Pin 39 is HI the A, M, and R counters are held in the reset state and the charge pump output is disabled. The data on the input bus is loaded into the buffers selected by the Address Input state (Pin 38) when Pin 39 goes low. When Pin 39 is low the data is fixed in the buffers, the buffers are loaded into the counter and control register, all the counters are active, and the charge pump is enabled. Open circuit =HI. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 ADDRESS STROBE 0V PRESCALER RF INPUT VCC +5V PRESCALER 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 38 39 12 14 13 15 INPUT INTERFACE LOAD 28 REFERENCE CRYSTAL B8/9 MODULUS CONTROL B2 B9 10 BIT REFERENCE DIVIDER B0 B13 B10 B14 Fref B12 B15 Fpd 25 24 18 PHASE DETECTOR 19 17 21 20 26 +5V V EE 0V Fref * F pd * C–LOCK DETECT Rset LOCK DET O/P CHARGE PUMP REFERENCE CHARGE PUMP OUTPUT 16 * Fpd and Fref outputs are reversed by the phase detector sense bit, bit 12. Diagram is correct when the sense bit is high REFERENCE BUFFER RF BUFFER B3 11 BIT M COUNTER Fig. 2 SP8852D block diagram 27 REFERENCE CAPACITOR LOAD B0 3 BIT A COUNTER SP8852D SEPTEMBER 1995 PRELIMINARY INFORMATION D.S. 3700 2.5 SP8852D 1.7GHz PARALLEL LOAD PROFESSIONAL SYNTHESISER The SP8852D is one of a family of parallel load synthesisers containing all the elements apart from the loop amplifier to fabricate a PLL synthesis loop. Other parts in the series are the SP8854D which has hard wired reference counter programming and requires only a single 16 bit programming word, and the SP8855D which is fully programmable using hard wired links or switches. The SP8852D is programmed using a 16 bit parallel data bus. Data can be stored in one of two internal buffers, selected by a single address bit on the input interface. In order to fully program the device, two 16 bit words are required, one to select the RF division ratio (A&M counters) and phase detector gain, and one to set the ten bit reference divider count, phase detector state and sense. Once the reference divide ratio has been set, frequency changes can be made by a single 16 bit data load entry to the RF divider chain. FEATURES 1.7GHz Operating Frequency Single 5V Supply Operation Low Power Consumption <1.3W High Comparison Frequency 20MHz High Gain Phase Detector 1mA/rad Zero ‘‘Dead Band” Phase Detector Wide Range of RF and Reference Divide Ratios Programming by Dual Word Data Transfer J J J J J J J J ABSOLUTE MAXIMUM RATINGS Supply Voltage –0.3V to 6V Storage Temperature –65°C to +150°C Operating Temperature –55°C to +100°C Prescaler & reference Input Voltage 2.5V p–p Data Inputs VCC +0.3V VEE –0.3V Junction temperature +175°C ORDERING INFORMATION SP8852D KG HCAR (non standard temperature range –55°C to +100°C standard product screening) SP8852D IG HCAR (Industrial temperature range –40°C to +85°C standard product screening) Thermal Data qJC=5°C/W qJC=53°C/W ESD: 1000V, Human body model INDEX CORNER 1 44 HC44 Pin Description Pin Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Input bus bit 10 Input bus bit 9 Input bus bit 8 Input bus bit 7 Input bus bit 6 Input bus bit 5 Input bus bit 4 Input bus bit 3 Input bus bit 2 Input bus bit 1 Input bus bit 0 0V (prescaler) RF input RF input VCC +5V (prescaler) VEE 0V Lock detect output C–lock detect Rset Charge pump output Charge pump ref. NC 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 NC Fpd* Fref* +5V Ref. osc capacitor Ref in/XTAL NC NC NC NC NC NC NC NC NC Address input Strobe Input bus bit 15 Input bus bit 14 Input bus bit 13 Input bus bit 12 Input bus bit 11 * Fpd and Fref outputs are reversed by the phase detector sense bit, bit 12 in the programming word. The table above is correct when the sense bit is high. Fig. 1 Pin connections – top view For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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