SP7653
Wide Input Voltage Range,
1.3MHz, Buck Regulator
TM
SP7653
SP7653
FEATURES
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Power Blox
DFN PACKAGE
DFN
7mmPACKAGE
x 4mm
7mm x 4mm
2.5V to 20V Step Down Achieved Using Dual Input
Output Voltage down to 0.8V
3A Output Capability
Built in Low RDSON Power Switches (40 m1 typical)
Highly Integrated Design, Minimal Components
1.3MHz Fixed Frequency Operation
UVLO Detects Both VCC and VIN
Over Temperature Protection
Short Circuit Protection with Auto-Restart
Wide BW Amp Allows Type II or III Compensation
Programmable Soft Start
Fast Transient Response
High Efficiency: Greater than 95% Possible
Asynchronous Start-Up into a Pre-Charged Output
Small 7mm x 4mm DFN Package
U.S. Patent #6,922,041
26
PLX
GND 1
LX 25
PGND 2
LX 24
PGND 3
LX 23
GND 4
22
VCC
VFB 5
GND 21
COMP 6
20
GND
UVIN 7
BOTTOM VIEW
BOTTOM VIEW
Heatsink Pad 1
Heatsink
Pad
Connect to
Lx1
Connect to Lx
Heatsink Pad 2
Heatsink
2
Connect
topad
GND
Connect to GND
19
GND
GND 8
BSTSS18
9
NC 17
VIN 10
Heatsink Pad 3
Connect to VIN
Heatsink pad 3
Connect to VIN
LXV 16
IN 11
LXV 15
IN 12
LXV 14
IN 13
1 PGND
26 LX
2 PGND
25 LX
3 PGND
24 LX
4 GND
23 LX
5 VFB
2 2 VCC
6 COMP
21 GND
7 UVIN
20 GND
8 GND
19 GND
9 SS
18 BST
10 VIN
17 NC
11 VIN
16 LX
12 VIN
15 LX
13 VIN
14 LX
Now Available in Lead Free Packaging
DESCRIPTION
The SP7653 is a synchronous step-down switching regulator optimized for high efficiency. The part is designed to be
especially attractive for dual supply, 12V to 20V distributed power systems stepped down with 5V used to power the
controller. This lower VCC voltage minimizes power dissipation in the part and is used to drive the top switch. The SP7653
is designed to provide a fully integrated buck regulator solution using a fixed 1.3MHz frequency, PWM voltage mode
architecture. Protection features include Under Voltage Lock Out (UVLO), thermal shutdown and output short circuit
protection. The SP7653 is available in the space saving DFN package.
TYPICAL APPLICATION CIRCUIT
L1 IHLP2525CZER2R2M01
U1
SP7653
1
1.5nF
2
RZ2
CZ2
3
38.3k1, 1%
CP1
4
5
3.3pF
6
7
CF1
100pF
8
9
CSS
22nF
10
11
12
13
VIN
12V
C1,C5:
CERAMIC
X5R
GND
R3
200k1,1%
C1
22uF
16V
C5
22uF
16V
PGND
LX
PGND
LX
PGND
LX
GND
LX
VFB
VCC
COMP
GND
UVIN
GND
GND
GND
SS
BST
VIN
NC
VIN
LX
VIN
LX
VIN
LX
Fs=1.3MHz
1
2
3
R4
C2
100k1,1% 0.1uF
26
2.2uH, Irate=8A
DCR=18m1
25
C3: X5R
CERAMIC
24
23
22
21
20
C3
47uF
6.3V
CVCC
2.2uF
17
16
15
14
RBST
5.111,
1%
CBST
1uF
CZ3
820pF
VOUT
3.30V
0-3A
R1
68.1k1,1%
GND2
19
18
RZ3
1581,1%
R2
21.5k1,1%
DBST
SD101AWS
U2
SPX5205
VIN
VOUT
5
GND
EN
BYP
4
Notes:
U1 Bottom-Side Layout should have
three Contacts which are
isolated from one another: QTDrain Contact, QB-Drain Contact and
Controller-GND Contact.
ALL RESISTORS & CAPACITORS ARE SIZE
0603 UNLESS OTHERWISE SPECIFIED.
2/17/06
Date: 11/20/06
SP7653
Voltage
Range,
1.3MHz,
Regulator
SP7653
WideWide
InputInput
Voltage
Range,
1.3MHz,
BuckBuck
Regulator
1
© Copyright 2006 Sipex Corporation
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the
specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
VCC .................................................................................................. 7V
VIN ........................................................................................................................................... 20V
ILX ............................................................................................................................................... 5A
BST ............................................................................................... 27V
LX-BST ............................................................................. -0.3V to 7V
LX ....................................................................................... -1V to 20V
All other pins .......................................................... -0.3V to VCC+0.3V
Storage Temperature .................................................. -65°C to 150°C
Power Dissipation ...................................... Internally Limited via OTP
ESD Rating .......................................................................... 2kV HBM
Thermal Resistance VJC .................................................................................... 5°C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < TAMB < 85°C, -40°C< Tj< 125°C, 4.5V < VCC < 5.5V, 3V< Vin< 28V, Boost=LX + 5V,
LX = GND = 0.0V, UVIN = 3.0V, CVCC = 1µF, CCOMP = 0.1µF, CSS = 50nF, Typical measured at VCC = 5V.
The z denotes the specifications which apply over the full temperature range, unless otherwise specified.
PARAMETER
MIN.
TYP.
MAX.
UNITS
1.5
3
mA
CONDITIONS
QUIESCENT CURRENT
VCC Supply Current (No switching)
VCC Supply Current (switching)
8
Boost Supply Current (No
switching)
0 .2
Boost Supply Current (switching)
4.0
mA
0. 4
VFB =0.9V
♦
mA
mA
VFB =0.9V
♦
PROTECTION: UVLO
VCC UVLO Start Threshold
4 .0 0
4.25
4.5
V
VCC UVLO Hysteresis
10 0
200
30 0
mV
UVIN Start Threshold
2.3
2.5
2.65
V
UVIN Hysteresis
200
300
400
mV
1
µA
UVIN Input Current
♦
UVIN= 3.0V
ERROR AMPLIFIER REFERENCE
Error Amplifier Reference
0.792
0.800
0.808
V
Error Amplifier Reference
Over Line and Temperature
0.788
0.800
0.812
V
2X Gain Config., Measure
VFB; VCC =5 V, T=25ºC
♦
Error Amplifier Transconductance
6
mA/V
Error Amplifier Gain
60
dB
No Load
COMP Sink Current
150
µA
VFB =0.9V, COMP= 0.9V
COMP Source Current
150
µA
VFB =0.7V, COMP= 2.2V
VFB Input Bias Current
50
nA
VFB = 0.8V
Internal Pole
4
MH z
COMP Clamp
2.5
V
COMP Clamp Temp. Coefficient
-2
mV/ºC
Date: 11/20/06
2/17/06
Date:
20 0
SP7653
Voltage
Range,
1.3MHz,
Regulator
SP7653
WideWide
InputInput
Voltage
Range,
1.3MHz,
BuckBuck
Regulator
2
VFB =0.7V, TA=25ºC
© Copyright
Copyright 2006
2006 Sipex
Sipex Corporation
Corporation
©
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < TAMB < 85°C, -40°C< Tj< 125°C, 4.5V < VCC < 5.5V, 3V< Vin< 28V, Boost = LX + 5V,
LX = GND = 0.0V, UVIN = 3.0V, CVCC = 1µF, CCOMP = 0.1µF, CSS = 50nF, Typical measured at VCC = 5V.
The z denotes the specifications which apply over the full temperature range, unless otherwise specified.
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH
Ramp Amplitude
0.92
1.1
1.28
V
RAMP Offset
1.1
V
RAMP offset Temp. Coefficient
-2
mV/ºC
GH Minimum Pulse Width
90
Maximum Controllable Duty Ratio
92
Maximum Duty Ratio
100
Internal Oscillator Ratio
1.1
180
97
1.3
1. 5
ns
TA = 25ºC, RAMP COMP
until GH starts Switching
♦
%
Maximum Duty Ratio
Measured just before
pulsing begins
%
Valid for 20 cycles
MHz
♦
TIMERS: SOFTSTART
SS Charge Current:
10
SS Discharge Current:
µA
1
mA
♦
Fault Present, SS = 0.2V
V
♦
Measured VREF (0.8V) V FB
PROTECTION: Short Circuit & Thermal
Short Circuit Threshold Voltage
0.2
0.25
0. 3
Hiccup Timeout
200
ms
VFB = 0.5V
Number of Allowable Clock Cycles
at 100% Duty Cycle
20
Cycles
Minimum GL Pulse After 20 Cycles
0. 5
Cycles
VFB = 0.7V
Thermal Shutdown Temperature
14 5
ºC
VFB = 0.7V
Thermal Recovery Temperature
13 5
ºC
Thermal Hysteresis
10
ºC
High Side Switch RDSON
40
mΩ
VCC = 5V ; IOUT = 3A
TAMB = 25ºC
Synchronous Lowside Switch RDSON
40
mΩ
VCC = 5V ; IOUT = 3A
TAMB = 25ºC
OUTPUT: POWER STAGE
Maximum Output Current
Date: 11/20/06
2/17/06
3
A
SP7653
Voltage
Range,
1.3MHz,
Regulator
SP7653
WideWide
InputInput
Voltage
Range,
1.3MHz,
BuckBuck
Regulator
3
© Copyright 2006 Sipex Corporation
PIN DESCRIPTION
Pin #
Pin Name
Description
1-3
PGND
Ground connection for the synchronous rectifier
4,8,19-21
GND
Ground Pin. The control circuitry of the IC and lower power driver are
referenced to this pin. Return separately from other ground traces to the (-)
terminal of COUT.
5
VFB
Feedback Voltage and Short Circuit Detection pin. It is the inverting input of
the Error Amplifier and serves as the output voltage feedback point for the
Buck Converter. The output voltage is sensed and can be adjusted through
an external resistor divider. Whenever V FB drops 0.25V below the positive
reference, a short circuit fault is detected and the IC enters hiccup mode.
6
COMP
7
UVIN
9
SS
10-13
VIN
14-16,23-26
LX
17
NC
No Connect
18
BST
High side driver supply pin. Connect BST to the external boost diode and
capacitor as shown in the Typical Application Circuit on page 1. High side
driver is connected between BST pin and SWN pin.
22
Vcc
Input for external 5V bias supply
Output of the Error Amplifier. It is internally connected to the inverting input of
the PWM comparator. An optimal filter combination is chosen and connected
to this pin and either ground or VFB to stabilize the voltage mode loop.
UVLO input for VIN voltage. Connect a resistor divider between V IN and UVIN
to set minimum operating voltage.
Soft Start. Connect an external capacitor between SS and GND to set the
soft start rate based on the 10µA source current. The SS pin is held low via a
1mA (min) current during all fault conditions.
Input connection to the high side N-channel MOSFET. Place a decoupling
capacitor between this pin and PGND.
Connect an inductor between this pin and V OUT
THEORY OF OPERATION
General Overview
The SP7653 is a fixed frequency, voltage mode,
synchronous PWM regulator optimized for high
efficiency. The part has been designed to be
especially attractive for high input voltages of
2.5V to 20V.
The SP7653 contains two unique control features that are very powerful in distributed applications. First, asynchronous driver control is
enabled during startup, to prohibit the low side
switch from pulling down the output until the
high side switch has attempted to turn on. Second, a 100% duty cycle timeout ensures that the
low side switch is periodically enhanced during
extended periods at 100% duty cycle. This guarantees the synchronized refreshing of the Boost
capacitor during very large duty cycle ratios.
The heart of the SP7653 is a wide bandwidth
transconductance amplifier designed to accommodate Type II and Type III compensation
schemes. A precision 0.8V reference, present on
the positive terminal of the error amplifier,
permits the programming of the output voltage
down to 0.8V via the VFB pin. The output of the
error amplifier, COMP, compared to a 1.1V
peak-to-peak ramp is responsible for trailing
edge PWM control. This voltage ramp, and
PWM control logic are governed by the internal
oscillator that accurately sets the PWM frequency to 1.3MHz.
Date: 11/20/06
2/17/06
Date:
The SP7653 also contains a number of valuable
protection features. Programmable VIN UVLO
allows the user to set the exact value at which the
conversion voltage can safely begin down conversion, and an internal VCC UVLO which ensures that the controller itself has enough voltage to operate properly. Other protection fea-
SP7653
Voltage
Range,
1.3MHz,
Regulator
SP7653
WideWide
InputInput
Voltage
Range,
1.3MHz,
BuckBuck
Regulator
4
© Copyright
Copyright 2006
2006 Sipex
Sipex Corporation
Corporation
©
THEORY OF OPERATION
Thermal and Short-Circuit Protection
tures include thermal shutdown and short-circuit detection. In the event that either a thermal,
short-circuit, or UVLO fault is detected, the
SP7653 is forced into an idle state where the
output drivers are held off for a finite period
before a restart is attempted.
Because the SP7653 is designed to drive large
output current, there is a chance that the power
converter will become too hot. Therefore, an
internal thermal shutdown (145°C) has been
included to prevent the IC from malfunctioning
at extreme temperatures.
Soft Start
“Soft Start” is achieved when a power converter
ramps up the output voltage while controlling
the magnitude of the input supply source current. In a modern step down converter, ramping
up the positive terminal of the error amplifier
controls soft start. As a result, excess source
current can be defined as the current required to
charge the output capacitor:
A short-circuit detection comparator has also
been included in the SP7653 to protect against
an accidental short at the output of the power
converter. This comparator constantly monitors
the positive and negative terminals of the error
amplifier, and if the VFB pin falls more than
250mV (typical) below the positive reference, a
short-circuit fault is set. Because the SS pin
overrides the internal 0.8V reference during soft
start, the SP7653 is capable of detecting shortcircuit faults throughout the duration of soft
start as well as in regular operation.
IVIN = COUT * (6VOUT / 6TSOFT-START)
The SP7653 provides the user with the option to
program the soft start rate by tying a capacitor
from the SS pin to GND. The selection of this
capacitor is based on the 10uA pull up current
present at the SS pin and the 0.8V reference
voltage. Therefore, the excess source can be
redefined as:
Handling of Faults:
Upon the detection of power (UVLO), thermal,
or short-circuit faults, the SP7653 is forced into
an idle state where the SS and COMP pins are
pulled low and both switches are held off. In the
event of UVLO fault, the SP7653 remains in this
idle state until the UVLO fault is removed.
Upon the detection of a thermal or short-circuit
fault, an internal 200ms timer is activated. In the
event of a short-circuit fault, a restart is attempted immediately after the 200ms timeout
expires. Whereas, when a thermal fault is detected, the 200ms delay continuously recycles
and a restart cannot be attempted until the thermal fault is removed and the timer expires.
IVIN = COUT *[ (DVOUT *10µA) /(CSS * 0.8V)]
Under Voltage Lock Out (UVLO)
The SP7653 contains two separate UVLO comparators to monitor the bias (VCC) and conversion (VIN) voltages independently. The VCC
UVLO threshold is internally set to 4.25V,
whereas the VIN UVLO threshold is programmable through the UVIN pin. When the voltage
on the UVIN pin is greater than 2.5V, the SP7653
is permitted to start up pending the removal of
all other faults. Both the VCC and VIN UVLO
comparators have been designed with hysteresis
to prevent noise from resetting a fault.
Date:
Date: 11/20/06
2/17/06
Error Amplifier and Voltage Loop
The heart of the SP7653 voltage error loop
compensation is a high performance, wide bandwidth transconductance amplifier. Because of
the amplifier’s current limited (+/-150µA)
transconductance, there are many ways to compensate the voltage loop or to control the COMP
SP7653
WideWide
InputInput
Voltage
Range,
1.3MHz,
BuckBuck
Regulator
SP7653
Voltage
Range,
1.3MHz,
Regulator
5
©
© Copyright
Copyright 2006
2006 Sipex
Sipex Corporation
Corporation
THEORY OF OPERATION
pin externally. If a simple, single-pole singlezero response is desired, then compensation can
be as simple as an RC circuit to Ground. If a
more complex compensation is required, then
the amplifier has enough bandwidth (45° at 4
MHz) and enough gain (60dB) to run Type III
compensation schemes with adequate gain and
phase margins at crossover frequencies greater
than 50kHz.
VBST
GH
Voltage
VSWN
V(VCC)
GL
Voltage
0V
V(VIN)
The common mode output of the error amplifier
is 0.9V to 2.2V. Therefore, the PWM voltage
ramp has been set between 1.1V and 2.2V to
ensure proper 0% to 100% duty cycle capability.
The voltage loop also includes two other very
important features. One is an asynchronous
startup mode. Basically, the synchronous rectifier cannot turn on unless the high side switch
has attempted to turn on or the SS pin has
exceeded 1.7V. This feature prevents the controller from “dragging down” the output voltage
during startup or in fault modes. The second
feature is a 100% duty cycle timeout that ensures synchronized refreshing of the Boost capacitor at very high duty ratios. In the event that
the high side NFET is on for 20 continuous
clock cycles, a reset is given to the PWM flipflop half way through the 21st cycle. This forces
GL to rise for the cycle, in turn refreshing the
Boost capacitor. The boost capacitor is used to
generate a high voltage drive supply for the high
side switch, which is 5V above VIN.
SWN
Voltage
-0V
-V(Diode) V
V(VIN)+V(VCC)
BST
Voltage
V(VCC)
TIME
Setting Output Voltages
The SP7653 can be set to different output voltages. The relationship in the following formula
is based on a voltage divider from the output to
the feedback pin VFB, which is set to an internal
reference voltage of 0.80V. Standard 1% metal
film resistors of surface mount size 0603 are
recommended.
Power MOSFETs
VOUT = 0.80V ( R1 / R2 + 1 ) =>
The SP7653 contains a pair of integrated low
resistance N-channel switches designed for up
to 3Amps. Care should be taken to de-rate the
output current based on the thermal conditions
in the system such as ambient temperature,
airflow and heat sinking. Maximum output current could be limited by thermal limitations of a
particular application by taking advantage of
the integrated-over-temperature protective
scheme employed in the SP7653. The SP7653
incorporates a built-in overtemperature protection to prevent internal overheating.
R2 =
Date: 2/17/06
Date: 11/20/06
R1
.
{ ( VOUT / 0.80V ) – 1 }
Where R1 = 68.1K1 and for VOUT = 0.80V
setting, simply remove R2 from the board. Furthermore, one could select the value of the R1
and R2 combination to meet the exact output
voltage setting by restricting the resistance range
of R1 such that 50K1 < R1 < 100K1 for overall
system loop stability.
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
6
© Copyright 2006 Sipex Corporation
© Copyright 2006 Sipex Corporation
APPLICATIONS INFORMATION
Inductor Selection
I PEAK = I OUT (max) +
There are many factors to consider in selecting
the inductor including core material, inductance
vs. frequency, current handling capability, efficiency, size and EMI. In a typical SP7653 circuit, the inductor is chosen primarily for value,
saturation current and DC resistance. Increasing
the inductor value will decrease output voltage
ripple, but degrade transient response. Low inductor values provide the smallest size, but
cause large ripple currents, poor efficiency and
require more output capacitance to smooth out
the larger ripple current. The inductor must be
able to handle the peak current at the switching
frequency without saturating, and the copper
resistance in the winding should be kept as low
as possible to minimize resistive power loss. A
good compromise between size, loss and cost is
to set the inductor ripple current to be within
20% to 40% of the maximum output current.
...and provide low core loss at the high switching frequency. Low cost powdered-iron cores
have a gradual saturation characteristic but can
introduce considerable AC core loss, especially
when the inductor value is relatively low and the
ripple current is high. Ferrite materials, although
more expensive, have an abrupt saturation characteristic with the inductance dropping sharply
when the peak design current is exceeded. Nevertheless, they are preferred at high switching
frequencies because they present very low core
loss while the designer is only required to
prevent saturation. In general, ferrite or
molypermalloy materials are a better choice for
all but the most cost sensitive applications.
Optimizing Efficiency
The switching frequency and the inductor operating point determine the inductor value as follows:
L=
The power dissipated in the inductor is equal to
the sum of the core and copper losses. To minimize copper losses, the winding resistance needs
to be minimized, but this usually comes at the
expense of a larger inductor. Core losses have a
more significant contribution at low output current where the copper losses are at a minimum,
and can typically be neglected at higher output
currents where the copper losses dominate. Core
loss information is usually available from the
magnetics vendor. Proper inductor selection can
affect the resulting power supply efficiency by
more than 15%!
VOUT (V IN (max) < VOUT )
VIN (max) FS Kr I OUT ( max)
where:
fS = switching frequency
Kr = ratio of the AC inductor ripple current to
the maximum output current
The copper loss in the inductor can be calculated
using the following equation:
The peak-to-peak inductor ripple current is:
I PP =
PL( Cu) = I L2 ( RMS ) RWINDING
VOUT (VIN (max) < VOUT )
where IL(RMS) is the RMS inductor current that
can be calculated as follows:
VI N (max) FS L
IL(RMS) = IOUT(max) 1 + 1
3
Once the required inductor value is selected, the
proper selection of core material is based on
peak inductor current and efficiency requirements. The core must be large enough not to
saturate at the peak inductor current...
2/17/06
Date: 11/20/06
I PP
2
SP7653
Voltage
Range,
1.3MHz,
Regulator
SP7653
WideWide
InputInput
Voltage
Range,
1.3MHz,
BuckBuck
Regulator
7
(
IPP
)
2
IOUT(max)
© Copyright
Copyright 2006
2006 Sipex
Sipex Corporation
Corporation
©
APPLICATIONS INFORMATION
Output Capacitor Selection
FS = Switching Frequency
The required ESR (Equivalent Series Resistance) and capacitance drive the selection of the
type and quantity of the output capacitors. The
ESR must be small enough that both the resistive voltage deviation due to a step change in the
load current and the output ripple voltage do not
exceed the tolerance limits expected on the
output voltage. During an output load transient,
the output capacitor must supply all the additional current demanded by the load until the
SP7653 adjusts the inductor current to the new
value.
D = Duty Cycle
COUT = Output Capacitance Value
Input Capacitor Selection
The input capacitor should be selected for ripple
current rating, capacitance and voltage rating.
The input capacitor must meet the ripple current
requirement imposed by the switching current.
In continuous conduction mode, the source current of the high-side MOSFET is approximately
a square wave of duty cycle VOUT/VIN. More
accurately, the current wave form is trapezoidal,
given a finite turn-on and turn-off, switch transition slope. Most of this current is supplied by
the input bypass capacitors. The RMS current
handling capability of the input capacitors is
determined at maximum output current and
under the assumption that the peak-to-peak inductor ripple current is low; it is given by:
In order to maintain VOUT ,the capacitance must
be large enough so that the output voltage is held
up while the inductor current ramps to the value
corresponding to the new load current. Additionally, the ESR in the output capacitor causes
a step in the output voltage equal to the current.
Because of the fast transient response and inherent 100% to 0% duty cycle capability provided
by the SP7653 when exposed to an output load
transient, the output capacitor is typically chosen for ESR, not for capacitance value.
ICIN(RMS) = IOUT(max) D(1 - D)
3
The worst case occurs when the duty cycle D is
50% and gives an RMS current value equal to
IOUT/2. Select input capacitors with adequate
ripple current rating to ensure reliable operation.
The ESR of the output capacitor, combined with
the inductor ripple current, is typically the main
contributor to output voltage ripple. The maximum allowable ESR required to maintain a
specified output voltage ripple can be calculated
by:
RESR )
The power dissipated in the input capacitor is:
6VOUT
2
PCIN = ICIN
( rms ) R ESR ( CIN )
IPK-PK
where:
This can become a significant part of power
losses in a converter and hurt the overall energy
transfer efficiency. The input voltage ripple
primarily depends on the input capacitor ESR
and capacitance. Ignoring the inductor ripple
current, the input voltage ripple can be determined by:
6VOUT = Peak-to-Peak Output Voltage Ripple
IPK-PK = Peak-to-Peak Inductor Ripple Current
The total output ripple is a combination of the
ESR and the output capacitance value and can
be calculated as follows:
(
6VOUT = IPP (1 – D)
COUTFS
Date:
2/17/06
Date: 11/20/06
)
2
+
6 VIN = I out (max) RE SR (CIN ) +
(IPPRESR)2
SP7653
Wide
Input
Voltage
Range,
1.3MHz,
Regulator
SP7653
Wide
Input
Voltage
Range,
1.3MHz,
BuckBuck
Regulator
8
I OUT ( MAX )VOUT (VI N < VOUT )
FS C INV IN
2
©
© Copyright
Copyright 2006
2006 Sipex
Sipex Corporation
Corporation
APPLICATIONS INFORMATION
The capacitor type suitable for the output capacitors can also be used for the input capacitors.
However, exercise extra caution when tantalum
capacitors are used. Tantalum capacitors are known
for catastrophic failure when exposed to surge
current, and input capacitors are prone to such
surge current when power supplies are connected
“live” to low impedance power sources. Although
tantalum capacitors have been successfully employed at the input, it is generally not recommended.
The first step of compensation design is to pick
the loop crossover frequency. High crossover
frequency is desirable for fast transient response,
but often jeopardizes the power supply stability.
Crossover frequency should be higher than the
ESR zero but less than 1/5 of the switching
frequency or 60kHz. The ESR zero is contributed by the ESR associated with the output
capacitors and can be determined by:
Loop Compensation Design
The next step is to calculate the complex conjugate poles contributed by the LC output filter,
ƒZ(ESR) =
The open loop gain of the whole system can be
divided into the gain of the error amplifier,
PWM modulator, buck converter output stage,
and feedback resistor divider. In order to cross
over at the desired frequency cut-off (FCO), the
gain of the error amplifier must compensate for
the attenuation caused by the rest of the loop at
this frequency. The goal of loop compensation
is to manipulate loop frequency response such
that its crossover gain at 0db, results in a slope
of -20db/dec.
ƒP(LC) =
+
_
2/ COUT RESR
1
2/
L COUT
When the output capacitors are Ceramic, the
SP7653 Evaluation Board requires a Type III
compensation circuit to give a phase boost of
180° in order to counteract the effects of an
underdamped resonance of the output filter at
the double pole frequency.
Type III Voltage Loop
Compensation
GAMP (s) Gain Block
VREF
(Volts)
1
PWM Stage
GPWM Gain
Block
Output Stage
GOUT (s) Gain
Block
VIN
(SRz2Cz2+1)(SR1Cz3+1)
(SRESRCOUT+ 1)
VRAMP_PP
SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)
[S^2LCOUT+S(RESR+RDC) COUT+1]
VOUT
(Volts)
Notes: RESR = Output Capacitor Equivalent Series Resistance.
RDC = Output Inductor DC Resistance.
VRAMP_PP = SP6132 Internal RAMP Amplitude Peak to Peak Voltage.
Condition: Cz2 >> Cp1 & R1 >> Rz3
Output Load Resistance >> RESR & RDC
Voltage Feedback
GFBK Gain Block
R2
VFBK
(Volts)
(R1 + R2)
or
VREF
VOUT
SP7653 Voltage Mode Control Loop with Loop Dynamic
Definitions:
RESR = Output Capacitor Equivalent Series Resistance
RDC = Output Inductor DC Resistance
RRAMP_PP = SP7653 internal RAMP Amplitude Peak to Peak Voltage
Conditions:
CZ2 >> Cp1 and R1 >> Rz3
Output Load Resistance >> RESR and RDC
Date:
2/17/06
Date: 11/20/06
SP7653
Wide
Input
Voltage
Range,
1.3MHz,
Buck
Regulator
SP7653
Wide
Input
Voltage
Range,
1.3MHz,
Buck
Regulator
9
©
© Copyright
Copyright 2006
2006 Sipex
Sipex Corporation
Corporation
APPLICATIONS INFORMATION
Gain
(dB)
Error Amplifier Gain
Bandwidth Product
Condition:
C22 >> CP1, R1 >> RZ3
1/6.28 (RZ3) (CZ3)
1/6.28 (RZ2) (CP1)
1/6.28 (R1) (CZ2)
1/6.28 (R1) (CZ3)
1/6.28(R22) (CZ2)
20 Log (RZ2/R1)
Frequency
(Hz)
Bode Plot of Type III Error Amplifier Compensation.
CP1
RZ3
CZ3
CZ2
VOUT
R1
68.1k, 1%
5
VFB
R
SET
+
+
- 0.8V
R
SET
RZ2
6
COMP
CF1
-0.8V)(k1)
=54.48/ (V
OUT
Type III Error Amplifier Compensation Circuit
Date: 11/20/06
2/17/06
SP7653
Voltage
Range,
1.3MHz,
Regulator
SP7653
WideWide
InputInput
Voltage
Range,
1.3MHz,
BuckBuck
Regulator
10
10
© Copyright 2006 Sipex Corporation
APPLICATIONS INFORMATION
SP765X Thermal Resistance
The SP765X family has been tested with a
variety of footprint layouts along with different
copper area and thermal resistance has been
measured. The layouts were done on 4 layer
FR4 PCB with the top and bottom layers using
3oz copper and the Power and Ground layers
using 1oz copper.
Using a minimum of 0.1 square inches of (3
ounces of) copper on the top layer with no vias
connecting to the 3 other layers produced a
thermal resistance of 44°C/W. This thermal
impedance is only 22% higher than the medium
and large footprint layouts, indicating that space
constrained designs can still benefit thermally
from the Powerblox family of ICs. This indicates that a minimum footprint of 0.1 square
inch, if used on a 4 layer board, can produce
44°C/W thermal resistance. This approach is
still very worthwhile if used in a space constrained design.
For the Minimum footprint, only about 0.1 square
inch (of 3 ounces of) copper was used on the top
or footprint layer, and this layer had no vias to
connect to the 3 other layers. For the Medium
footprint, about 0.7 square inches (of 3 ounces
of) copper was used on the top layer, but vias
were used to connect to the other 3 layers. For
the Maximum footprint, about 1.0 square inch
(of 3 ounces of) copper was used on the top layer
and many vias were used to connect to the 3
other layers.
The following page shows the footprint layouts
from an ORCAD file. The thermal data was
taken for still air, not with forced air. If forced
air is used, some improvement in thermal resistance would be seen.
The results show that only about 0.7 square
inches (of 3 ounces of) copper on the top layer
and vias connecting to the 3 other layers are
needed to get the best thermal resistance of
36°C/W. Adding area on the top beyond the 0.7
square inches did not reduce thermal resistance.
SP765X Thermal Resistance
4 Layer Board:
Top Layer 3ounces Copper
GND Layer 1ounce Copper
Power Layer 1ounce Copper
Bottom Layer 3ounces Copper
Minimum Footprint: 44°C/W
Top Layer: 0.1 square inch
No Vias to other 3 Layers
Medium Footprint: 36°C/W
Top Layer: 0.7 square inch
Vias to other 3 Layers
Maximum Footprint: 36°C/W
Top Layer: 1.0 square inch
Vias to other 3 Layers
Date: 2/17/06
Date: 11/20/06
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
11
11
© Copyright 2006 Sipex Corporation
© Copyright 2006 Sipex Corporation
APPLICATIONS INFORMATION
Date: 2/17/06
Date: 11/20/06
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
12
12
© Copyright 2006 Sipex Corporation
© Copyright 2006 Sipex Corporation
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Output Load at 12Vin
100
Efficiency (%)
90
80
70
Vout = 5.0V
Vout = 3.3V
60
Vout = 2.5V
Vout = 1.8V
50
Vout = 1.5V
Vout = 1.2V
40
0
0.5
1
1.5
2
Output Load Current (A)
2.5
3
2.5
3
2.5
3
Efficiency vs Output Load at 5Vin
100
Efficiency (%)
90
80
70
Vout = 3.3V
Vout = 2.5V
60
Vout = 1.8V
50
Vout = 1.5V
Vout = 1.2V
40
0
0.5
1
1.5
2
Output Load Current (A)
Efficiency vs Output Load at 3.3Vin
100
Efficiency (%)
90
80
70
Vout = 2.5V
60
Vout = 1.8V
Vout = 1.5V
50
Vout = 1.2V
40
0
0.5
1
1.5
2
Output Load Current (A)
Date:
2/17/06
Date: 11/20/06
SP7653
Wide
Input
Voltage
Range,
1.3MHz,
Regulator
SP7653
Wide
Input
Voltage
Range,
1.3MHz,
BuckBuck
Regulator
13
13
©
© Copyright
Copyright 2006
2006 Sipex
Sipex Corporation
Corporation
PACKAGE: 26 PIN DFN
D
e
E
L
(7 x 4 mm)
14
15
16
17
b
26
18
L
E2
TOP VIEW
Pin #1
Identification
13
5
4
3
2
1
L/2
J
D3
D2
J1
D2
J1
BOTTOM VIEW
Note: Fused Pin Area for pins 1-3 and
pins 14-16 = (2e+b)xL - 2x(e-b) x L/2
= 0.376mm2 or 0.0148 in2
A
A3
A1
(K)
SIDE VIEW
26 Pin
SYMBOL
A
A1
A3
b
D
D2
D3
e
E
E2
J
J1
K
L
Dimensions in Millimeters:
Controlling Dimension
MIN
0.800
0.000
0.178
0.170
6.950
2.000
1.780
3.950
2.730
0.200
0.250
0.340
0.350
NOM
0.900
0.203
0.220
7.000
2.050
1.830
0.500 BSC
4.000
2.780
0.250
0.300
0.390
0.400
MAX
1.000
0.050
0.228
0.270
7.050
2.100
1.880
4.050
2.830
0.300
0.350
0.440
0.450
SIPEX Pkg Signoff Date/Rev:
Date: 11/20/06
2/17/06
Date:
DFN
Dimensions in Inches
Conversion Factor:
1 Inch = 25.40 mm
MIN
NOM
MAX
0.0315
0.0354
0.0394
0.0000
0.0020
0.0070
0.0080
0.0090
0.0067
0.0087
0.0106
0.2736
0.2756
0.2776
0.0787
0.0807
0.0827
0.0701
0.0720
0.0740
0.0197 BSC
0.1555
0.1575
0.1594
0.1075
0.1094
0.1114
0.0079
0.0098
0.0118
0.0098
0.0118
0.0138
0.0134
0.0154
0.0173
0.0138
0.0157
0.0177
JL Feb16-06 / RevB
SP7653
Voltage
Range,
1.3MHz,
Regulator
SP7653
WideWide
InputInput
Voltage
Range,
1.3MHz,
BuckBuck
Regulator
14
14
© Copyright
Copyright 2006
2006 Sipex
Sipex Corporation
Corporation
©
Part Number
Temperature
ORDERING INFORMATION
Package
SP7653ER .............................................. -40°C to +85°C ................................. 26 Pin 7 X 4 DFN
SP7653ER-L ........................................... -40°C to +85°C ............. (Lead Free) 26 Pin 7 X 4 DFN
SP7653ER/TR ........................................ -40°C to +85°C ................................. 26 Pin 7 X 4 DFN
SP7653ER-L/TR ..................................... -40°C to +85°C ............. (Lead Free) 26 Pin 7 X 4 DFN
Bulk Pack minimum quantity is 500.
/TR = Tape and Reel. Pack quantity is 3,000 DFN.
Sipex Corporation
Sipex Corporation
Headquarters
and
Sales Office
Headquarters
and
233 South Hillview
Drive
Sales Office
Solved by Sipex
Milpitas,
CA 95035
233 (408)
South934-7500
Hillview Drive
TEL:
Milpitas,
95035
FAX:
(408)CA
935-7600
TEL: (408) 934-7500
Solved By
Sipex
TM
Sipex
Corporation
reserves
right
to make changes to any products described herein. Sipex does not assume
FAX: the
(408)
935-7600
any liability arising out of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others.
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
tm
Date:
2/17/06
Date: 11/20/06
SP7653
Wide
Voltage
Range,
1.3MHz,
Regulator
SP7653
Wide
InputInput
Voltage
Range,
1.3MHz,
BuckBuck
Regulator
15
15
©
© Copyright
Copyright 2006
2006 Sipex
Sipex Corporation
Corporation