RT9645 Preliminary 5 Channels ACPI Regulator General Description Features The RT9645 is a combo regulator which is compliant to ACPI specification for desktop/server power management and system application. The part features one switching regulator for DDR memory VDDQ power; a second PWM controller for GMCH core power, a LDO controller for FSB_ VTT termination, a LDO controller for 5VSB to 3VSB conversion; and a dual power control 5VDL for S0 and S3 system power. z Integrated 5 Channels Power Regulator z DC/DC Buck PWM Regulator (Driver Included) DC/DC Buck PWM Controller Linear Regulator Controller for FSB_VTT Power 3.3VSB Linear Regulator Controller with 40mA Output Capability 5VDL Switch Control Conform to ACPI Specification, Supporting Power Management at S0, S3, and S5 State 300kHz Fixed Frequency Oscillator Low-Side RDS(ON) Current Sensing for Precision Over-Current Detection Thermal Shutdown Small 24-Lead VQFN Package RoHS Compliant and 100% Lead (Pb)-Free The part is generally operated to conform to ACPI specification. In S3 mode, only VDDQ and 3.3VSB regulators remain on while the FSB_ VTT regulator is off. In the transition from S3 to S0, an internal SS capacitor is attached for linear regulators to control its slew rate respectively to avoid inrush current induced. z z z z z z z z z z RT9645 supports both Intel VR11 and AMD K8 platform. There is extra control pin VTT_EN to enable FSB_VTT regulator at AMD K8 mode. This part also implements PWM1 (VDDQ) enabled by release COMP1 at AMD K8 application. This part is assemblyed in the tiny VQFN-24L 4x4 package. Applications z z Desktop System Power Server System Power Pin Configurations Ordering Information (TOP VIEW) VCC_DRV SB5V_DRV GND S5 19 18 VTT_DRV VDD 2 17 VTT_SEN PWM2 3 16 VTT_EN 15 ISNS2 14 FB1 13 COMP1 SS2/EN2 4 COMP2 5 FB2 6 PGND 25 7 8 9 10 11 12 LGATE `Suitable for use in SnPb or Pb-free soldering processes. `100% matte tin (Sn) plating. 20 PVIN ments of IPC/JEDEC J-STD-020. 21 ISNS `RoHS compliant and compatible with the current require- 22 PHASE Richtek Pb-free and Green products are : 23 1 BOOT Note : 24 SB3V_DRV UGATE Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard) SB3V_SEN Package Type QV : VQFN-24L 4x4 S3 RT9645 VQFN-24L 4x4 DS9645-00 August 2007 www.richtek.com 1 RT9645 Preliminary Typical Application Circuit VCC5 5VSB VCC12 11 VCC5/VCC12 Q3 VGMCH Q4 Richtek MOSFET Driver 3 ROCSET2 15 6 Q5 BOOT ISNS 7 10 5VDL ROCSET1 PWM2 RT9645 5 VCC3 PVIN VDD 2 18 UGATE 8 Q1 L1 ISNS2 PHASE 9 COMP2 LGATE FB2 GND VDDQ 12 Q2 19 VTT_DRV 17 VTT_SEN FSB_VTT COMP1 5VSB FB1 Q6 1 SB3V_DRV 24 SB3V_SEN 3VSB 13 14 VCC5 VCC_DRV 21 5VDL 4 SS2/EN2 PWM2-EN SB5V_DRV 20 5VSB 16 VTT_EN VLDT_EN 23 S3 S3 S5 22 S5 Figure 1. RT9645 Typical Application for Intel Mode VCC5 5VSB VCC12 VCC5/VCC12 Q3 VGMCH Richtek MOSFET Driver ROCSET2 Q4 3 6 Q5 BOOT ISNS 18 UGATE ISNS2 COMP2 Q6 Q1 L1 LGATE GND 12 VDDQ Q2 19 VTT_DRV FB1 1 13 14 5VSB SB3V_DRV 24 SB3V_SEN VCC_DRV 4 SS2/EN2 21 20 16 VTT_EN 23 S3 VCC5 5VDL SB5V_DRV S3 8 PHASE 9 FB2 5VSB VLDT_EN 5VDL ROCSET1 PWM2 COMP1 PWM2-EN 10 17 VTT_SEN FSB_VTT 3VSB 7 RT9645 15 5 VCC3 11 PVIN VDD 2 VDDQ_EN 5VSB S5 22 S5 Figure 2. RT9645 Typical Application for AMD K8 www.richtek.com 2 DS9645-00 August 2007 RT9645 Preliminary Timing Diagram ~3Tss 5VSB 3VSB 5VSB- VD PVIN POR VCC12 - VD S5 S3 VCC5/12 5VDL ~Tss VDDQ ~Tss FSB_VTT ~Tss ~Tss Figure 3. RT9645 Timing Diagram for Intel CPU ~3Tss 5VSB 3VSB PVIN 5VSB- VD POR VCC12 - VD S5 S3 VCC5/12 5VDL VDDQ_EN ~Tss VDDQ VTT_EN ~Tss ~Tss ~Tss FSB_VTT Figure 4. RT9645 Timing Diagram for AMD CPU VPT_EN2 Release fault SS2/EN2 VEN2 PWM2_EN (Internal) PWM2 (Output) PWM2 UV Protection_EN Figure 5. RT9645 Timing Diagram for PWM2 DS9645-00 August 2007 www.richtek.com 3 RT9645 Preliminary Functional Pin Description Pin No. 1 Pin Name Function Description SB3V_DRV Gate Drive for 3.3VSB Linear Controller. The pin will be high in S0, S3 and S5 state. IC Power Supply. 5VSB is generally applied for bias power for IC logics and gate 2 VDD driver control. 3 PWM2 Second PWM Output Signal Second PWM Soft Start Ramp/Enable Control SS ramp slope is defined by 4 SS2/EN2 V/T = 5μA/CSS. Compensation pin of PWM2. Output of the PWM2 error amplifier. Connect 5 COMP2 compensation network between this pin and FB2. The output feedback of PWM2. The pin is applied for voltage regulation and provide 6 FB2 under-voltage protection. The pin is applied for VDDQ PWM bootstrapped power for the embedded driver 7 BOOT power. High-Side Drive. High-side MOSFET driver output of VDDQ PWM. Connect to gate 8 UGATE of high-side MOSFET. Phase Node of VDDQ PWM. The pin is applied to sense phase node of VDDQ 9 PHASE PWM for gates switch control. Current Sense Input. Monitors the voltage drop across the low-side MOSFET for 10 ISNS Over current protection. ROCSET1 x 40μA = RDS(ON) x IMAX 11 PVIN Apply to Driver Power Source and generate Internal Power Good Signal. Low-Side Drive. The low-side MOSFET driver output. Connect to gate of low-side 12 LGATE MOSFET. Compensation pin of VDDQ. Output of the VDDQ error amplifier. Connect compensation network between this pin and FB1 In AMD Application. This pin can 13 COMP1 be used to control VDDQ sequence. This pin needs to be pulled low ( < VDIS1) to disable the PWM. The output feedback of PWM1. The pin is applied for voltage regulation, 14 FB1 under-voltage and Over Voltage protection. PWM2 Current Sense Input. Monitors the voltage drop across the low-side 15 ISNS2 MOSFET for Over current protection. ROCSET2 x 40μA = RDS(ON) x IMAX 16 VTT_EN In AMD K8 Application, Connect this pin to VLDT_EN to control FSB_VTT Timing. Feedback for the FSB_VTT Linear Controller. The pin is applied for FSB_VTT LDO 17 VTT_SEN output regulation sense. Gate drive for FSB_VTT Linear Controller. The pin will be turned off in S3 and S5 18 VTT_DRV state. 19 GND Signal Ground. 5VSB Control Switch. The pin is applied to drive an external P-Channel MOSFET to 20 SB5V_DRV switch 5VDL power to 5VSB in S3 state. The pin goes high in S0 and S5 States. VCC5 Control Switch. The pin is applied to driver an external N-Channel MOSFET 21 VCC_DRV low in S5 and S3 States. The pin goes high in S0 State. 22 S5 ACPI Control Signal. 23 S3 ACPI Control Signal. Feedback for the 3.3VSB Linear Controller. The pin is applied for 3.3V LDO output 24 SB3V_SEN regulation sense. The exposed pad must be soldered to a large PCB and connected to PGND for Exposed Pad (25) PGND maximum power dissipation. www.richtek.com 4 DS9645-00 August 2007 RT9645 Preliminary Function Block Diagram SS2/EN2 FB2 FB COMP1 EN_Detect EN_Detect SS + COMP2 + - VREF UV + VREF + BOOT + UGATE PHASE + PWM2 PVIN Oscillator - LGATE SB3V_SEN VDD 70k SB3V_DRV + IOC2 40uA - + 35k ISNS2 + PVIN VTT_DRV - - + ISNS + VTT_EN VDDQ UV or FSB-VTT UV VTT_SEN VDD IOC1 40uA Digital & Peripheral Control + VDDQ OC SB3V Fault (UV &OC) Thermal shut_down Back S5 PVIN VCC_DRV VDD Hiccup SB5V_DRV GND DS9645-00 August 2007 S3 S5 www.richtek.com 5 RT9645 Preliminary Absolute Maximum Ratings (Note 1) Supply Voltage, VDD ------------------------------------------------------------------------------------Supply Voltage, PVIN ----------------------------------------------------------------------------------z PHASE to GND DC -----------------------------------------------------------------------------------------------------------< 200ns ----------------------------------------------------------------------------------------------------z BOOT to GND DC -----------------------------------------------------------------------------------------------------------< 200ns ----------------------------------------------------------------------------------------------------z BOOT, VBOOT − VPHASE ---------------------------------------------------------------------------------z UGATE Voltage ------------------------------------------------------------------------------------------z LGATE Voltage -------------------------------------------------------------------------------------------z Input, Output or I/O Voltage ---------------------------------------------------------------------------z Power Dissipation, PD @ TA = 25°C VQFN-24L 4x4 -------------------------------------------------------------------------------------------z Package Thermal Resistance (Note 4) VQFN-24L 4x4, θJA --------------------------------------------------------------------------------------z Junction Temperature -----------------------------------------------------------------------------------z Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------z Storage Temperature Range --------------------------------------------------------------------------z ESD Susceptibility (Note 2) HBM (Human Body Mode) ----------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------z z Recommended Operating Conditions z z z z 7V 16V −0.5V to 7V −2V to 7V −0.3V to 20V −0.3V to 22V 16V VPHASE − 0.3V to VBOOT + 0.3V GND − 0.3V to VDD + 0.3V GND − 0.3V to 7V 1.85W 54°C/W 150°C 260°C −40°C to 150°C 2kV 200V (Note 3) Supply Voltage, VDD ------------------------------------------------------------------------------------Supply Voltage, PVIN ----------------------------------------------------------------------------------Junction Temperature Range --------------------------------------------------------------------------Ambient Temperature Range --------------------------------------------------------------------------- 5V ± 5% 12V ± 10% −40°C to 125°C 0°C to 70°C Electrical Characteristics (VDD = 5V, PVIN = 12V, TA = 25°C, unless otherwise specification) Parameter Symbol Test Condition Min Typ Max Units -- 4 -- mA Supply Current Nominal Supply Current ICC S0; no load for UGATE / LGATE and regulators Power-On Reset Rising VDD POR Threshold VPORH_5V 3.9 4.1 4.3 V VDD POR Hysteresis VPORHY S_5V 0.06 0.1 -- V Rising PVIN POR Threshold VPORH_12V 9 9.5 10 V PVIN POR Hysteresis VPORHY S_12V VDD = 5V 0.6 1 -- V VDD = 5V To be continued www.richtek.com 6 DS9645-00 August 2007 RT9645 Preliminary Parameter Symbol Test Condition Min Typ Max Units 265 300 345 kHz Oscillator and Soft-Start PW M Frequency fOSC Ramp Amplitude ΔVOSC -- 1.2 -- V Ramp Offset VOSC_OS -- 0.9 -- V Soft-Start Interval TSS 4 8 -- ms VREF 0.784 0.8 0.816 V Reference Voltage Reference Voltage V REF VDDQ PWM1 Controller UGATE Source IUGATEsc V BOOT −V PHASE = 12V; V UGATE − VPHA SE = 6V 0.5 1 -- A UGATE Sink RUGATEsk V BOOT −V PHASE = 12V; V UGATE − VPHASE = 1V -- 4 8 Ω LGATE Source ILGATEsc V PVIN = 12V; VLGATE = 6V 0.5 1 -- A LGATE Sink RLGATEsk V PVIN = 12V; VLGATE = 1V -- 3 5 Ω OC Current Source IOC1 34 40 46 μA Under Voltage Lockout V UV1 -- 75 -- % COMP1 Enable Threshold V EN1 0.1 0.2 -- V 34 40 46 μA -- 75 -- % -- 5 -- μA V IS NS = 0V PWM2 Controller OC current source IOC2 V IS NS2 = 0V Under Voltage Lockout V UV2 SS2/EN2 Source Current ISS2 Enable Threshold V EN2 -- 0.5 -- V UV Protection Enable Threshold V PT_EN2 V DD = 5V -- 3.6 -- V 10.5 -- -- V V SS2/EN2 = 0V FSB_VTT Regulator External Gate Driver VOH3 V PVIN = 12V Gate Source Current ISC3 V VTT_DRV = 3V -- 4 -- mA Gate Sink Current ISK3 V VTT DRV = 0.6V 15 22 -- mA Under Voltage Lockout VUV3 -- 75 -- % 3VSB Regulator Regulated Voltage V 3VSB 3.2 3.3 3.4 V Source Current ISC4 30 40 -- mA OC Current IOC4 40 80 -- mA Under Voltage Lockout V UV4 -- 75 -- % S3, S5 High Input Threshold V IL -- -- 0.75 V S3, S5 Low Input Threshold V IH 2.2 -- -- V Thermal Shutdown Limit TSHDN -- 140 -- °C Others DS9645-00 August 2007 www.richtek.com 7 RT9645 Preliminary Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution is highly recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. θJA is measured in the natural convection at T A = 25°C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. The case point of θJC is on the expose pad for the QFN package. www.richtek.com 8 DS9645-00 August 2007 RT9645 Preliminary Application Information Overview The RT9645 integrates two synchronous buck PWM controllers, two LDO controllers, and a dual power switching controller. It is primarily designed for computer applications powered from an ATX power supply. A 300kHz Synchronous Buck PWM controller with a precision 0.8V reference provides the proper Core voltage to the system main memory. A second 300kHz PWM Buck controller which requires an external MOSFET driver, provides the GMCH core voltage. One LDO controller regulates for FSB_VTT termination and other one is for the 3VSB power regulation. RT9645 also provides a dual power control 5VDL for S0 and S3 system power. Table 1 State VCC_DRV SB5V_DRV 5VDL S5 L H Off S3 L L On S0 H H On State S5 S3 S0 FSB_VTT Off Off On 3VSB On On On VDDQ Off On On ACPI State Transitions ACPI compliance is realized through the S3 and S5 sleep signals. Figure 3 shows how the RT9645 regulators are working during all state transitions. S5 to S0 Transition After AC power is plugged, the RT9645 stays in S5 state until the power button is pushed on. The S3 and S5 signals transit to HIGH and the +12V rail starts to ramp up. The RT9645 POR is executed as soon as PVIN voltage exceeds the threshold. In Intel mode, after an internal time delay TSS the VDDQ PWM will enable soft-start sequence and VCC_DRV will change to high. In AMD mode, VDDQ PWM is enabled after VDDQ_EN goes high. FSB_VTT soft-start will follow VDDQ soft-start with a time delay TSS in Intel mode, but in AMD mode FSB_VTT soft-start is triggered by VTT_EN becoming high. After VDDQ rail and the FSB_VTT softstart completes, all RT9645 regulators work in normal operation. Refer to Figure 3 and Figure 4 for the detailed timing diagrams. DS9645-00 August 2007 S0 to S3 Transition When S3 goes LOW but S5 still HIGH ,the RT9645 will disable FSB_VTT regulators. SB5V_DRV and VCC_DRV will go low to continually power on 5VDL rail. The memory power VDDQ is also maintained. S3 to S0 Transition When S3 transits from LOW to HIGH with S5 keeps HIGH and after the PVIN exceeds its POR threshold, in Intel mode the RT9645 will wait a time delay TSS and then softstarts FSB_VTT LDO. In AMD mode, FSB_VTT will softstart after VTT_EN goes high. S0 to S5 Transition When the system transits from active state to shutdown (S0 to S5) state, the RT9645 keeps powering 3VSB and turn off the other power regulators. Fault Protection The RT9645 monitors the VDDQ ,PWM2 and 3VSB regulator for under voltage and over-current protection. The FSB_VTT LDO regulator is monitored for under voltage protection. If RT9645 detects thermal Shutdown, over current (or Under Voltage) of 3VSB, the RT9645 will immediately shutdown all regulators and jump to first system state to redo power sequence. When VDDQ issues Under Voltage or Over Current or FSB_VTT issues Under Voltage, the RT9645 will immediately enters into S5 sleep state.This can only be cleared by toggling the S5 signal. VDDQ and PWM2 Over Current Protection The RT9645 senses the current flowing through low side MOSFET for over current protection (OCP). A 40μA current source flows through the external resistor ROCSET to PHASE pin causes 40μA x ROCSET voltage drop across the resistor. OCP is triggered if the voltage at PHASE pin (drop of lower MOSFET VDS) is lower than Rocset voltage drop when low side MOSFET conducting. Accordingly inductor current threshold for OCP is a function of conducting resistance of lower MOSFET RDS(ON) as : IOCSET = 40μA × ROCSET RDS(ON) www.richtek.com 9 RT9645 Preliminary To prevent OC form tripping in normal operation, ROCSET must be carefully chosen with : 1. Maximum RDS(ON) at highest junction temperature 2. Minimum IOCSET from specification table 3. IL(MAX) > IOUT(MAX) + Δ IL / 2 ΔIL = inductor ripple current If Low side MOSFET with RDS(ON) = 6mΩ is used, the OCP threshold current is about 20A. Once OCP is triggered, the RT9645 enters S5 sleep state. UGATE (20V/Div) LGATE FP _ LC = FZ _ ESR = 1 2π × ESR × COUT (3) FZ2 1 2π × R2 × C1 1 = 2π × (R1 + R3 ) × C3 (4) 1 (5) I LOAD (10A/Div) FP2 Time (250μs/Div) (2) FZ1 = FP1 = (1V/Div) (1) The compensation network consists of the error amplifier EA and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest DC gain, the highest 0dB crossing frequency (FC) and adequate phase margin. Typically, FC in range 1/5 to 1/10 of switching frequency is adequate. Higher FC will cause faster dynamic response. A phase margin in the range of 45°C to 60°C is desirable. The equations below relate the compensation network poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 7. (10V/Div) VOUT 1 2π LCOUT 2π × R2 × C1× C2 C1 + C2 1 = 2π × R3 × C3 (6) Figure 6. Over Cuuent Protection V IN OSC Feedback Compensation Figure 7 highlights the voltage-mode control loop for a synchronous buck converter. Figure 8 shows the corresponding Bode plot. The output voltage (VOUT) is regulated to the reference voltage. The error amplifier EA output (COMP) is compared with the oscillator (OSC) sawtooth wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (L and COUT). The modulator transfer function is the small-signal transfer function of VOUT/COMP. This function is dominated by a DC gain and the output filter (L and COUT), with a double pole break frequency at FP_LC and a zero at FZ_ESR. The DC gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage ΔVOSC. The break frequency FLC and FESR are expressed as Equation (1) and (2) respectively. www.richtek.com 10 Driver PWM Comparator ΔV OSC L V OUT - Driver + PHASE C OUT ESR Z FB V E/A EA + Z IN REF Z FB C2 C1 Z IN C3 R2 V OUT R3 R1 COMP FB EA + REF R FB Figure 7 DS9645-00 August 2007 RT9645 Preliminary 100 F Z1 F Z2 F P1 Generally, an inductor that limits the ripple current between 20% and 50% of output current is appropriate. Make sure that the output inductor could handle the maximum output current and would not saturate over the operation temperature range. F P2 80 Gain (dB) 60 Open Loop Error AMP Gain 40 20 20LOG (R1/R2) 20LOG (V IN /ΔV OSC ) 0 Modulator Gain -20 Output Capacitor Selection Compensation Gain Closed Loop Gain -40 F LC -60 10 100 1K F ESR 10K 100K 1M 10M Frequency (Hz) The output capacitors determine the output ripple voltage (%VOUT) and the initial voltage drop after a high slew rate load transient. The selection of output capacitor depends on the output ripple requirement. The output ripple voltage is described as Equation (8). ΔVOUT = ΔIL × ESR + 1 × 8 I2 Figure 8 OSC Feedback Loop Design Procedure Use these guidelines for locating the poles and zeros of the compensation network : 1. Pick Gain (R2/R1) for desired 0dB crossing frequency (FC). 2. Place 1st zero FZ1 below modulator double pole FLC (~75% FLC). VOUT × L × COUT (1 − D) (8) For electrolytic capacitor application, typically 90 to 95% of the output voltage ripple is contributed by the ESR of output capacitors. Paralleling lower ESR ceramic capacitor with the bulk capacitors could dramatically reduce the equivalent ESR and consequently the ripple voltage. Input Capacitor Selection 6. Check gain against error amplifier's open-loop gain. Use mixed types of input bypass capacitors to control the input voltage ripple and switching voltage spike across the MOSFETs. The buck converter draws pulsewise current from the input capacitor during the on time of upper MOSFET. The RMS value of ripple current flowing through the input capacitor is described as : 7. Pick RFB for desired output voltage. IIN(RMS) = IOUT × D × (1 − D) 8. Estimate phase margin and repeat if necessary. The input bulk capacitor must be cable of handling this ripple current. Sometime, for higher efficiency the low ESR capacitor is necessarily. Appropriate high frequency ceramic capacitors physically near the MOSFETs effectively reduce the switching voltage spikes. 3. Place 2nd zero FZ2 at modulator double pole FLC. 4. Place 1st pole FP1 at the ESR zero FZ_ESR 5. Place 2nd pole FP2 at half the switching frequency. Component Selection Components should be appropriately selected to ensure stable operation, fast transient response, high efficiency, minimum BOM cost and maximum reliability. MOSFET Selection of PWM Buck Converter Output Inductor Selection The selection of output inductor is based on the considerations of efficiency, output power and operating frequency. For a synchronous buck converter, the ripple current of inductor (%IL) can be calculated as follows : ΔIL = (VIN − VOUT ) × VOUT VIN × IOSC × L DS9645-00 August 2007 (7) The selection of MOSFETs is based upon the considerations of RDS(ON), gate driving requirements, and thermal management requirements. The power loss of upper MOSFET consists of conduction loss and switching loss and is expressed as : PUPPER = PCOND _ UPPER + PSW _ UPPER 2 = IOUT × RDS(ON) × D + 1 IOUT × VIN × (TRISE + TFALL ) × IOSC 2 www.richtek.com 11 RT9645 Preliminary where TRISE and TFALL are rising and falling time of VDS of upper MOSFET respectively. RDS(ON) and QG should be simultaneously considered to minimize power loss of upper MOSFET. The power loss of lower MOSFET consists of conduction loss, reverse recovery loss of body diode, and conduction loss of body diode and is expressed as : PLOWER = PCOND _ LOWER + PRR + PDIODE = IOUT × RDS(ON) × (1 − D) + QRR × VIN × fOSC Place the input capacitor directly to the drain of high-side MOSFET. The MOSFETs of linear regulator should have wide pad to dissipate the heat. In multilayer PCB, use one layer as power ground and have a separate control signal ground as the reference of the all signal. To avoid the signal ground is effect by noise and have best load regulation, it should be connected to the ground terminal of output. Furthermore, follows below guide lines can get better performance of IC : 2 + 1 IOUT × Vf × TDIODE × fOSC 2 where TDIODE is the conducting time of lower body diode. Special control scheme is adopted to minimize body diode conducting time. As a result, the RDS(ON) loss dominates the power loss of lower MOSFET. Use MOSFET with adequate RDS(ON) to minimize power loss and satisfy thermal requirements. MOSFET Selection of LDO The main criteria for selection of the LDO pass transistor is package selection for efficient removal of heat. Select a package and heatsink that maintains the junction temperature below the rating with a maximum expected ambient temperature. The power dissipated in the linear regulator is : `The IC needs a bypassing ceramic capacitor as a R-C filter to isolate the pulse current from power stage and supply to IC, so the ceramic capacitor should be placed adjacent to the IC. `Place the high frequency ceramic decoupling close to the power MOSFETs. `The feedback part should be placed as close to IC as possible and keep away from the inductor and all noise sources. `The components of bootstraps should be closed to each other and close to MOSFETs. `The PCB trace from Ug and Lg of controller to MOSFETs should be as short as possible and can carry 1A peak current. `Place all of the components as close to IC as possible. PD = IOUT(MAX) x (VIN - VOUT) where IOUT(MAX) is the maximum output current and VOUT is the nominal output voltage of LDO. Layout Consideration Layout is very important in high frequency switching converter design. If designed improperly, the PCB could radiate excessive noise and contribute to the converter instability. First, place the PWM power stage components. Mount all the power components and connections in the top layer with wide copper areas. The MOSFETs of Buck, inductor, and output capacitor should be as close to each other as possible. This can reduce the radiation of EMI due to the high frequency current loop. If the output capacitors are placed in parallel to reduce the ESR of capacitor, equal sharing ripple current should be considered. www.richtek.com 12 DS9645-00 August 2007 RT9645 Preliminary Outline Dimension D2 D SEE DETAIL A L 1 E E2 e b 1 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A A3 A1 Symbol 1 2 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Min Dimensions In Inches Max Min Max A 0.800 1.000 0.031 0.039 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 3.950 4.050 0.156 0.159 D2 2.300 2.750 0.091 0.108 E 3.950 4.050 0.156 0.159 E2 2.300 2.750 0.091 0.108 e L 0.500 0.350 0.020 0.450 0.014 0.018 V-Type 24L QFN 4x4 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)89191466 Fax: (8862)89191465 Email: [email protected] DS9645-00 August 2007 www.richtek.com 13