RT8110B Compact Wide Input Range Synchronous Buck DC/DC PWM Controller General Description Features The RT8110B is a compact fixed-frequency PWM controller with integrated MOSFET drivers for single power rail synchronous single-phase buck converter. This part features an internal regulator that allows wide input voltage range operation. The RT8110B utilizes voltage-mode control with internal compensation to simplify the converter design. An internal 0.8V reference voltage allows low output voltage application. The switching frequency is fixed at 400kHz to reduce the external passive component size to save board space. The RT8110B provides under voltage protection, current limit, over current protection and over temperature protection. The low-side MOSFET RDS(ON) is used to sense the inductor current for over current protection. z z z z z z z z z z z z Applications z Ordering Information z RT8110B z Package Type J8 : TSOT-23-8 z Lead Plating System G : Green (Halogen Free and Pb Free) z z Note : z Richtek products are : z RoHS compliant and compatible with the current require- PHASE BOOT 8 7 6 5 2 3 4 GND VCC For marking information, contact our sales representative directly or through a Richtek distributor located in your area. (TOP VIEW) UGATE Marking Information Pin Configurations VIN Suitable for use in SnPb or Pb-free soldering processes. LGATE ments of IPC/JEDEC J-STD-020. ` Set-top Box Power Supplies PC Subsystem Power Supplies Cable Modems, DSL Modems DSP and Core Communication Processor Power Supplies Memory Power Supplies Personal Computer Peripherals Industrial Power Supplies Low Voltage Distributed Power Supplies FB ` 10V to 28V Wide Input Voltage Range 0.8V Internal Reference Internal Soft Start High DC Gain Voltage Mode PWM Control Fixed 400kHz Switching Frequency Fast Transient Response Fully Dynamic 0 to 80% Duty Cycle Over Current Protection Under Voltage Protection Over Temperature Protection Tiny Package TSOT-23-8 RoHS Compliant and Halogen Free TSOT-23-8 DS8110B-02 April 2011 www.richtek.com 1 RT8110B Typical Application Circuit V IN + C2 RT8110B 1 VCC BOOT 5 C1 UGATE 4 R3 VIN C3 8 FB C BOOT Q1 PHASE 6 LGATE 2 3 GND L V OUT + 7 C IN C4 D Q2 C OUT C5 R1 R2 Functional Pin Description Pin No. Pin Name 1 VCC 2 LGATE 3 GND 4 UGATE 5 BOOT 6 PHASE 7 VIN 8 FB www.richtek.com 2 Pin Function Internal regulator output pin, typically 5.5V. VIN is regulated to VCC by the internal regulator. VCC is the main bias supply of the IC. This pin also provides power for the low side MOSFET gate driver. Connect a ceramic capacitor to this pin. The voltage at this pin is monitored for power on reset (POR). Gate Drive Pin for Low-Side MOSFET. Signal and Power Ground of the IC. All voltage levels are referenced with respect to this pin. Gate Drive Pin for High Side MOSFET. This pin provides power to the high-side MOSFET gate driver. A bootstrap circuit is used to drive the high side MOSFET. Switching Node of the Buck Converter. This pin is also used to monitor the voltage drop across the low side MOSFET for over current protection. This pin is internally connected to the collector of integrated BJT, which is designed to withstand 28V to provide a regulated 5.5V voltage to VCC pin. Inverting Input of the Error Amplifier. This pin is connected to the joint of output voltage divider resistors to set the output voltage. The voltage at this pin is also monitored for under voltage protection. DS8110B-02 April 2011 RT8110B Function Block Diagram VIN 5k VCC VCC Pre-Regulator PowerOn Reset VCC POR ROC OC PHASE + 0.8VREF 0.5V - UVP + SS FB IOC + +Gm - Soft-Start and Fault Logic S1L EO + - PWM Gate Control Logic + PH_M 1.5V VCC UGATE BOOT LGATE GND Oscillator DS8110B-02 April 2011 www.richtek.com 3 RT8110B Absolute Maximum Ratings z z z z z z z z z z z (Note 1) Supply Voltage, VCC -----------------------------------------------------------------------------------------------------Supply Voltage, VIN ------------------------------------------------------------------------------------------------------PHASE ---------------------------------------------------------------------------------------------------------------------BOOT -----------------------------------------------------------------------------------------------------------------------Input/Output Voltage -----------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C TSO-23-8 ------------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) TSO-23-8, θJA --------------------------------------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) ---------------------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------------------ Recommended Operating Conditions z z z 7V 33V −3V to 29V 34V 0.3V to 7V 0.382W 262°C/W 150°C 260°C −65°C to 150°C 2kV 200V (Note 4) Supply Voltage, VIN ------------------------------------------------------------------------------------------------------- 10V to 28V Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VIN = 5V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit -- 3 6 mA VIN Supply Current Power Supply Current IVIN UGATE, LGATE open Input Voltage Range VIN 10 -- 28 V Regulated Output Voltage VCC -- 5.5 -- V -- 4.7 -- V -- 0.9 -- V 0.784 0.8 0.816 V 320 400 480 kHz -- 2.2 -- V Power-On Reset VCC Threshold Voltage Rising VCC Threshold Hysteresis Reference Reference Voltage VREF Oscillator Free Running Frequency fSW Ramp Amplitude ΔVOSC Error Amplifier E/A Transconductance Gm Note 5 -- 0.3 -- ms Open Loop DC Gain AO Note 5 60 90 -- dB To be continued www.richtek.com 4 DS8110B-02 April 2011 RT8110B Parameter Symbol Test Conditions Min Typ Max Unit -- 3 4.5 Ω MOSFET Gate Driver VBOOT − PHASE = 5V VBOOT − VUGATE = 1V UGATE Drive Source RUGATEsr UGATE Drive Sink RUGATEsk VBOOT − PHASE = 5V -- 2 3 Ω LGATE Drive Source RLGATEsr VCC − VLGATE = 1V -- 4 6 Ω LGATE Drive Sink RLGATEsk VLGATE = 1V -- 2 4 Ω UGATE Drive Source IUGATEsr VBOOT −VUGATE = 5V -- 0.72 -- A UGATE Drive Sink IUGATEsk VUGATE −PHASE = 5V -- 0.82 -- A LGATE Drive Source ILGATEsr VVCC −VLGATE = 5V -- 0.65 -- A LGATE Drive Sink ILGATEsk VLGATE −GND = 5V -- 1.18 -- A VOC Sense Phase Pin Voltage -- −350 -- mV -- 80 -- % -- 0.5 0.6 V 1 3 6 ms VUGATE −PHASE = 1V Protection Over Current Threshold Maximum Duty Cycle UVP Threshold FB Voltage Falling Soft Start Soft-Start Interval TSS Note 1. Stresses listed as the above “ Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at TA = 25°C on a low effective single layer thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guarantee by design. DS8110B-02 April 2011 www.richtek.com 5 RT8110B Typical Operating Characteristics Power On Power On single rail, VIN = 12V, VOUT = 2.5V, ILOAD = 5A VIN (10V/Div) V CC (5V/Div) VOUT (2V/Div) single rail, VIN = 28V, VOUT = 2.5V, ILOAD = 5A VIN (20V/Div) V CC (5V/Div) VOUT (2V/Div) UGATE (50V/Div) UGATE (20V/Div) Time (2ms/Div) Time (2ms/Div) Power Sequence Under Voltage Protection dual rail, controller VIN is ready then power on converter input dual rail, power off converter input VOUT = 2.5V, ILOAD = 5A VIN (10V/Div) Converter VIN (10V/Div) VIN (10V/Div) Converter VIN (10V/Div) VOUT (2V/Div) VOUT (2V/Div) UGATE (20V/Div) VOUT = 2.5V, ILOAD = 0.5A UGATE (20V/Div) Time (2ms/Div) Time (4ms/Div) Over Current Protection Short Circuit Over Current Protection short output then power on Low-side MOSFET RDS(ON) = 20mΩ Low-side MOSFET RDS(ON) = 20mΩ VOUT (2V/Div) V CC (5V/Div) Inductor Current (20A/Div) Inductor Current (20A/Div) UGATE (20V/Div) UGATE (20V/Div) VOUT (100mV/Div) LGATE (10V/Div) Time (4ms/Div) www.richtek.com 6 Time (4ms/Div) DS8110B-02 April 2011 RT8110B Reference Voltage vs. Temperature 0.816 Switching Frequency vs. Temperature 480 VOUT = 2.5V, No Load Switching Frequency (kHz) Reference Voltage (V) 0.812 0.808 0.804 0.800 VIN = 28V 0.796 VIN = 12V 0.792 0.788 0.784 VOUT = 2.5V, No Load 460 440 420 VIN = 28V 400 VIN = 12V 380 360 340 320 -50 -25 0 25 50 75 100 125 Temperature (°C) -50 -25 0 25 50 75 100 125 Temperature (°C) VCC vs. Temperature 5.60 VOUT = 2.5V, No Load 5.58 VIN = 28V VCC (V) 5.56 5.54 VIN = 12V 5.52 5.50 5.48 5.46 -50 -25 0 25 50 75 100 125 Temperature (°C) DS8110B-02 April 2011 www.richtek.com 7 RT8110B Applications Information The RT8110B is a wide input voltage range, voltage-mode PWM controller with integrated MOSFET gate drivers for single-phase synchronous buck converter. It features tiny package and an internal regulator, which provides regulated VCC from a wide input range of VIN to power the controller. This part provides internal soft start, internal loop compensation and protection functions. start ends and FB will track VREF. The typical soft start time interval is 3ms. V OUT R1 R2 Transconductance Error Amplifier FB +GM + + V REF Internal VCC Regulator RT8110B can operate with input voltage range from 10V to 28V in single input power applications. The input voltage at VIN pin is internally connected to the integrated bipolar junction transistor and is then regulated to 5.5V by the internal regulator to support VCC. VCC is used as the power of internal control logic circuit and low-side MOSFET gate driver. It is recommended to add a 2.2μF ceramic capacitor to the VCC pin. Power-up and Soft Start The power-on-reset (POR) function continuously monitors the voltage at the VCC pin. When VCC rises and exceeds the POR threshold, the controller initiates its power-up sequence with continuous low-frequency, small-width pulses at UGATE (~6kHz). These pulses are used for converter power stage input voltage (VIN) detection. If VIN is applied, the voltage at PHASE pin will rise and fall due to these detection pulses. A digital counter and a comparator are used to record the number of times that voltage at PHASE pin exceeds the internally-defined voltage level (~1.5V). If the voltage at PHASE pin exceeds and below the internally-defined voltage level for two times, detection pulse stops and VIN is recognized to be ready. Once VIN is ready, soft-start will then initiate after a time delay. Otherwise the detection pulse at UGATE continues. RT8110B provides soft start function internally. Figure 1 shows the PWM comparator and the operational transconductance amplifier (OTA). The OTA has three inputs: reference voltage VREF, feedback voltage signal FB, and soft start signal SS. During the soft start interval, the feedback voltage signal tracks the SS signal. Because SS signal rises from zero in monotone, therefore the PWM duty cycle will increase gradually at start up to prevent large inrush current. When FB voltage reaches VREF, soft www.richtek.com 8 PWM Comparator + - Compensation Network SS Figure 1. Transconductance Amplifier and PWM Comparator. Bootstrap Circuit Figure 2 shows the bootstrap gate drive circuit supplied from VCC. The bootstrap circuit consists of bootstrap capacitor CBOOT and blocking diode DBOOT. The selection of these two components can be done after choosing the high-side MOSFET. The bootstrap capacitor must have a voltage rating that is able to withstand twice the maximum supply voltage. The capacitance is determined using the following equation : CBOOT = QGATE ΔVBOOTSTRAP where QGATE is the total gate charge of the high-side MOSFET, and ΔVBOOTSTRAP is the voltage drop allowed on the high-side MOSFET gate drive. For example, the total gate charge for MOSFET is about 30nC. For an allowed voltage drop of 300mV, the required bootstrap capacitance is 0.1μF. Referring to Figure 2, the bootstrap diode must be able to block the power stage supply voltage plus any peak ringing voltage at the PHASE pin when Q1 is turned on. Therefore, the voltage rating of the bootstrap diode should be at least 1.5 to twice of the power stage supply voltage. Since the RDS(ON) of MOSFET will be higher if the gateto-source driving voltage is lower, a bootstrap diode with larger forward voltage results in lower gate drive voltage, higher on-resistance and lower efficiency. Therefore, the forward voltage of the bootstrap diode should be low. Fast recovery diode or Schottky diode which has low forward voltage is recommended for the bootstrap diode. DS8110B-02 April 2011 RT8110B The OCP threshold is determined by the RDS(ON) of low- D BOOT VCC VCC Regulator V IN BOOT UGATE C BOOT Q1 side MOSFET. The inductor peak current IPEAK can be calculated using the following equation. IPEAK ≅ VOC RDS(ON) PHASE PWM + Comparator - LGATE Q2 Figure 2. Gate Driver and Bootstrap Circuit Current Limit and Over Current Protection (OCP) RT8110B provides current limit and over current protection. The low-side MOSFET on-resistance is used to sense the inductor current. Once the high-side MOSFET is turned off, the low-side MOSFET is turned on when dead time ends. Inductor current then flows through the lowside MOSFET and build a voltage drop across the drain and source (PHASE to GND). This voltage is sensed to monitor the inductor peak current. Note that IPEAK is the inductor peak current, therefore IPEAK should be set greater than IOUT(MAX) + (ΔI)/2 to prevent false tripping, where ΔI is the output inductor ripple current, and IOUT(MAX) is the maximum load current. Since MOSFET RDS(ON) increases with temperature, the controller will trip OCP/current limit earlier at high temperature. To avoid false tripping, considering the highest junction temperature of the MOSFET and calculate the OCP threshold to select RDS(ON). V IN V CC Q1 IOC R OC OC Comparator + - If the load current further increases, either over current protection or under voltage protection will be tripped. The over current protection will be tripped when the over current event occurs for continuously four PWM pulses. When OCP is triggered, both UGATE and LGATE go low, controller will initiate re-start in hiccup way. For OCP, controller has three times of hiccupped re-start before shutdown. Controller will latch off after three times of hiccup. DS8110B-02 April 2011 IL x R DS(ON) Q2 As shown in Figure 3, the over current threshold is determined internally by the current source IOC and the internal resistor ROC. The current source IOC flows through resistor ROC and builds voltage VOC (=IOC x ROC) which is referenced to the PHASE pin. When load current increase and the sensed PHASE voltage falls below VOC in one switching cycle, controller will treat this as an over current event. Each over current event will cause one UGATE PWM pulse to be prohibited, but has no influence on LGATE signal, it still keep switching. UGATE PWM pulse is permitted when over current event does not exist. If over current event does not occur in the next switching cycle, UGATE will switching again, or the UGATE pulse will still be prohibited. In this way, inductor peak current will be limited. L PHASE + IOC x R OC + Figure 3. Over Current Protection Mechanism Under Voltage Protection (UVP) After soft start completes, the FB voltage is monitored for UVP. The UVP function has a 10μs time delay and the threshold is typically 0.5V. If FB voltage falls below the threshold, UVP will be tripped, both UGATE and LGATE go low and then the hiccupped re-start will be initialized. The UVP re-start behavior is different from that of OCP; the controller will always initiate re-start in a hiccupped way. Over Temperature Protection (OTP) The RT8110B integrates thermal protection function. The over temperature protection is a latched protection and its threshold is typically 160°C. When OTP is triggered, controller shuts down, both high-side and the low-side MOSFET are turned off. www.richtek.com 9 RT8110B Input Capacitor Selection The input capacitor not only reduces the noise and voltage ripple on the input, but also reduces the peak current drawn from the power source. The input capacitor must meet the RMS current requirement imposed by the switching current defined by the following equation : IRMS = IOUT × VOUT × (VIN − VOUT ) VIN The input RMS current varies with load and input voltage, and has a maximum of half the output current when output voltage is equal to half the input voltage. In addition, ceramic capacitor is recommended for high frequency decoupling because of its low equivalent series resistance and low equivalent inductance. These ceramic capacitors should be placed physically between and close to the drain of high-side MOSFET and the source of the lowside MOSFET. The voltage rating is another key parameter for the input capacitor. In general, choose the voltage rating with 50% higher than the input voltage for the input capacitor to ensure the operation reliability. Feedback Compensation and Output Capacitor Selection The RT8110B is a voltage-mode PWM controller, it uses operational transconductance amplifier (OTA) with internal compensation network to eliminate external compensation components. The compensation network is used to shape the gain curve to obtain accurate dc regulation, fast load transient response and maintain stability. Figure 5 shows the Bode plot of the modulation gain, compensation gain and the close loop gain. A stable control loop has a close gain curve with a -20dB/decade slope at the crossover frequency and the phase margin is greater than 45°. Gain (dB) F LC F ESR FC Compensation Gain Freq.(Log) 0 F Z1 Close Loop Gain F P1 Modulation Gain F Z2 F P2 Figure 5. Bode Plot of Loop Gain. Output Voltage Setting The converter output voltage can be set by the external voltage divider resistors. Figure 4 shows the connection of the output voltage divider resistors. The controller will regulate the output voltage according to the ratio of the voltage divider resistors R1 and R2. Figure 6 illustrates the simplified synchronous buck converter using OTA with internal compensation. The feedback loop consists of Zin (R1, R2 and C1), OTA and the internal compensation network ZFB (RS, CS, CP). The value of internal compensation component is : RS ≈ 50k, CS ≈ 4nF, CP ≈ 10pF. V OUT Output Inductor Transconductance Error Amplifier GM + + V REF R1 FB L Q1 ESR + V IN DCR Q2 Output Capacitor R LOAD C OUT Optional R2 C3 Figure 4. Voltage Divider Resistors If R1 is given and the output voltage is specified, then R2 can be determined using the following equation : VREF ⎞ R2 = R1× ⎛⎜ ⎟ V − V REF ⎠ ⎝ OUT www.richtek.com 10 PWM Generator & MOSFET Driver C P ≈10pF Transconductance Error Amplifier GM + R S ≈50k + V REF C S≈ 4nF R1 R3 R2 Figure 6. Simplified Diagram for Synchronous Buck Converter with Internal Compensation Network DS8110B-02 April 2011 RT8110B Referring to Figure 5, the location of pole and zero of the LC filter and the compensation network can be determined using the following equations. The inductor and the output capacitor create a double pole at FLC : FLC = 1 2π × L × COUT The equivalent series resistance (ESR) of the output capacitor creates a zero at FESR : 1 FESR = 2π × ESR × COUT The internal compensation network introduces a zero at FZ1 : FZ1 = 1 2π × RS × CS The internal compensation network also introduces a pole at FP2 : 1 FP2 = C × CP ⎞ ⎛ 2π × RS × ⎜ S ⎟ ⎝ CS + CP ⎠ The external R3 and C3 introduces a zero at FZ2 : FZ2 = 1 2π × (R3 + R2 ) × C3 The external R3 and C3 introduces a pole at FP1 : FP1 = 1 2π × (R3 + R1 // R2 ) × C3 Since the internal compensation values are given, the close loop crossover frequency and phase margin can be obtained after inductance and capacitance are determined. External R3 and C3 are used to adjust the crossover frequency and phase margin. The typical design procedure is described as follows. Step 1 : Collect system parameters such as switching frequency, input voltage, output voltage, output voltage ripple, and full load current. Step 2 : Determine the output inductance value. The recommended inductor ripple current is between 10% and 30% of the full load output current. The inductance can be calculated using the following equation. VIN − VOUT V × OUT × 1 < L IFULL_LOAD × 0.3 VIN FSW < VIN − VOUT V × OUT × 1 IFULL_LOAD × 0.1 VIN FSW DS8110B-02 April 2011 Step 3 : Determine the output capacitance and the ESR. Neglecting the equivalent series inductance of the output capacitor, the output capacitance C OUT can be approximately determined using the following equations. VRIPPLE = VRIPPLE(ESR) + VRIPPLE(C) VRIPPLE(ESR) = IRIPPLE × ESR VRIPPLE(C) = IRIPPLE 8 × COUT × FSW Step 4 : Calculate the crossover frequency, phase margin and check stability. Calculate the frequency of FLC, FESR, FZ1, FZ2, FP1 and FP2 with selected inductance, capacitance and ESR. Then plot the Bode diagram of close loop gain to check crossover frequency and phase margin. In general, the crossover frequency FC is between 1/10 and 1/5 of the switching frequency (40kHz to 80kHz); and the phase margin should be greater than 45°. If the bandwidth and phase margin are not within an acceptable range, add R3 and C3 to slightly adjust the crossover frequency and phase margin. If the crossover frequency and phase margin still can't meet the requirement after tuning R3 and C3, re-select the ESR and COUT (mainly) or inductance value to change the location of FLC and FESR then repeat step 4. Note that the output voltage ripple and transient response should still meet the specification after changing ESR, COUT or L. Thermal Considerations For continuous operation, do not exceed absolute maximum operation junction temperature. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = (TJ(MAX) − TA) / θJA Where T J(MAX) is the maximum operation junction temperature, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of RT8110B, the maximum junction temperature is 125°C www.richtek.com 11 RT8110B and TA is the maximum ambient temperature. The junction to ambient thermal resistance θJA is layout dependent. For TSOT-23-8 packages, the thermal resistance θJA is 262°C/W on the standard JEDEC 51-3 single layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula : Layout Guidelines PCB layout plays an important role in converter design. PCB with carefully layout can help to decrease switching noise, have stable operation and better performance. The following guidelines can be used in PCB layout. ` Feedback voltage divider resistors, compensation RCs, bootstrap capacitor, bootstrap diode and ceramic capacitors for VIN and VCC should be placed close to the controller as possible. ` Keep the power loops as short as possible. The current transition from one device to another at high speed causes voltage spikes due to the parasitic components on the circuit board. Therefore, all the current switching loops should be kept as short as possible with wide traces to minimize the parasitic components. ` Minimize the trace length between the MOSFET and the controller. Since the drivers are integrated in the controller, the driving path should be short and wide to reduce the parasitic inductance and resistance. ` Place the ceramic capacitor physically close to the drain of the high-side FET and source of low-side FET. This can reduce the input voltage ringing at heavy load. ` Place the output capacitor physically close to the load. This can minimize the impedance seen by the load, and then improves the transient response. ` The voltage feedback trace should be away from the switching node. Keep the voltage feedback trace away from the PHASE node, inductor and MOSFETs, these switching node or components are noisy. PD(MAX) = (125°C − 25°C) / (262°C/W) = 0.382W for TSOT-23-8 package The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θJA. For RT8110B package, the Figure 7 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power dissipation allowed. Maximum Power Dissipation (W) 0.50 Single Layer PCB 0.45 0.40 0.35 0.30 TSOT-23-8 0.25 0.20 0.15 0.10 0.05 0.00 0 25 50 75 100 Ambient Temperature (°C) Figure 7. Derating Curves for RT8110B Package www.richtek.com 12 125 DS8110B-02 April 2011 RT8110B Outline Dimension H D L C B b A A1 e Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 1.000 0.028 0.039 A1 0.000 0.100 0.000 0.004 B 1.397 1.803 0.055 0.071 b 0.220 0.380 0.009 0.015 C 2.591 3.000 0.102 0.118 D 2.692 3.099 0.106 0.122 e 0.585 0.715 0.023 0.028 H 0.080 0.254 0.003 0.010 L 0.300 0.610 0.012 0.024 TSOT-23-8 Surface Mount Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. DS8110B-02 April 2011 www.richtek.com 13