RFMD RF2722_1

RF2722
Proposed
GSM/GPRS/EDGE RECEIVER
Part of the POLARISTM TOTAL RADIOTM Solution
RoHS Compliant & Pb-Free Product
Package Style: QFN, 32-Pin, 5x5
• Supports Both VLIF & DCR
GPO1
RX EN
CLK IN
SCLK
SDI
SSB
PCS Operation
GPO2
• GSM850, EGSM, DCS &
LNA VCC
Features
32
31
30
29
28
27
26
25
LNA 1P 1
24 DIG/FLT VCC
LNA1
Modes
Serial
Data
Interface
LNA 1N 2
• Integrated RF VCO
23 I OUT
LNA 2P 3
22 IB OUT
LNA2
• Integrated LNA’s Support
up to Four RF Bands
• EDGE Receive Compatible
LNA 2N 4
21 QB OUT
Quadrature
Mixer
Polyphase
Filter
DC
Correct
LNA 3P 5
20 Q OUT
LNA3
LNA 3N 6
19 TX EN
LNA 4P 7
18 TXB IN HB
Quadrature
Generator
LNA4
Applications
12
13
14
15
16
TX OUT HB
VT
VTC
VCO VCC
• EGSM/DCS/PCS
11
TX OUT LB
MIX VCC
• EGSM/DCS Handsets
17 TXB IN LB
10
VCO OUT
9
LO VCC
LNA 4N 8
Functional Block Diagram
Handsets
• GSM850/PCS Handsets
Product Description
• GSM850/EGSM/DCS/PCS
The RF2722 is a highly-integrated receiver IC supporting GSM, GPRS, and EDGE
cellular standards in the GSM850, EGSM, DCS, and PCS bands. The RF2722 supports both very-low intermediate frequency (VLIF) as well as direct conversion
receive (DCR) architectures, reducing external component count and eliminating
the need for IF SAW and RF interstage filters without compromising performance.
The IC includes: four LNA’s for multi-band support; an integrated voltage controlled
oscillator (VCO); automatic gain control (AGC); a quadrature downconverting mixer;
and, low and high band transmit buffers. Chip functionality, including IF AGC setting, is controlled through a three-wire serial data interface (SDI). The RF2722 is
Handsets
„
part of the POLARISTM TOTAL RADIOTM solution.
Ordering Information
RF2722
RF2722PCBA-41X
GSM/GPRS/EDGE Receiver
Fully Assembled Evaluation Board
Optimum Technology Matching® Applied
GaAs HBT
GaAs MESFET
InGaP HBT
SiGe BiCMOS
Si BiCMOS
SiGe HBT
GaAs pHEMT
Si CMOS
Si BJT
GaN HEMT
RF MICRO DEVICES®, RFMD®, Optimum Technology Matching®, Enabling Wireless Connectivity™, PowerStar®, POLARIS™ TOTAL RADIO™ and UltimateBlue™ are trademarks of RFMD, LLC. BLUETOOTH is a trademark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. ©2006, RF Micro Devices, Inc.
Rev A4 DS050919
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
1 of 26
RF2722
Proposed
Absolute Maximum Ratings
Parameter
Rating
Unit
Supply Voltage
-0.5 to +3.6
V
Storage Temperature
-40 to +150
°C
Input Voltage, any pin
3.6
V
Caution! ESD sensitive device.
Exceeding any one or a combination of the Absolute Maximum Rating conditions may
cause permanent damage to the device. Extended application of Absolute Maximum
Rating conditions to the device may reduce device reliability. Specified typical performance or functional operation of the device under Absolute Maximum Rating conditions is not implied.
RoHS status based on EUDirective2002/95/EC (at time of this document revision).
The information in this publication is believed to be accurate and reliable. However, no
responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any
infringement of patents, or other rights of third parties, resulting from its use. No
license is granted by implication or otherwise under any patent or patent rights of
RFMD. RFMD reserves the right to change component circuitry, recommended application circuitry and specifications at any time without prior notice.
Parameter
Min.
Specification
Typ.
Max.
Unit
Condition
Temp=-30°C to +85°C, VCC =2.7V to 3.0V, all
specifications referenced to 50Ω, unless specified differently.
Operating Range
Temperature (TOP)
-30
+85
°C
Frequency Range
GSM850 RX
869
894
MHz
Low Band
GSM850 TX
824
849
MHz
Low Band
EGSM RX
925
960
MHz
Low Band
EGSM TX
880
915
MHz
Low Band
DCS RX
1805
1880
MHz
High Band
DCS TX
1710
1785
MHz
High Band
PCS RX
1930
1990
MHz
High Band
PCS TX
1850
1910
MHz
High Band
3.0
V
Pins 9 (MIXVCC), 10 (LOVCC),
16 (VCOVCC), 24(DIG/FLT VCC), and
32 (LNAVCC).
10
μA
RX EN=0
Supply Voltage (VCC)
2.7
2.75
Power Down Current
Active Current
RX VLIF Mode
Low Band (850/950MHz)
64
77
91
mA
All circuits on, (LNA_CURR=10,
MIX_CURR=10)
High Band (1800/1900MHz)
63
76
90
mA
All circuits on, (LNA_CURR=00,
MIX_CURR=00)
Low Band (850/950MHz)
62.5
75.5
89.5
mA
All circuits on, (LNA_CURR=10,
MIX_CURR=10)
High Band (1800/1900MHz)
61.5
74.5
88.5
mA
All circuits on, (LNA_CURR=00,
MIX_CURR=00)
Low Band (850/950MHz)
19.5
25
mA
VCC =2.8V, PIN =+4dBm
High Band (1800/1900MHz)
24.5
32
mA
RX DCR Mode
TX Mode
Low side LO injection for all bands.
Except where noted, receiver specifications
defined from LNA input with I or Q channel differential as output.
Receiver System
Cascaded Noise Figure
Low Band (850/950MHz)
2.8
dB
+25°C, LNA_BYP=0
High Band (1850/1950MHz)
3.2
dB
+25°C, LNA_BYP=0
2 of 26
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
Rev A4 DS050919
RF2722
Proposed
Low Band (850/950MHz)
4.8
dB
-30-85°C, LNA_BYP=0
High Band (1850/1950MHz)
5.2
dB
-30-85°C, LNA_BYP=0
Noise Figure with 3MHz Blocker
Low Band (850/950MHz)
3.8
4.8
dB
+25°C; -26dBm at LNA input.
High Band (1800/1900MHz)
4.7
5.7
dB
+25°C; -29dBm at LNA input.
Cascaded IIP3
Low Band (850/950MHz)
-12
dBm
High Band (1850/1950MHz)
-11
dBm
Low Band (850/950MHz)
-15
dBm
High Band (1850/1950MHz)
-14
dBm
Rev A4 DS050919
+25°C; LNA_BYP=0;
Interferers at 0.8MHz and 1.6MHz
-30-85°C; LNA_BYP=0;
Interferers at 0.8MHz and 1.6MHz
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
3 of 26
RF2722
Proposed
Parameter
Min.
Specification
Typ.
Max.
Unit
Condition
Receiver System, cont’d
Cascaded IIP2 (VLIF Improvement
not included)
Low Band (850/950MHz)
1 tone (IIP21)/2 tone (IIP21)
LNA_BYP=0
50
58
dBm
1 tone
44
52
dBm
2 tone
50
58
dBm
1 tone
44
52
dBm
2 tone
Low Band (850/950MHz)
-22
-20
dBm
Minimum Gain
High Band (1850/1950MHz)
-23
-21
dBm
Minimum Gain
Low Band (850/950MHz)
54.5
57.5
60.5
dB
LNA_BYP=0;
Polyphase Gain=0/12.6/7.4/1/8.4dB
High Band (1850/1950MHz)
53.5
56.5
59.5
dB
LNA_BYP=0;
Polyphase Gain=0/12.6/7.4/1/8.4dB
Low Band (850/950MHz)
1.5
dB
+25°C; LNA_BYP=0; -26dBm at LNA input,
with gain settings for a -99dBm wanted signal.
High Band (1850/1950MHz)
1.0
dB
+25°C; LNA_BYP=0; -29dBm at LNA input,
with gain settings for a -99dBm wanted signal.
High Band (1850/1950MHz)
Cascaded P1dB
Cascaded Gain
Gain Compression with 3MHz
Blocker
LNA Gain Step
Low Band (850/950MHz)
15
16
17
dB
LNA_BYP=1
High Band (1850/1950MHz)
17
18
19
dB
LNA_BYP=1
Low Band (850/950MHz)
-110
-100
dBm
At the LNA input.
High Band (1850/1950MHz)
-110
-100
dBm
At the LNA input.
Low Band (850/950MHz)
-22
-20
dB
High Band (1850/1950MHz)
-24
-22
dB
Low Band (850/950MHz)
-6
-4
dB
High Band (1850/1950MHz)
-16
-14
dB
Low Band (850/950MHz)
-22
-20
dB
High Band (1850/1950MHz)
-45
-43
dB
LO Leakage
2LO Suppression
LNA_BYP=0
3LO Suppression
LNA_BYP=0
5LO Suppression
LNA_BYP=0
Image Balance
Low Band (850/950MHz)
32
36
dB
High Band (1850/1950MHz)
32
36
dB
LNA Input Impedance
Low Band (850/950MHz)
82-j156
Ω
High Band (1850/1950MHz)
38-j66
Ω
LNA Input Return Loss
Low Band (850/950MHz)
-10
dB
With external match to 100Ω
High Band (1850/1950MHz)
-10
dB
With external match to 100Ω
+3.2
dB
For any recommended AGC setting across frequency and temperature in a single band, for
power levels between -110dBm and -48dBm,
assuming 1 gain calibration point per band.
Absolute Gain Accuracy
4 of 26
-3.2
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
Rev A4 DS050919
RF2722
Proposed
Relative Gain Accuracy
Rev A4 DS050919
-1
+1
dB
For any 20dB gain step, using recommended
AGC gain settings for receive power levels in
the range -110dBm and -48dBm.
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
5 of 26
RF2722
Proposed
Parameter
Min.
Specification
Typ.
Max.
Unit
VCO+LO Chain
Condition
Buffers, divide-by-2, divide-by-4, divide-by-8
LO Frequency
869
960
1805
VCOHL=0
1990
MHz
VCOHL=1
-16.2
dBm
2kΩ//5pF load
VCO_OUT=VCO/8
Output Level to Synth
-18.6
Output Frequency to Synth
434.5
497.5
MHz
0.5
2.0
V
-107
MHz/V
Tuning Voltage
Tuning Line Input Impedance
-17.4
MHz
12
KVCO*
-27
MΩ
LO Phase Noise, Low Band
DC measurement
GSM850/EGSM
0.6MHz
-129.2
-127.2
dBc/Hz
dBc/Hz
1.6MHz
-138.4
-136.4
3.0MHz
-142.8
-140.8
dBc/Hz
10.0MHz
-145.0
-143.0
dBc/Hz
LO Phase Noise, High Band
DCS/PCS
0.6MHz
-123.0
-121.0
1.6MHz
-133.1
-131.1
dBc/Hz
dBc/Hz
3.0MHz
-137.9
-135.9
dBc/Hz
10.0MHz
-140.0
-138.0
dBc/Hz
* When used with an RF600X, the product of KVCO xCharge Pump Current is calibrated to be within 5% of nominal value.
6 of 26
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
Rev A4 DS050919
RF2722
Proposed
Min.
Specification
Typ.
Max.
Center Frequency
99.5
107.0
114.5
kHz
Half-Bandwidth
180
200
220
kHz
In-Band Ripple
0.35
dB
130kHz Half-Bandwidth
Group Delay
1.3
us
130kHz Half-Bandwidth
Parameter
Unit
Condition
Polyphase Filter
(4th Order)
VLIF Mode
Integrated Attenuation
200kHz
5.0
dB
400kHz
23.0
dB
600kHz
38.0
dB
>600kHz
38.0
dB
I/Q Phase Error
1.0
1.8
°
Entire RX chain
I/Q Amplitude Error
0.1
0.25
dB
Entire RX chain
20
pF
Output Capacitive Load
Output Resistive Load
30
Maximum Output Voltage Swing
1
Output Common Mode Voltage
1.23
Static DC Offset
-160
1.26
kΩ
30kΩ RF6001/3 RX A/D input impedance.
VP-P
Differential
1.29
V
+160
mV
Uncorrected
Direct Conversion (DCR) Mode
Center Frequency
-7.5
0
+7.5
kHz
Half-Bandwidth
180
200
220
kHz
In-Band Ripple
0.35
dB
130kHz Half-Bandwidth
Group Delay
1.3
us
130kHz Half-Bandwidth
Integrated Attenuation
200kHz
5.0
dB
400kHz
23.0
dB
600kHz
38.0
dB
>600kHz
38.0
dB
I/Q Phase Error
1.0
1.8
°
Entire RX chain
I/Q Amplitude Error
0.1
0.25
dB
Entire RX chain
20
pF
Output Capacitive Load
Output Resistive Load
30
Maximum Output Voltage Swing
1
Output Common Mode Voltage
1.20
DC Offset (Uncorrected)
-160
Rev A4 DS050919
1.23
kΩ
30kΩ RF6001/3 RX A/D input impedance.
VP-P
Differential
1.26
V
+160
mV
Uncorrected
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
7 of 26
RF2722
Parameter
Proposed
Specification
Typ.
Max.
-0.3
0
+0.3
dB
C_G1_1:0=11
-6.1
-5.5
-4.9
dB
C_G1_1:0=10
-14.0
-13.0
-12.0
dB
C_G1_1:0=00
18.6
18.7
18.8
dB
F_G1_3:0=0111
17.5
17.6
17.7
dB
F_G1_3:0=0110
Min.
Unit
Condition
Polyphase Filter
(4th Order), cont’d
Polyphase Input Attenuator
(DCR)
(Midband Gain)
Gain
First Pole (DCR)
(Midband Gain)
Gain
16.5
16.6
16.7
dB
F_G1_3:0=0101
15.5
15.6
15.7
dB
F_G1_3:0=0100
F_G1_3:0=0011
14.5
14.6
14.7
dB
13.5
13.6
13.7
dB
F_G1_3:0=0010
12.5
12.6
12.7
dB
F_G1_3:0=0001
11.5
11.6
11.7
dB
F_G1_3:0=0000
10.4
10.5
10.6
dB
F_G1_3:0=1111
9.4
9.5
9.6
dB
F_G1_3:0=1110
8.4
8.5
8.6
dB
F_G1_3:0=1101
7.4
7.5
7.6
dB
F_G1_3:0=1100
6.4
6.5
6.6
dB
F_G1_3:0=1011
5.4
5.5
5.6
dB
F_G1_3:0=1010
4.4
4.5
4.6
dB
F_G1_3:0=1001
3.4
3.5
3.6
dB
F_G1_3:0=1000
Second Pole (DCR)
(Midband Gain)
Gain
7.3
7.4
7.6
dB
S_G2_0=1
-0.9
-0.7
-0.5
dB
S_G2_0=0
Third Pole (DCR)
(Midband Gain)
Gain
0.9
1.0
1.1
dB
S_G2_1=1
-6.9
-6.8
-6.7
dB
S_G2_1=0
13.9
14.3
14.7
dB
S_G3_1:0=11
8.1
8.4
8.7
dB
S_G3_1:0=01
2.2
2.5
2.8
dB
S_G3_1:0=00
Fourth Pole (DCR)
(Midband Gain)
Gain
8 of 26
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
Rev A4 DS050919
RF2722
Proposed
Parameter
Min.
Specification
Typ.
Max.
Unit
Condition
DC Offset Correction
Residual DC Error
-20
+20
DC Correction Time
DC Offset Drift Referred to the LNA
Input
CLK IN Frequency
mV
Following DC offset correction. Differential
measurement.
20
μs
-126
dBm
Max gain measured in a window 150μs to
730μs after RXEN is activated.
MHz
CLKF=0
26
TX Buffer
Low Band
Input Power
3
6
dBm
7.7
8.8
dBm
1.1
dB
5.2
7.2
9.3
mA
DC with no RF input
14
19.5
25
mA
PIN =+4dBm
Saturated Output Power
6.6
Output Power Variation
-1.1
DC Current Drain
RF Current Drain
Phase Noise
-167
Input VSWR
dBc/Hz
3:1
Output VSWR
20MHz offset
PIN =+4dBm
2:1
Load VSWR
PIN =+4dBm
PIN =+4dBm
3:1
PIN =+4dBm
Reverse Isolation
20
dB
TXEN=H
Forward Isolation
20
dB
TXEN=L
High Band
Input Power
3
Saturated Output Power
4.9
Output Power Variation
-1.6
DC Current Drain
RF Current Drain
Phase Noise
6.5
6
dBm
8.1
dBm
1.6
dB
mA
DC with no RF input
mA
PIN =+4dBm
8
11
13.8
18
24.5
32
-160
Input VSWR
PIN =+4dBm
dBc/Hz
3:1
PIN =+4dBm
Output VSWR
2:1
PIN =+4dBm
Load VSWR
3:1
PIN =+4dBm
Reverse Isolation
35
dB
TXEN=H
Forward Isolation
28
dB
TXEN=L
Rev A4 DS050919
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
9 of 26
RF2722
Parameter
Proposed
Min.
Specification
Typ.
Max.
Unit
Serial Interface
Input High Voltage (VIH)
Applies to pins SCLK, SDI and SSB.
0.7*VCC
V
Input Low Voltage (VIL)
0.3*VCC
V
Input High Current (IIH)
5
μA
5
μA
Input Low Current (IIL)
Setup Time (TSU)
25
ns
Hold Time (TH)
10
ns
Rise/Fall Time (TRF)
Clock to Select Time (TCS)
Condition
10
10
ns
ns
Clock Pulse Width High (TCWH)
50
ns
Clock Pulse Width Low (TCWL)
50
ns
VCC -0.05
V
1mA load
VCC -0.50
V
10mA load
0.05
V
1mA load
0.50
V
10mA load
5
ns
Digital Output Drivers
Output High Voltage (VOH)
Apply to pins: GPO1, GPO2
Output Low Voltage (VOL)
Output Rise/Fall Time (TRFO)
26MHz Reference
Clock Input
Applies to CLKIN.
Frequency Range (FR)
Input Level (VINR)
26
600
Input Impedance (ZINR)
Transient Startup Time
Input Low Voltage (VIL)
mVP-P
AC-coupled mode
49kΩ//
480fF
Interface Voltage
Input High Voltage (VIH)
MHz
VCC/2
V
250
ns
0.7VCC
0.3VCC
Internal bias
V
DC-coupled mode
V
DC-coupled mode
Package Drawing
10 of 26
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
Rev A4 DS050919
RF2722
Proposed
Pin
1
Function
LNA 1P
Description
Interface Schematic
RF input to LNA 1. Internally matched for 800MHz to 1000MHz operation.
This pin possesses a DC voltage with respect to ground, and a series blocking cap may be required in some applications.
BIAS
+
-
2
LNA 1N
3
LNA 2P
Complementary input to pin 1. This pin possesses a DC voltage with
See Pin 1.
respect to ground, and a series blocking cap may be required in some
applications.
RF input to LNA 2. Internally matched for 800MHz to 1000MHz operation.
This pin possesses a DC voltage with respect to ground, and a series blockBIAS
ing cap may be required in some applications.
+
-
4
LNA2N
5
LNA 3P
Complementary input to pin 3. This pin possesses a DC voltage with
respect to ground, and a series blocking cap may be required in some
applications.
RF input to LNA 3. Internally matched for 1800MHz to 2000MHz operation. This pin possesses a DC voltage with respect to ground, and a series
blocking cap may be required in some applications.
See Pin 3.
BIAS
+
-
6
LNA 3N
7
LNA 4P
Complementary input to pin 5. This pin possesses a DC voltage with
respect to ground, and a series blocking cap may be required in some
applications.
RF input to LNA 4. Internally matched for 1800MHz to 2000MHz operation. This pin possesses a DC voltage with respect to ground, and a series
blocking cap may be required in some applications.
See Pin 5.
BIAS
+
-
8
LNA 4N
9
MIX VCC
Complementary input to pin 7. This pin possesses a DC voltage with
respect to ground, and a series blocking cap may be required in some
applications.
Supply for the quadrature mixer.
See Pin 7.
MIX VCC
LOAD
10
LO VCC
VCO divider supply.
LO VCC
BIAS
11
VCO OUT
Output from the VCO to drive the synthesizer input. This is the VCO divided
by 8.
VCO OUT
12
TXB OUT LB
Low band TX buffer output.
TXB OUT LB
Rev A4 DS050919
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
11 of 26
RF2722
Pin
13
Function
TXB OUT HB
Proposed
Description
Interface Schematic
High band TX buffer output.
TXB OUT HB
14
VT
Tuning control line for the VCO. Analog input.
VCO VCC
VT
VCO VCC
15
VTC
Coarse VCO tuning control driven by RF6001. Digital input.
VTC
16
VCO VCC
Supply for the RF VCO.
VCO VCC
LOAD
17
TXB IN LB
18
TXB IN HB
19
TX EN
20
Q OUT
TX buffer low band input. This is a high impedance voltage-driven input
designed to be driven by the RF6001/3 TXVCO output.
TX buffer high band input. This is a high impedance voltage-driven input
designed to be driven by the RF6001/3 TXVCO output.
TX buffer enable. If the TX SEL (CRX1[2]) bit is set high, the TX buffers are
enabled by this pin. If the TX SEL bit is set low, this pin has no effect on the
activation of the TX buffers. (See register map for more information.) The
TX buffers are enabled by setting this pin high. The TX buffers are disabled
by setting this pin low.
Q-channel differential IF output.
Q OUT
21
QB OUT
Complementary output to Q OUT.
QB OUT
22
IB OUT
Complementary output to I OUT.
IB OUT
23
I OUT
I-channel differential IF output.
I OUT
24
DIG/FLT VCC
Supply for all digital circuitry.
Supply for the filter.
DIG/FLT VCC
LOAD
12 of 26
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Rev A4 DS050919
RF2722
Proposed
Pin
25
Function
SSB
Description
Interface Schematic
SDI enable input (active low).
SSB
26
SDI
SDI data input.
SDI
27
SCLK
SDI clock input.
SCLK
28
CLK IN
Clock input for the DC offset correction system. A 26MHz clock must be
applied to this pin for proper operation of the DC offset correction system.
29
RX EN
Set to VCC to activate the IC. Set to GND to deactivate.
30
GPO1
General purpose digital output 1. Controlled via SDI programming.
CLK IN
RX EN
GPO1
31
GPO2
General purpose digital output 2. Controlled via SDI programming.
GPO2
32
RX VCC
Supply for the LNA’s.
RX VCC
BIAS
Rev A4 DS050919
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support, contact RFMD at (+1) 336-678-5570 or [email protected].
13 of 26
RF2722
Proposed
Package Drawing
-A-
2 PLCS
0.10 C A
0.05 C
0.90
0.85
5.00 SQ.
2.50 TYP.
0.70
0.65
0.05
0.00
2 PLCS
0.10 C B
3
12°
MAX
2 PLCS
0.10 C B
-B-
-C-
SEATING
PLANE
2.37 TYP.
2 PLCS
0.10 C A
4.75 SQ.
0.10 M C A B
0.60
0.24
TYP.
0.30
0.18
2
Pin 1 ID
R.20
Shaded lead is pin 1.
Dimensions in mm.
3.45
SQ.
3.15
0.50
0.30
0.50
14 of 26
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Rev A4 DS050919
RF2722
Proposed
LNA VCC
GPO2
GPO1
RX EN
CLK IN
SCLK
SDI
SSB
Detailed Functional Block Diagram
32
31
30
29
28
27
26
25
LNA 1P 1
24 DIG/FLT VCC
LNA1
Serial
Data
Interface
LNA 1N 2
23 I OUT
LNA 2P 3
22 IB OUT
LNA2
LNA 2N 4
21 QB OUT
Quadrature
Mixer
Polyphase
Filter
DC
Correct
LNA 3P 5
20 Q OUT
LNA3
LNA 3N 6
19 TX EN
LNA 4P 7
18 TXB IN HB
Quadrature
Generator
LNA4
Rev A4 DS050919
9
10
11
12
13
14
15
16
LO VCC
VCO OUT
TX OUT LB
TX OUT HB
VT
VTC
VCO VCC
17 TXB IN LB
MIX VCC
LNA 4N 8
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support, contact RFMD at (+1) 336-678-5570 or [email protected].
15 of 26
RF2722
Proposed
Application Schematic
26 MHz Clock Input
RX Enable from RF6001/3 or RX Controller
GPO1
GPO2
VCC
To Serial Port
Controller
150 Ω EGSM or
GSM850 RF SAW
Filter
32
31
30
29
28
27
26
25
1
EGSM/GSM850
RF INPUT
LNA1
Serial
Data
Interface
2
150 Ω EGSM or
GSM850 RF SAW
Filter
23
3
EGSM/GSM850
RF INPUT
VCC
24
22
To RF6001/3 or
VLIF-to-Baseband
Converter
LNA2
4
21
Quadrature
Mixer
100 Ω PCS or
DCS RF SAW Filter
Polyphase
Filter
DC
Correct
5
PCS/DCS
RF INPUT
20
LNA3
6
100 Ω DCS or
PCS RF SAW Filter
7
PCS/DCS
RF INPUT
Quadrature
Generator
LNA4
8
9
10
11
12
13
14
15
19
TX EN
18
HB TXVCO Output from RF6001/3
17
LB TXVCO Output from RF6001/3
16
VCC
VCC
To RF6001/3 or PLL
(See Note)
4.7 μF
10 nF
5
VIN
National LP2985
2.8 V Low-Dropout Regulator
or Equivalent
1
3 CE
2 GND
VO
BP 4
To RF31XX PA HB Input
To RF31XX PA LB Input
VBATT
16 of 26
NOTE
If external PLL is used for RF2722 VCO Control, VTC must be manually
toggled to place the VCO in appropriate frequency range to achieve lock.
2.2 μF
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support, contact RFMD at (+1) 336-678-5570 or [email protected].
Rev A4 DS050919
Proposed
RF2722
Application Information
Functional Description
The RF2722 receiver IC will support GSM and EDGE cellular standards.
Four Low Noise Amplifiers (LNA’s) are provided to accommodate various combinations of up to four bands. The four LNA’s
share a common quadrature mixer. The active LNA is selected and may be bypassed through the Serial Data Interface (SDI).
An RX Local Oscillator (VCO) is provided. The VCO is fully integrated including an internal resonator and is band-selectable to
cover the GSM850, EGSM, DCS, and PCS bands.
The desired signal is converted to either a VLIF (100kHz/120kHz) or directly to DC, as determined by the setting of bit 1 in SDI
register CF.
Once downconverted, the signal is filtered by an active RC Polyphase bandpass filter. The purpose of this filter is to provide
some rejection to interfering signals such that the dynamic range of the A/D converters will not be compromised.
The RF2722 also includes two reverse isolation dual-band buffer amplifiers. These buffers are suitable for use in the transmit
path between the VCO output and the PA input to improve transmit performance. The RF2722 accepts single-ended inputs
from the RF6001/3 and provides single-ended outputs to the PA.
DC Correction Operation
The Polaris RF2722 VLIF/DCR IC will reduce the residual DC error of the I and Q channels to less than 20mV within 20usec
assuming that no input signal is present during the DC adapt time. The DC correction system will activate on the rising edge of
RX_EN if the SDI bit DC_EN is programmed true. Programming the SDI bit DC_ST true can also activate the DC correction system. In this case the SDI bit DC_ST will automatically return to a false state once the DC correction system is activated.
The RF6001/3 also has an RX_EN pin that normally is set high at the same time as the RX_EN of the RF2722.
The DC correction system of the RF2722 will run for DC_TIME1 cycles of the clock present on CLK_IN divided by 16. This
should be set for approximately 20usec. With a 26MHz clock on CLK_IN the setting of DC_TIME1 will be 20H. Given the low
levels of LO leakage to the LNA inputs of the RF2722, the coarse DC adapt will be performed when RX_EN rises with the LNAs
disabled. The residual DC error due to LO leakage when the LNAs are enabled will be less than 5mV. Once completed the DC
correction outputs of the RF2722 will be held until power is removed from the IC or until another DC correction command is
issued.
During operation of the DC correction system the input signal should be muted so that the coarse DC correction system does
not attempt to lock to the instantaneous signal level. This can be accomplished by disabling all LNAs. This mode is selected if
the LND SDI bit is programmed true. This is performed for DC_TIME2 clock cycles of CLK_IN divided by 16 beginning at the DC
correction command time so that the RF2722 will have sufficient time to complete DC correction.
If the radio employs a T/R switch then the T/R switch can also be used to disable the signal instead of or in addition to disabling the LNAs. The RF2722 can be used to automatically disable the T/R switch if the SDI bit TRD is programmed true. In this
case it is assumed that GPO1 and GPO2 provide on/off control for each of the possible bands of the receive side of the T/R
switch. During the DC control time interval set by DC_TIME2 the outputs of GPO1 and GPO2 will be overridden by the SDI register TRDC. The bits of this register can be set to 0 or 1 as needed by the particular T/R switch implementation to deactivate the
receiver inputs. After DC_TIME2 has expired the normally programmed GPO states will return.
After the coarse DC adapt time has elapsed then the RF6001/3 will require an additional time of approximately 50usec to
complete the fine digital DC correction.
Note that the input signal may be present during the final DC correction time of the RF6001/3. For VLIF modes this will not
cause a DC problem since the RF6001/3 does an averaging of the DC error and there will be few components of the signal
Rev A4 DS050919
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17 of 26
RF2722
Proposed
near DC. In addition, the RF6001/3 will notch out 100kHz converted DC components for channel bandwidths less than or
equal to 85kHz. The RF6003 will also notch out 120kHz converted DC components for channel bandwidth of 90kHz. This is
only useful in VLIF mode.
In DCR mode there may be significant spectral content near DC during the final adapt of the RF6001/3. This may result in a
significant DC component that will track the input desired signal level. It is assumed that the baseband DSP will be able to
remove any such static DC error. In addition, if the DC adapt of the RF6001/3 is performed during the guard times then the
spectral content of the input signal should be a tone in the region of 50kHz to 70kHz and should not interfere with the DC
adapt process.
If DC_TIME2 is extended to encompass the fine DC adapt time of the RF6001/3 then the input signal will not interfere with the
adapt process as the LNAs will be muted. However, if there is any residual LO leakage into the LNA input then this error will
remain after the DC correction process. This may be a smaller residual error than that due to the input signals.
A diagram depicting the composite DC correction and RX startup of the RF2722 and RF6001/3 is presented below.
System
Warm-Up
t=-120usec
t=-140usec
Activate RF2722/ RF2722 DCOCl
completed
RF6001/3
t=-90usec
Initial Cal
completed
t=-20usec
RF6001/3
PLL lock
completed
t=0usec
RF6001/3 DCOC
completed
BURST STARTS
t=42
RF6001/3 filter
data flushed
receive valid
data
RX_EN,
EN_SE
RF2722
Turn on
Initial
Calibration
PLL
Lockup
RF2722
RXI, Q
DCOC
RF6001/3
RXI,Q
DCOC
Valid
Data
DC_TIME1
<20mV DC
DC_TIME2
<80uV DC
42 usec latency
GPO Control
The RF2722 allows the GPOs to switch to an alternate setting defined by TRDC during RX DC offset correction when TRD is programmed high. This is triggered by the rising edge of RX_EN pin and terminated by the expiration of DC_TIME2 in the RF2722.
This mode of operation is used to turn off the LNAs or redirect the T/R switch to TX mode during the DCOC time interval so that
the signal present from the previous time slot or LO leakage will not cause an error in the DCOC.
18 of 26
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Rev A4 DS050919
RF2722
Proposed
In TX mode the RF2722 can also switch to an alternate set of GPO settings defined by TRTXA at the rising edge of TX_EN pin
when TRTX_EN is programmed high. This functionality is used to redirect the T/R switch to RX mode during the synthesizer lock
time so that the PA output due to feed-through from the VCO will not violate the ETSI time-mask specification.
RX Mode
When RXEN rises, DC_TIME2 starts in the RF2722 and the part switches to the alternate GPO settings defined in TRDC. Once
the timer expires then the settings of the GPO's revert back to the originally programmed GPO SDI fields.
RXEN
DC_TIME2
GPO
TRDC
GPO1,2
TX Mode
When TXEN rises, the RF2722 GPOs switch to the alternate GPO settings defined in TRTXA. When TXEN falls, the RF2722 GPO
settings revert back to the originally programmed GPO SDI fields.
TX_EN
GPO
GPO1,2
TRTXA
GPO1,2
Device Control and Programming
The Polaris RF2722 VLIF/DCR IC provides a serial interface for programming the control settings. The interface consists of
eight registers that are accessed individually via a six-bit address word. (Two registers are unused at this time and are included
for future expansion.) The register map is shown below. Each register plus the six address bits requires an 18-bit transfer
(except register CF, which has 18 bits and so requires a 24-bit transfer). Additional 'padding' bits can be added between the
address bits and the data bits, if longer transfer lengths are needed. Since the RF2722 will be most likely used with the
RF6001/3 then it is expected that six such padding bits will be used in each transfer to bring the total number of bits up to 24.
This will then match the programming width of the RF6001/3.
Address
Register
Description
100000
CRX1
AGC, standby modes, LO phase cal
100001
CRX2
DCOC and GPO
100010
CRX3
DCOC
100011
CRX4
DCOC
100100
CRX5
LNA, VCO, mixer current settings, Gain cal
100101
CF
100110
Reserved
Reserved for future use.
100111
Reserved
Reserved for future use.
011111
Reset
Rev A4 DS050919
Gain settings for the polyphase filters and LNA’s.
Writing this address resets all SDI bits to their default states.
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19 of 26
RF2722
Proposed
At power up the SDI address 011111 should be written to set up the default reset states of all registers. Note that programmed
settings will be lost if power to the part is removed.
The figure below shows a timing diagram for the serial interface. The slave select (SS) pin is normally high. A serial transfer is
initiated by taking SS low. The address and data bits on the serial data in (SDI) pin are shifted in on rising edges of the serial
clock (SCLK) pin. Twelve data bits follow the four address bits. The data is latched and changes take effect on the rising edge
of SS. Refer to the Electrical Specifications for the timing requirements.
Tcs
Tcwh
Tcwl
Tcs
...
...
...
MSB
Tsu
20 of 26
LSB
Th
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Tcs
Rev A4 DS050919
Proposed
RF2722
Receiver Configuration Register 1 (CRX1) - Address 100000
Location
Bit Name Default
Description
CRX1(11)
reserved
0
Reserved
CRX1(10:7)
LO_PH_CAL
0000
CRX1(6)
CLK BYP
1
If set to zero, then the CLK_IN pin is AC-coupled. If set to one, then the CLK_IN pin is
DC-coupled.
CRX1(5)
CLKF
0
Input clock frequency select. (Must be set to 26MHz for normal
operation.) Programming this bit high activates a divide-by-two function on the
CLK_IN pin. Programming this bit low deactivates the divide-by-two function. The
DC offset correction circuitry requires a 26MHz clock for proper operation. Therefore, CLKF should be programmed low if a 26MHz clock is provided to the
CLK_IN pin.
0=CLK_IN frequency is 26MHz
1=CLK_IN frequency is 52MHz
CRX1(4)
VCOSEL
0
When set to zero, the VCO is turned on and off by RX_EN. When programmed high,
the VCO is controlled by the VCOEN bit instead of RX_EN.
CRX1(3)
VCOEN
0
When VCOSEL is set to one, then VCOEN turns on and off the VCO. When VCOEN is
set to zero, the VCO is off. When VCOEN is set to one, the VCO is turned on.
CRX1(2)
TXSEL
1
If programmed high, the TX buffers are enabled by the TX_EN pin. If programmed
low, the TX buffers are enabled by CF[16].
CRX1(1:0)
TEST
00
Test Output Selection Bits: The GPO1 pin provides test signal outputs as well as
the activation signal for the RF6001 RX system. The available signals are
shown below.
00
Normal output of GPO1 pin
01
Serial data shifting through Configuration Registers
10
MSB bit of the VCO calibration counter
11
dcadapt counter 2 output
I/Q Phase Calibration
Receiver Configuration Register 2 (CRX2) - Address 100001
Programming Bits
# of Bits
Default
Description
CRX2(11)
DC_ST
0
If programmed high, the DC correction system is activated when the SDI word is
loaded. DC_ST will revert low once the DC correction system is activated. RX EN
needs to be high for DC_ST to operate correctly.
CRX2(10)
DC_EN
1
If programmed high, the DC correction system is activated on the rising edge of
RX_EN (default=1).
CRX2(9)
LND
0
If programmed high, the LNA’s are disabled during the time interval of the DC correction system.
CRX2(8)
TRD
0
If programmed high, GPO1 and GPO2 follow TRDC instead of the normal GP0 programming during the time interval defined by DC_TIME2.
CRX2(7)
TRTX_EN
0
If programmed high, the functionality defined by TRTXA is active.
CRX2(6)
reserved
0
Reserved
CRX2(5:4)
TRDC
00
If TRD is set true, then during the time interval defined by DC_TIME2, GPO1
and GPO2 are reassigned as follows.
GPO1=TRDC[0]
GPO2=TRDC[1]
CRX2(3:2)
TRTXA
00
If TRTX_EN is programmed high, while TXEN pin is high the GPO outputs are
reassigned as follows:
GPO1=TRTXA[0]
GPO2=TRTXA[1]
CRX2(1:0)
GPO
00
The states of each bit within this word are transferred to the corresponding GP0 pin
as follows.
GPO1=GPO[0]
GPO2=GPO[1]
Rev A4 DS050919
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21 of 26
RF2722
Proposed
Receiver Configuration Register 3 (CRX3) - Address 100010
Programming Bits
# of Bits
Defaults
Description
CRX3(11:10)
reserved
00
CRX3(9:2)
DC_TIME1
20H
CRX3(1:0)
reserved
00
Reserved
Sets the number of 26MHz/16 clock cycles from activation until the RF2722 DCOC
system is frozen.
Reserved
Receiver Configuration Register 4 (CRX4) - Address 100011
Programming Bits
# of Bits
Defaults
Description
CRX4(11:10)
reserved
00
CRX4(9:0)
DC_TIME2
124H
Reserved
Sets the number of 26MHz/16 clock cycles from activation until the LNA’s and/or
the RX T/R switch are reactivated.
Receiver Configuration Register 5 (CRX5) - Address 100100
Programming Bits
# of Bits
Defaults
Description
CRX5(11:9)
Gain_Cal
011
I/Q Gain Calibration
CRX5(8:6)
Reserved
000
Reserved
CRX5(5:4)
Reserved
00
Reserved
CRX5(3:2)
LNA_CURR
10
These bits control the LNA current as shown below.
Low Band
High Band
00
11mA
13.2mA
01
12.8mA
15mA
10
14.6mA
16.9mA
11
16.4mA
18.7mA
CRX5(1:0)
MIX_CURR
10
These bits control the Mixer current as shown below.
00
12.5mA
01
13.5mA
10
14.4mA
11
15.6mA
Polyphase Filter Gain Register (CF) - Address 100101
Programming Bits
# of Bits
Defaults
Description
CF(17)
22 of 26
TX_HL
0
If programmed low, enables Cellular/GSM TX buffer. If programmed high, enables
PCS/DCS TX buffer.
If TX_SEL is set false, TX buffers are controlled by this bit.
CF(16)
TX_EN
0
CF(15:13)
LNA_SEL
101
CF(12)
VCOHL
0
CF(11:8)
F_G1
0000
CF(7:6)
C_G1
11
Selects the active LNA.
000
LNA1 (US/GSM)
001
LNA2 (US/GSM)
010
LNA3 (DCS/PCS)
011
LNA4 (DCS/PCS)
100
All LNA’s off
101
All LNA’s off
If programmed low, divides the VCO by 2 and routes signal through
US Cellular/GSM filter path. If programmed high, the VCO signal is routed
through PCS/DCS filter path.
Selects the fine gain setting of the first pole of the filter. The gain in dB at the midband (0Hz for DCR) is as shown below.
0000=11.6dB0001=12.6dB0010=13.6dB0011=14.6dB
0100=15.6dB0101=16.6dB0110=17.6dB0111=18.7dB
1000=3.5dB1001=4.5dB1010=5.5dB1011=6.5dB
1100=7.5dB1101=8.5dB1110=9.5dB1111=10.5dB
Selects the coarse input attenuation setting of the first pole of the filter.
00=-13dB01=N/A10=-5.5dB11=0dB
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
Rev A4 DS050919
Proposed
RF2722
CF(5)
S_G2_0
1
Selects the gain setting at midband of the second filter stage.
0=-0.7dB1=+7.4dB
CF(4)
S_G2_1
1
Selects the gain setting at midband of the third filter stage.
0=-6.8dB1=+1dB
CF(3:2)
S_G3
00
Selects the gain setting at midband of the output buffer.
00=2.5dB01=8.4dB10=N/A11=14.3dB
CF(1)
VDS
0
Selects VLIF mode if programmed low. Selects DCR mode if programmed high.
CF(0)
LNA_BYP
0
If set to zero, the LNA is active. If set to one, the LNA is bypassed with a front end
gain reduction of: 11.9dB in low band; 10.4dB in high band.
Rev A4 DS050919
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support, contact RFMD at (+1) 336-678-5570 or [email protected].
23 of 26
RF2722
Proposed
PCB Design Requirements
PCB Surface Finish
The PCB surface finish used for RFMD's qualification process is electroless nickel, immersion gold. Typical thickness is 3μinch
to 8μinch gold over 180μinch nickel.
PCB Land Pattern Recommendation
PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested
for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances.
PCB Metal Land Pattern
A = 0.64 x 0.28 (mm) Typ.
B = 0.28 x 0.64 (mm) Typ.
C = 3.50 (mm) Sq.
3.50 Typ.
0.50 Typ.
Dimensions in mm.
Pin 32
Pin 1
0.50 Typ.
B
B
B
B
B
B
B
A
A
A
A
A
A
A
A
C
A
0.55 Typ.
B
A
A
A
A
A
A
A
B
B
B
B
B
B
B
Pin 24
1.75 Typ.
3.50 Typ.
B
Pin 16
0.55 Typ.
1.75 Typ.
Figure 1. PCB Metal Land Pattern (Top View)
24 of 26
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support, contact RFMD at (+1) 336-678-5570 or [email protected].
Rev A4 DS050919
RF2722
Proposed
PCB Solder Mask Pattern
Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the PCB
metal land pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all pads. The
center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be
provided in the master data or requested from the PCB fabrication supplier.
A = 0.74 x 0.38 (mm) Typ.
B = 0.38 x 0.74 (mm) Typ.
C = 3.60 (mm) Sq.
3.50 Typ.
0.50 Typ.
Dimensions in mm.
Pin 32
B B B B B B B B
Pin 1
0.50 Typ.
A
A
A
A
A
A
C
A
0.55 Typ.
Pin 24
A
A
A
A
A
A
A
A
A
1.75 Typ.
3.50 Typ.
B B B B B B B B
Pin 16
0.55 Typ.
1.75 Typ.
Figure 2. PCB Solder Mask (Top View)
Rev A4 DS050919
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support, contact RFMD at (+1) 336-678-5570 or [email protected].
25 of 26
RF2722
Proposed
Thermal Pad and Via Design
The PCB land pattern has been designed with a thermal pad that matches the exposed die paddle size on the bottom of the
device.
Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern shown has been
designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing
strategies.
The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a
0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the
quantity of vias be increased by a 4:1 ratio to achieve similar results.
Via
0.203 - 0.330 (mm)
Finished Hole
0.5 - 1.2 (mm) Grid
Figure 3. Thermal Pad and Via Design (RFMD Qualification)
26 of 26
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support, contact RFMD at (+1) 336-678-5570 or [email protected].
Rev A4 DS050919