19-1582; Rev 0; 12/99 8-Bit, 40MHz, Current/Voltage-Output DACs The MAX5187/MAX5190 are designed to provide a high level of signal integrity for the least amount of power dissipation. They operate from a single supply of +2.7V to +3.3V. Additionally, these DACs have three modes of operation: normal, low-power standby, and full shutdown, which provides the lowest possible power dissipation with a 1µA (max) shutdown current. A fast wake-up time (0.5µs) from standby mode to full DAC operation allows for power conservation by activating the DAC only when required. The MAX5187/MAX5190 are packaged in a 24-pin QSOP and are specified for the extended (-40°C to +85°C) temperature range. For higher resolution, 10-bit versions, see the MAX5181/MAX5184 data sheet. Features ♦ +2.7V to +3.3V Single-Supply Operation ♦ Wide Spurious-Free Dynamic Range: 70dB at fOUT = 2.2MHz ♦ Fully Differential Output ♦ Low-Current Standby or Full Shutdown Modes ♦ Internal +1.2V Low-Noise Bandgap Reference ♦ Small 24-Pin QSOP Package Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX5187BEEG MAX5190BEEG -40°C to +85°C -40°C to +85°C 24 QSOP 24 QSOP Pin Configuration Applications Signal Reconstruction TOP VIEW Digital Signal Processing Arbitrary Waveform Generation (AWG) CREF 1 24 REFO Imaging Applications OUTP 2 23 REFR OUTN 3 22 DGND AGND 4 21 DVDD AVDD 5 DACEN 6 20 D7 MAX5187 MAX5190 19 D6 PD 7 18 D5 CS 8 17 D4 CLK 9 16 D3 REN 10 15 D2 DGND 11 14 D1 DGND 12 13 D0 QSOP ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX5187/MAX5190 General Description The MAX5187 is an 8-bit, current-output digital-to-analog converter (DAC) designed for superior performance in signal reconstruction or arbitrary waveform generation applications requiring analog signal reconstruction with low distortion and low-power operation. The voltage-output MAX5190 provides equal specifications, with on-chip precision resistors for voltage output operation. Both devices are designed for a 10pVs glitch operation to minimize unwanted spurious signal components at the output. An on-board +1.2V bandgap circuit provides a well-regulated, low-noise reference that can be disabled for external reference operation. MAX5187/MAX5190 8-Bit, 40MHz, Current/Voltage-Output DACs ABSOLUTE MAXIMUM RATINGS AVDD, DVDD to AGND, DGND .................................-0.3V to +6V Digital Input to DGND...............................................-0.3V to +6V OUTP, OUTN, CREF to AGND .................................-0.3V to +6V VREF to AGND ..........................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V AVDD to DVDD .....................................................................±3.3V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70°C) 24-Pin QSOP (derate 9.50mW/°C above +70°C)........762mW Operating Temperature Ranges MAX5187BEEG/MAX5190BEEG ....................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = DVDD = +3V ±10%, AGND = DGND = 0, fCLK = 40MHz, IFS = 1mA, 400Ω differential output, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution 8 N Bits -1 ±0.25 +1 LSB Guaranteed monotonic -1 ±0.25 +1 LSB Zero-Scale Error MAX5182 MAX5191 -1 +1 -4 +4 Full-Scale Error (Note 1) -20 Integral Nonlinearity INL Differential Nonlinearity DNL ±4 +20 LSB LSB DYNAMIC PERFORMANCE Output Settling Time To ±0.5LSB error band Glitch Impulse Spurious-Free Dynamic Range to Nyquist SFDR fCLK = 40MHz Total Harmonic Distortion to Nyquist THD fCLK = 40MHz Signal-to-Noise Ratio to Nyquist SNR fCLK = 40MHz Clock and Data Feedthrough ns 10 pVs 72 fOUT = 550kHz fOUT = 2.2MHz 25 57 fOUT = 550kHz -70 fOUT = 2.2MHz -68 fOUT = 550kHz 52 fOUT = 2.2MHz 46 All 0s to all 1s Output Noise dBc 70 -63 dB dB 52 50 nVs 10 pA/√Hz ANALOG OUTPUT OUTPUT ANALOG Full-Scale Output Voltage 400 VFS -0.3 Voltage Compliance of Output DACEN = 0, MAX5187 only -1 Full-Scale Output Current IFS MAX5187 only 0.5 DAC External Output Resistor Load RL MAX5187 only Output Leakage Current 2 mV 0.8 1 400 _______________________________________________________________________________________ V 1 µA 1.5 mA Ω 8-Bit, 40MHz, Current/Voltage-Output DACs (AVDD = DVDD = +3V ±10%, AGND = DGND = 0, fCLK = 40MHz, IFS = 1mA, 400Ω differential output, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1.12 1.2 1.28 V REFERENCE Output Voltage Range VREF Output Voltage Temperature Drift TCVREF 50 ppm/°C Reference Output Drive Capability IREFOUT 10 µA Reference Supply Rejection Current Gain (IFS / IREF) 0.5 mV/V 8 mA/mA POWER REQUIREMENTS Analog Power-Supply Voltage 2.7 AVDD PD = 0, DACEN = 1, digital inputs at 0 or DVDD 1.7 3.3 V 4 mA 3.3 V Analog Supply Current IAVDD Digital Power-Supply Voltage DVDD Digital Supply Current IDVDD PD = 0, DACEN = 1, digital inputs at 0 or DVDD 4.2 5 mA ISTANDBY PD = 0, DACEN = 0, digital inputs at 0 or DVDD 1 1.5 mA ISHDN PD = 1, DACEN = X, digital inputs at 0 or DVDD (X = don’t care) 0.5 1 µA Standby Current Shutdown Current 2.7 LOGIC INPUTS AND OUTPUTS Digital Input Voltage High VIH Digital Input Voltage Low VIL Digital Input Current IIN Digital Input Capacitance CIN 2 V VIN = 0 or DVDD 10 0.8 V ±1 µA pF TIMING CHARACTERISTICS DAC DATA to CLK Rise Setup Time tDS 10 ns DAC CLK Rise to DATA Hold Time tDH 0 ns CS Fall to CLK Rise Time 5 ns CS Fall to CLK Fall Time 5 ns 0.5 µs 50 µs DACEN Rise Time to VOUT PD Fall Time to VOUT Clock Period tCLK 25 ns Clock High Time tCH 10 ns Clock Low Time tCL 10 ns Note 1: Excludes reference and reference resistor (MAX5190) tolerance. _______________________________________________________________________________________ 3 MAX5187/MAX5190 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (AVDD = DVDD = +3V, AGND = DGND = 0, 400Ω differential output, IFS = 1mA, CL = 5pF, TA = +25°C, unless otherwise noted.) DIFFERENTIAL NONLINEARITY vs. INPUT CODE 0.075 0.100 0.050 DNL (LSB) 0.050 0.025 0 0.025 -0.025 0 -0.050 MAX5190 1.5 MAX5187 96 0 128 160 192 224 256 32 64 128 160 192 224 256 2.5 2.0 MAX5190 MAX5187 10 35 60 7 MAX5190 6 MAX5187 5 4 3.25 3.0 3.5 4.0 4.5 5.0 5.5 -40 -15 10 35 60 STANDBY CURRENT vs. SUPPLY VOLTAGE STANDBY CURRENT vs. TEMPERATURE SHUTDOWN CURRENT vs. SUPPLY VOLTAGE 580 580 MAX5187 570 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 0.10 MAX5187 0.08 MAX5190 0.04 550 3.5 0.12 0.06 560 570 0.14 85 MAX5187/90-09 MAX5190 590 STANDBY CURRENT (µA) MAX5187 MAX5187/90-08 600 MAX5187/90-07 590 3.0 MAX5187 TEMPERATURE (°C) MAX5190 2.5 MAX5190 3.50 SUPPLY VOLTAGE (V) 600 5.5 3.75 TEMPERATURE (°C) 610 5.0 3.00 2.5 85 4.5 4.00 3 1.0 4.0 DIGITAL SUPPLY CURRENT vs. TEMPERATURE MAX5187/90-05 8 DIGITAL SUPPLY CURRENT (mA) 2.5 -15 3.5 SUPPLY VOLTAGE (V) DIGITAL SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX5187/90-04 3.0 -40 3.0 INPUT CODE ANALOG SUPPLY CURRENT vs. TEMPERATURE 1.5 96 MAX5187/90-06 64 DIGITAL SUPPLY CURRENT (mA) 32 INPUT CODE ANALOG SUPPLY CURRENT (mA) 2.0 1.0 -0.075 0 4 2.5 -0.050 -0.025 SHUTDOWN CURRENT (µA) INL (LSB) 0.075 3.0 MAX5187/90-03 0.125 MAX5187/90-02 0.100 MAX5187/90-01 0.150 ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE ANALOG SUPPLY CURRENT (mA) INTEGRAL NONLINEARITY vs. INPUT CODE STANDBY CURRENT (µA) MAX5187/MAX5190 8-Bit, 40MHz, Current/Voltage-Output DACs -40 -15 10 35 TEMPERATURE (°C) 60 85 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 5.0 5.5 8-Bit, 40MHz, Current/Voltage-Output DACs SHUTDOWN CURRENT vs. TEMPERATURE MAX5190 0.07 MAX5187 1.27 1.26 MAX5190 1.25 MAX5187 -15 10 35 60 85 1.26 MAX5187 1.25 MAX5190 1.23 1.23 2.5 3.0 3.5 4.0 4.5 5.0 -40 5.5 -15 10 35 60 TEMPERATURE (°C) SUPPLY VOLTAGE (V) TEMPERATURE (°C) OUTPUT CURRENT vs. REFERENCE CURRENT DYNAMIC RESPONSE RISE TIME DYNAMIC RESPONSE FALL TIME 85 MAX5187/90-15 MAX5187/90-13 4 MAX5187/90-14 -40 1.27 1.24 1.24 0.03 MAX5187/90-12 MAX5187/90-11 1.28 REFERENCE VOLTAGE (V) 0.09 REFERENCE VOLTAGE (V) 0.11 0.05 3 OUTP 150mV/ div OUTP 150mV/ div OUTN 150mV/ div OUTN 150mV/ div 2 1 0 100 200 300 400 50ns/div 500 50ns/div REFERENCE CURRENT (µA) SETTLING TIME fOUT = 2.2MHz fCLK = 40MHz -20 MAX5187/90-17 FFT PLOT 0 -10 -30 OUTN 100mV/ div (dBc) 0 MAX5187/90-16 OUTPUT CURRENT (mA) 1.28 MAX5187/90-10 SHUTDOWN CURRENT (µA) 0.13 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE MAX5187/MAX5190 Typical Operating Characteristics (continued) (AVDD = DVDD = +3V, AGND = DGND = 0, 400Ω differential output, IFS = 1mA, CL = 5pF, TA = +25°C, unless otherwise noted.) -40 -50 -60 -70 OUTP 100mV/ div 12.5ns/div -80 -90 -100 -110 -120 0 2 4 6 8 10 12 14 16 18 20 OUTPUT FREQUENCY (MHz) _______________________________________________________________________________________ 5 Typical Operating Characteristics (continued) (AVDD = DVDD = +3V, AGND = DGND = 0, 400Ω differential output, IFS = 1mA, CL = 5pF, TA = +25°C, unless otherwise noted.) SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY AND CLOCK FREQUENCY 76 62.4 MAX5187/90-20 90 fOUT = 50MHz fOUT = 20MHz fOUT = 40MHz SIGNAL-TO-NOISE PLUS DISTORTION vs. OUTPUT FREQUENCY MAX5187/90-19 78 MAX5187/90-18 100 62.2 62.0 80 70 72 fOUT = 10MHz 70 60 50 15 20 25 30 35 40 45 50 55 60 fOUT = 30MHz 61.0 60.8 500 700 900 1100 1300 1500 1700 1900 2100 2300 CLOCK FREQUENCY (MHz) 0 500 OUTPUT FREQUENCY (kHz) MULTITONE SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY 74 MAX5187/90-22 -20 1000 72 -30 70 SFDR (dBc) -40 -50 -60 -70 68 66 -80 64 -90 -100 -110 -120 62 60 0 2.5 5 7.5 10 12.5 15 17.5 OUTPUT FREQUENCY (MHz) 6 0.50 1500 2000 OUPUT FREQUENCY (kHz) SPURIOUS-FREE DYNAMIC RANGE vs. FULL-SCALE OUTPUT CURRENT MAX5187/90-21 0 -10 SFDR (dBc) 61.6 61.2 66 0 61.8 61.4 fOUT = 60MHz 68 40 SINAD (dB) 74 SFDR (dBc) SFDR (dBc) MAX5187/MAX5190 8-Bit, 40MHz, Current/Voltage-Output DACs 0.75 1.00 1.25 1.50 FULL-SCALE OUTPUT CURRENT (mA) _______________________________________________________________________________________ 2500 8-Bit, 40MHz, Current/Voltage-Output DACs PIN NAME FUNCTION 1 CREF Reference Bias Bypass 2 OUTP Positive Analog Output. Current output for MAX5187; voltage output for MAX5190. 3 OUTN Negative Analog Output. Current output for MAX5187; voltage output for MAX5190. 4 AGND Analog Ground 5 AVDD Analog Positive Supply, +2.7V to +3.3V DAC Enable, Digital Input 0: Enter DAC standby mode with PD = DGND 1: Power-up DAC with PD = DGND X: Enter shutdown mode with PD = DVDD (X = don’t care) 6 DACEN 7 PD Power-Down Select 0: Enter DAC standby mode (DACEN = DGND) or power-up DAC (DACEN = DVDD) 1: Enter shutdown mode 8 CS Active-Low Chip Select 9 CLK Clock Input 10 REN Active-Low Reference Enable. Connect to DGND to activate on-chip +1.2V reference. 11, 12, 22 DGND 13 D0 14–19 D1–D6 20 D7 21 DVDD Digital Supply, +2.7V to +3.3V 23 REFR Reference Input 24 REFO Reference Output Digital Ground Data Bit D0 (LSB) Data Bit D1–D6 Data Bit D7 (MSB) _______________________________________________________________________________________ 7 MAX5187/MAX5190 Pin Description MAX5187/MAX5190 8-Bit, 40MHz, Current/Voltage-Output DACs REN AVDD AGND CS DACEN PD 1.2V REF REFO CREF CURRENTSOURCE ARRAY REFR OUTP 9.6k* DAC SWITCHES OUTN OUTPUT LATCHES OUTPUT LATCHES MSB DECODE CLK 400Ω * MSB DECODE INPUT LATCHES INPUT LATCHES MAX5187 MAX5190 DVDD *INTERNAL 400Ω AND 9.6kΩ RESISTORS FOR MAX5190 ONLY. 400Ω* DGND D7–D0 Figure 1. Functional Diagram Detailed Description The MAX5187/MAX5190 are 8-bit DACs capable of operating with clock speeds up to 40MHz. Each converter consists of separate input and DAC registers, followed by a current-source array capable of generating up to 1.5mA full-scale output current (Figure 1). An integrated +1.2V voltage reference and control amplifier determine the data converters’ full-scale output currents/voltages. Careful reference design ensures close gain matching and excellent drift characteristics. The MAX5190’s voltage-output operation features matched 400Ω on-chip resistors that convert the current array current into a voltage. Internal Reference and Control Amplifier The MAX5187/MAX5190 provide an integrated 50ppm/°C, +1.2V, low-noise bandgap reference that can be disabled and overridden by an external reference voltage. REFO serves either as an external reference input or an integrated reference output. If REN is connected to DGND, the internal reference is selected and REFO provides a +1.2V output. Due to its limited 8 10µA output drive capability, REFO must be buffered with an external amplifier if heavier loading is required. The MAX5187/MAX5190 also employ a control amplifier, designed to simultaneously regulate the full-scale output current (IFS) for both outputs of the devices. The output current is calculated as follows: IFS = 8 · IREF where I REF is the reference output current (I REF = VREFO / RSET) and IFS is the full-scale output current. R SET is the reference resistor that determines the amplifier’s output current on the MAX5187 (Figure 2). This current is mirrored into the current-source array, where it is equally distributed between matched current segments and summed to valid output current readings for the DACs. The MAX5190 converts this output current into a differential output voltage (VOUT) with two internal, groundreferenced 400Ω load resistors. Using the internal +1.2V reference voltage, the MAX5190’s integrated reference output current resistor (RSET = 9.6kΩ) sets IREF to 125µA and IFS to 1mA. _______________________________________________________________________________________ 8-Bit, 40MHz, Current/Voltage-Output DACs MAX5187/MAX5190 OPTIONAL EXTERNAL BUFFER FOR HEAVIER LOADS DGND REN +1.2V BANDGAP REFERENCE MAX4040 REFO CCOMP* AGND REFR VREF IREF = CURRENTSOURCE ARRAY IREF RSET RSET IFS RSET** 9.6k MAX5187 MAX5190 AGND *COMPENSATION CAPACITOR (CCOMP = 100nF) **9.6kΩ REFERENCE CURRENT SET RESISTOR INTERNAL TO MAX5190 ONLY. USE EXTERNAL RSET FOR MAX5188. Figure 2. Setting IFS with the Internal +1.2V Reference and the Control Amplifier DVDD 10µF 0.1µF DGND REN +1.21V BANDGAP REFERENCE AVDD EXTERNAL +1.21V REFERENCE REFO CURRENTSOURCE ARRAY REFR MAX6520 IFS IREF AGND RSET AGND 9.6k* MAX5187 MAX5190 *9.6kΩ REFERENCE CURRENT SET RESISTOR INTERNAL TO MAX5190 ONLY. USE EXTERNAL RSET FOR MAX5188. Figure 3. MAX5187/MAX5190 with External Reference _______________________________________________________________________________________ 9 MAX5187/MAX5190 8-Bit, 40MHz, Current/Voltage-Output DACs External Reference Shutdown Mode To disable the MAX5187/MAX5190’s internal reference, connect REN to DVDD. A temperature-stable external reference may now be applied to drive the REFO pin to set the full-scale output (Figure 3). Choose a reference that can supply at least 150µA to drive the bias circuit that generates the cascode current for the current array. For improved accuracy and drift performance, choose a voltage reference with a fixed output voltage, such as the +1.2V, 25ppm/°C MAX6520 bandgap reference. For lowest power consumption, the MAX5187/MAX5190 provide a power-down mode in which the reference, control amplifier, and current array are inactive and the DAC’s supply current is reduced to 1µA. To enter this mode, connect PD to DVDD. To return to active mode, connect PD to DGND and DACEN to DVDD. About 50µs are required for the parts to leave shutdown mode and settle to their outputs’ values prior to shutdown. Standby Mode Figure 4 shows a detailed timing diagram for the MAX5187/MAX5190. With each high transition of the clock, the input latch is loaded with the digital value set by bits D7 through D0. The content of the input latch is then shifted to the DAC register, and the output updates at the rising edge of the next clock. Timing Information To enter the lower power standby mode, connect the digital inputs PD and DACEN to DGND. In standby, both the reference and the control amplifier are active with the current array inactive. To exit this condition, DACEN must be pulled high with PD held at DGND. Both the MAX5187 and MAX5190 typically require 50µs to wake up and allow both the outputs and the reference to settle. tCLK tCL tCH CLK D0–D7 N-1 N N+1 tDH tDS OUT N-1 N N+1 Figure 4. Timing Diagram Table 1. Power-Down Mode Selection PD (POWER-DOWN SELECT) DACEN (DAC ENABLE) POWER-DOWN MODE 0 0 Standby 0 1 Wake-Up 1 X Shutdown OUTPUT STATE MAX5187 High-Z MAX5190 AGND Last state prior to standby mode MAX5187 High-Z MAX5190 AGND X = Don’t care 10 ______________________________________________________________________________________ 8-Bit, 40MHz, Current/Voltage-Output DACs Applications Information Static and Dynamic Performance Definitions Integral Nonlinearity Integral nonlinearity (INL) (Figure 5a) is the deviation of the values on an actual transfer function from either a best-straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the endpoints of the transfer function once offset and gain errors have been nullified. For a DAC, the deviations are measured every single step. Differential Nonlinearity Differential nonlinearity (DNL) (Figure 5b) is the difference between an actual step height and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. Offset Error Offset error (Figure 5c) is the difference between the ideal and the actual offset point. For a DAC, the offset point is the step value when the digital input is zero. This error affects all codes by the same amount and can usually be compensated by trimming. 7 6 5 4 AT STEP 011 (1/2 LSB ) 3 2 DIFFERENTIAL LINEARITY ERROR (-1/4 LSB) 4 3 1 LSB 2 AT STEP 001 (1/4 LSB ) 1 1 LSB 5 ANALOG OUTPUT VALUE ANALOG OUTPUT VALUE 6 DIFFERENTIAL LINEARITY ERROR (+1/4 LSB) 1 0 0 000 001 010 011 100 101 110 000 111 001 IDEAL DIAGRAM IDEAL OFFSET POINT 0 000 001 OFFSET ERROR (+1 1/4 LSB) ANALOG OUTPUT VALUE ANALOG OUTPUT VALUE 2 1 101 GAIN ERROR (-1 1/4 LSB) 6 IDEAL DIAGRAM ACTUAL FULL-SCALE OUTPUT 5 4 0 010 011 000 100 101 110 111 DIGITAL INPUT CODE DIGITAL INPUT CODE Figure 5c. Offset Error 100 IDEAL FULL-SCALE OUTPUT 7 ACTUAL DIAGRAM ACTUAL OFFSET POINT 011 Figure 5b. Differential Nonlinearity Figure 5a. Integral Nonlinearity 3 010 DIGITAL INPUT CODE DIGITAL INPUT CODE Figure 5d. Gain Error ______________________________________________________________________________________ 11 MAX5187/MAX5190 Outputs The MAX5187 output is designed to supply full-scale output currents of 1mA into 400Ω loads in parallel with a capacitive load of 5pF. The MAX5190 features integrated 400Ω resistors that restore the array current to proportional, differential voltages of 400mV. These differential output voltages can then be used to drive a balun transformer or a low-distortion, high-speed operational amplifier to convert the differential voltage into a single-ended voltage. MAX5187/MAX5190 8-Bit, 40MHz, Current/Voltage-Output DACs +3V AVDD +3V 10µF 0.1µF 0.1µF 10µF 0.1µF 402Ω AVDD DVDD CREF 402Ω +5V OUTP CLK OUTPUT 400Ω* D0–D7 MAX5187 MAX5190 REFO 402Ω MAX4108 -5V OUTN 402Ω 0.1µF 400Ω* REFR RSET** DGND REN AGND *400Ω RESISTORS INTERNAL TO MAX5190 ONLY. **MAX5187 ONLY Figure 6. Differential to Single-Ended Conversion Using a Low-Distortion Amplifier Gain Error Gain error (Figure 5d) is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. Settling Time Settling time is the amount of time required from the start of a transition until the DAC output settles its new output value to within the converter’s specified accuracy. Digital Feedthrough Digital feedthrough is the noise generated on a DAC’s output when any digital input transitions. Proper board layout and grounding will significantly reduce this noise, but there will always be some feedthrough caused by the DAC itself. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the input signal’s first five harmonics to the fundamental itself. This is expressed as: THD = 20 12 ⋅ 2 2 2 2 V2 + V3 + V4 + V5 log V1 where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component. Differential to Single-Ended Conversion The MAX4108 low-distortion, high-input bandwidth amplifier may be used to generate a voltage from the array current output of the MAX5187. The differential voltage across OUTP and OUTN is converted into a single-ended voltage by designing an appropriate operational amplifier configuration (Figure 6). I/Q Reconstruction in a QAM Application The low-distortion performance of two MAX5187/ MAX5190s supports analog reconstruction of in-phase (I) and quadrature (Q) carrier components typically used in quadrature amplitude modulation (QAM) architectures, where two separate buses carry the I and Q data. A QAM signal is both amplitude and phase modulated, created by summing two independently modulated carriers of identical frequency but different phase (90° phase difference). ______________________________________________________________________________________ 8-Bit, 40MHz, Current/Voltage-Output DACs MAX5187/MAX5190 AVDD +3V DVDD +3V I COMPONENT 8 DIGITAL SIGNAL PROCESSOR BP FILTER MAX5187 MAX5190 AVDD CARRIER FREQUENCY DVDD Q COMPONENT 8 MAX5187 MAX5190 0° 90° Σ IF BP FILTER MAX2452 QUADRATURE MODULATOR Figure 7. Using the MAX5187/MAX5190 for I/Q Signal Reconstruction In a typical QAM application (Figure 7), the modulation occurs in the digital domain, and two DACs such as the MAX5187/MAX5190 may be used to reconstruct the analog I and Q components. The I/Q reconstruction system is completed by a quadrature modulator that combines the reconstructed components with in-phase and quadrature carrier frequencies and then sums both outputs to provide the QAM signal. Using the MAX5187/MAX5190 for Arbitrary Waveform Generation Designing a traditional AWG requires five major functional blocks (Figure 8a): clock generator, counter, waveform memory, digital-to-analog converter for waveform reconstruction, and output filter. The waveform memory contains a sequentially stored digital replica of the desired analog waveforms. This memory shares a common clock with the DAC. For each clock cycle, a counter adds one count to the address for the waveform memory. The memory then loads the next value to the DAC, which generates an analog output voltage corresponding to that data value until the next clock cycle. A DAC output filter can either be a simple or complex lowpass filter, depending on the AWG requirements for waveform function and frequencies. The main limitations of the AWG’s flexibility are DAC resolution and dynamic performance, memory length, clock/playback frequency, and filter characteristics. Although the MAX5187/MAX5190 offer high-frequency operation and excellent dynamics, they are suitable for relaxed requirements in resolution (8-bit AWGs). To increase an AWG’s high-frequency accuracy, temperature stability, wideband tuning, and past phase continuous-frequency switching, the user may approach a direct digital synthesis (DDS) AWG (Figure 8b). This DDS loop supports standard waveforms that are repetitive, such as sine, square, TTL, and triangular waveforms. DDS allows for precise control of the data stream input to the DAC. Data for one complete output waveform cycle is sequentially stored in RAM. As the RAM addresses change, the DAC converts the incoming data bits into a corresponding voltage waveform. The resulting output signal frequency is proportional to the frequency rate at which the RAM addresses are changed. Grounding and Power-Supply Decoupling Grounding and power-supply decoupling strongly influence the MAX5187/MAX5190’s performance. Unwanted digital crosstalk may couple through the input, reference, power-supply, and ground connections, which may affect dynamic specifications like signal-to-noise ratio or spurious-free dynamic range. In addition, electromagnet- ______________________________________________________________________________________ 13 MAX5187/MAX5190 8-Bit, 40MHz, Current/Voltage-Output DACs AVDD COUNTER WAVEFORM MEMORY (RAM) ADR CLOCK GENERATOR DVDD LOWPASS RECONSTRUCTION FILTER 8 MAX5187 MAX5190 400Ω* VARIABLE fC 9.6k* FILTERED WAVEFORM (ANALOG OUTPUT) *MAX5187 ONLY Figure 8a. Traditional Arbitrary Waveform Generation (AWG) CLOCK GENERATOR AVDD PIR PHASE INCREMENT REGISTER A D D E R DVDD LOWPASS RECONSTRUCTION FILTER DATA PHASE ACCUMULATOR ADR WAVEFORM MEMORY (RAM) 8 MAX5187 MAX5190 REFR ACCUMULATOR FEEDBACK LOOP FOR DATA BITS 9.6k* 400Ω* VARIABLE fC FILTERED WAVEFORM (ANALOG OUTPUT) *MAX5187 ONLY Figure 8b. Direct Digital Synthesis AWG (DDS AWG) ic interference (EMI) can either couple into or be generated by the MAX5187/MAX5190. Therefore, grounding and power-supply decoupling guidelines for highspeed, high-frequency applications should be closely followed. First, a multilayer PC board with separate ground and power-supply planes is recommended. High-speed signals should be run on controlled impedance lines directly above the ground plane. Since the MAX5187/ MAX5190 have separate analog and digital ground buses (AGND and DGND, respectively), the PC board should also have separate analog and digital ground sections with only one point connecting the two. Digital signals should run above the digital ground plane, and analog signals should run above the analog ground plane. Both devices have two power-supply inputs: analog VDD (AVDD) and digital VDD (DVDD). Each AVDD input should be decoupled with parallel 10µF and 0.1µF 14 ceramic chip capacitors. These capacitors should be as close to the pin as possible, and their opposite ends should be as close as possible to the ground plane. The DVDD pins should also have separate 10µF and 0.1µF capacitors adjacent to their respective pins. Try to minimize the analog load capacitance for proper operation. For best performance, bypass with low-ESR 0.1µF capacitors to AVDD. The power-supply voltages should also be decoupled with large tantalum or electrolytic capacitors at the point they enter the PC board. Ferrite beads with additional decoupling capacitors forming a pi-network can also improve performance. Chip Information TRANSISTOR COUNT: 9464 SUBSTRATE CONNECTED TO AGND ______________________________________________________________________________________ 8-Bit, 40MHz, Current/Voltage-Output DACs QSOP.EPS ______________________________________________________________________________________ 15 MAX5187/MAX5190 Package Information MAX5187/MAX5190 8-Bit, 40MHz, Current/Voltage-Output DACs NOTES Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.