MAXIM MAX3507

19-2092; Rev 0; 7/01
Upstream CATV Amplifier with
On-Chip Anti-Alias Filter
Features
♦ Built-In 5th-Order Elliptic Anti-Aliasing Filter
♦ 5MHz to 65MHz Operation
♦ 55dB Gain Control Range
♦ Optional Positive Slope Generator
♦ 55dB Spurious-Free Dynamic Range Over
Transmit Band
The device operates from a single +5V supply and
draws 220mA nominal during transmit at max gain
(100% duty cycle). For burst-type transmissions, the
device is shut off between bursts to minimize noise and
save power while still maintaining a match at the output.
The device is optimized for high linearity with harmonic
levels below -55dBc.
The MAX3507 is available in a 28-pin QFN package
and operates over the extended industrial temperature
range (-40°C to +85°C).
Ordering Information
PART
TEMP. RANGE
PIN-PACKAGE
MAX3507EGI
-40°C to +85°C
28 QFN
Applications
Cable Modem Upstream Transmitter
Pin Configuration appears at end of data sheet.
Set-Top Box Upstream Transmitter
Telephony Over Cable
Typical Operating Circuit
28
BIASF
DC+
DC-
27
26
25
24
23
VCC
GND
N.C.
VCC
22
1
21
3
TXEN
VCC
BIAS
CIRCUIT
2
20
19
5-POLE
ELLIPTIC
FILTER
OPTIONAL
EQUALIZER
GND
VCC
GND
EQ-
EQ+
VCC
4
18
5
17
N.C.
OUT+
OUT-
VCC
16
MAX3507
11
12
13
15
4:1
IMPEDANCE
RATIO
CEXT
N.C.
14
SHDN
10
SCLK
9
GND
8
N.C.
7
SDA
IN-
6
CS
IN+
N.C.
GAIN
CONTROL
SERIAL DATA
GND
VCC
VCC
DIGITAL
CONTROL
LINES
SPI is a trademark of Motorola, Inc.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX3507
General Description
The MAX3507 is a variable-gain power amplifier for use
in CATV upstream transmitters. The variable-gain feature has 55dB of dynamic range and is controlled by a
3-wire SPI™ bus. The device is capable of generating
+64dBmV output (16QAM/QPSK) when driven with a
+34dBmV nominal input signal. The on-chip anti-alias
lowpass filter with 75MHz cutoff frequency saves system design cost and space. The optional positive slope
generator provides system design flexibility.
MAX3507
Upstream CATV Amplifier with
On-Chip Anti-Alias Filter
ABSOLUTE MAXIMUM RATINGS
VCC, OUT+, OUT- to GND.....................................-0.5V to +8.0V
Input Voltage Levels (all inputs),
CEXT to GND ...........................................-0.3V to (VCC + 0.3V)
Continuous Input Voltage (IN+, IN-) ..................................2Vp-p
Continuous Current (OUT+, OUT-) ..................................120mA
Continuous Power Dissipation (TA = +70°C)
28-Pin QFN (derate 20.8mW/°C above +70°C) ..............1.67W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +125°C
Bump Reflow Temperature ..............................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(MAX3507 EV Kit, VCC = +4.75V to +5.25V, VGND = 0, VTXEN = V SHDN = VCC, D7 = 1, TA = -40°C to +85°C, unless otherwise specified. No input signal applied. A 4:1 (300Ω to 75Ω) impedance ratio balun is connected to differential output ports and balun output is
terminated into a 75Ω load. Typical parameters are at VCC = +5.0V, TA = +25°C.) (Note 1)
PARAMETER
CONDITIONS
Supply Voltage
MIN
TYP
4.75
D7 = 1, gain code = 127 (max gain)
218
D7 = 1, gain code = 119 (gain of 28dB)
164
D7 = 1, gain code = 64 (gain of 0dB)
82
D7 = 0, gain code = 94 (gain of 0dB)
74
Supply Current Transmit Disable
Mode
VTXEN = VEE, V SHDN = VCC
45
Shutdown Supply Current
VTXEN = X, V SHDN = VEE
1
Supply Current Transmit Mode
MAX
UNITS
5.25
V
280
mA
59
mA
µA
LOGIC INPUTS
Input HIGH Voltage Threshold
2.0
Input LOW Voltage Threshold
Input HIGH Current
Input LOW Current
2
-100
_______________________________________________________________________________________
V
0.8
V
100
µA
µA
Upstream CATV Amplifier with
On-Chip Anti-Alias Filter
(MAX3507 EV Kit, VCC = +4.75V to +5.25V, VGND = 0, VTXEN = V SHDN = VCC, VIN = +34dBmV differential, TA = -40°C to +85°C,
unless otherwise specified. A 4:1 impedance ratio (300Ω to 75Ω) balun is connected to differential output ports and balun output is
terminated into a 75Ω load. Typical parameters are at VCC = +5.0V, TA = +25°C.) (Note 1)
PARAMETER
CONDITIONS
fIN = 5MHz,
TA = 0°C to +85°C
(Note 2)
Voltage Gain (AV)
MIN
TYP
MAX
D7 = 1, gain code = 125
29.6
31.1
32.6
D7 = 1, gain code = 119
26.8
28.3
29.8
D7 = 1, gain code = 104
19.5
20.9
22.3
D7 = 1, gain code = 84
9.7
10.9
12.1
D7 = 1, gain code = 64
-0.7
0.5
1.7
D7 = 0, gain code = 74
-10.5
-9.3
-8.1
D7 = 0, gain code = 54
-20.4
-19.1
-17.8
D7 = 0, gain code = 42
-27.2
-25.7
-24.2
-1.1
-0.5
+0.2
-2.1
-0.7
+0.3
fIN = 65MHz,
D7 = 1, gain code = 127
TA = 0°C to +85°C
(Note 3)
VOUT = 61dBmV, fIN = 42MHz, equalizer disabled (Note 3)
Gain Flatness
VOUT = 61dBmV, fIN = 65MHz, equalizer disabled (Note 3)
0.7
1.0
1.3
fIN = 5MHz to 42MHz, D7 = 0, gain code = 109; D7 = 1,
gain code = 81, TA = 0°C to +85°C
0.6
1.0
1.4
Any BW = 160kHz from 5MHz to 65MHz, TXEN = VEE
(Note 3)
Isolation in Transmit Disable
Mode
TXEN = VEE, fIN = 5MHz to 65MHz
Transmit Mode Noise
Any BW = 160kHz from 5MHz to 65MHz, gain = -26dB to
+30dB (Note 3)
Transmit Enable Transient
Duration
dB
0.5
fIN = 5MHz to 65MHz, AV = -26dB to +30dB, any 2-bit
transition of D0, D1
Transmit-Disable Mode Noise
dB
29.0
fIN = 5MHz to 65MHz, AV = -26dB to +30dB
Gain Step Size
UNITS
-64
70
dB
dBmV
dB
-54.5
dBc
TXEN input rise/fall time < 0.1µs,
TA = +25°C (Notes 3, 4)
2
µs
Transmit Disable Transient
Duration
TXEN input rise/fall time < 0.1µs,
TA = +25°C (Notes 3, 4)
2
µs
Transmit Disable/Transmit
Enable Transient Step Size
D7 = 0, gain code = 94 (AV = 0), TA = +25°C (Note 3)
Input Impedance
fIN = 5MHz to 65MHz, single ended (Note 3)
Output Return Loss
fIN = 5MHz to 42MHz in 75Ω system, D7 = 1,
gain code = 125 (AV = 30dB) (Note 5)
10
dB
Output Return Loss in Transmit
Disable Mode
fIN = 5MHz to 42MHz in 75Ω system, TXEN = VEE (Note 5)
10
dB
D7 = 1, gain code = 119 (AV = >27dB), TA = +25°C
100
1.5
0.8
5.2
mVp-p
kΩ
_______________________________________________________________________________________
3
MAX3507
AC ELECTRICAL CHARACTERISTICS
MAX3507
Upstream CATV Amplifier with
On-Chip Anti-Alias Filter
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX3507 EV Kit, VCC = +4.75V to +5.25V, VGND = 0, VTXEN = V SHDN = VCC, VIN = +34dBmV differential, TA = -40°C to +85°C,
unless otherwise specified. A 4:1 impedance ratio (300Ω to 75Ω) balun is connected to differential output ports and balun output is
terminated into a 75Ω load. Typical parameters are at VCC = +5.0V, TA = +25°C.) (Note 1)
PARAMETER
Two-Tone Third-Order Distortion
CONDITIONS
MIN
TYP
Input tones at 42MHz and 42.2MHz, both at +31dBmV,
VOUT = +58dBmV/tone
-55.4
Input tones at 65MHz and 65.2MHz, both at +31dBmV,
VOUT = +58dBmV/tone
-47.6
MAX
UNITS
dBc
fIN = 33MHz, VOUT = +63dBmV
-58
fIN = 33MHz, VOUT = +60dBmV, TA = 0°C to +85°C
-56
fIN = 65MHz, VOUT = +60dBmV
-61
fIN = 22MHz, VOUT = +63dBmV
-53
fIN = 22MHz, VOUT = +60dBmV
-58
fIN = 65MHz, VOUT = +60dBmV
-57
1dB Compression Point
Gain = 26dB, fIN = 65MHz
22
AM to AM
Gain = 28dB, VIN = +34dBmV to +38dBmV, fIN = 65MHz
-0.1
dB
AM to PM
Gain = 28dB, VIN = +34dBmV to +38dBmV, fIN = 65MHz
-1.3
degrees
Rejection at 135MHz
Referenced to 65MHz
47
dBc
2ND Harmonic Distortion
3RD Harmonic Distortion
36
-50
dBc
-51
dBc
dBm
TIMING CHARACTERISTICS
(MAX3507 EV Kit, VCC = +4.75V to +5.25V, VGND = 0, VTXEN = V SHDN = VCC, TA = +25°C, unless otherwise specified.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SEN to SCLK Rise Set Time
tSENS
20
ns
SEN to SCLK Rise Hold Time
tSENH
10
ns
SDA to SCLK Setup Time
tSDAS
10
ns
SDA to SCLK Hold Time
tSDAH
20
ns
SDA Pulse-Width High
tDATAH
50
ns
SDA Pulse-Width Low
tDATAL
50
ns
SCLK Pulse-Width High
tSCLKH
50
ns
SCLK Pulse-Width Low
tSCLKL
50
ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
4
Guaranteed by design and characterization to ±3 sigma for TA < +25°C, unless otherwise specified.
AC gain correlated to DC gain measurements to ±3 sigma.
Guaranteed by design and characterization to ±6 sigma.
All transients comply with DOCSIS 1.1 limits for transmit power ripple of ±0.1dB.
Does not include output matching; see Output Match in the Applications section.
_______________________________________________________________________________________
Upstream CATV Amplifier with
On-Chip Anti-Alias Filter
HP MODE, GC = 127
150
LN MODE, GC = 80
50
TA = +85°C
170
150
TA = +25°C
110
-15
10
35
60
85
100
90
TA = +25°C
80
70
60
TA = -40°C
50
40
50
-40
30
40
50
60
70
0
10
20
30
40
50
60
TEMPERATURE (°C)
POUT (dBmV)
POUT (dBmV)
VOLTAGE GAIN IN HIGH-POWER MODE
vs. TEMPERATURE
VOLTAGE GAIN IN LOW-NOISE MODE
vs. TEMPERATURE
VOLTAGE GAIN IN HIGH-POWER MODE
vs. FREQUENCY
31.7
VCC = +4.7V
31.5
VOLTAGE GAIN (dB)
VOLTAGE GAIN (dB)
VCC = +5.3V
31.6
GC = 127
GC = 119
GC = 99
GC = 79
26
-5.8
31.9
31.8
-5.6
-6.0
-6.2
-6.4
VCC = 4.7V,
5.0V, 5.3V
MAX3507 toc06
VCC = +5.0V
46
MAX3507 toc05
32.1
32.0
-5.4
MAX3507 toc04
32.2
6
GC = 59
-14
-34
-6.6
31.4
-54
-6.8
31.3
GC = 127
31.2
-40
-15
10
35
-7.0
-40
85
10
35
60
-74
85
1
10
100
1000
INPUT FREQUENCY (MHz)
VOLTAGE GAIN IN LOW-NOISE MODE
vs. FREQUENCY
VOLTAGE GAIN vs. GAIN CODE
GAIN STEP IN HIGH-POWER MODE
vs. GAIN CODE
26
0.9
0.8
GC = 50
-34
-54
16
GAIN STEP (dB)
VOLTAGE GAIN (dB)
HIGH-POWER MODE
GC = 70
6
-4
-14
MAX3507 toc09
1.0
MAX3507 toc08
MAX3507 toc07
36
GC = 90
-14
-15
TEMPERATURE (°C)
GC = 110
6
60
GC = 80
TEMPERATURE (°C)
26
VOLTAGE GAIN (dB)
TA = +85°C
TA = -40°C
70
0
NO AC SIGNALS APPLIED
110
90
TXEN = GND
VOLTAGE GAIN (dB)
190
130
120
SUPPLY CURRENT (mA)
210
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
200
NO AC SIGNALS
APPLIED
230
SUPPLY CURRENT IN LOW-NOISE MODE
vs. OUTPUT POWER
MAX3507 toc02
NO AC SIGNALS
APPLIED
100
250
MAX3507 toc01
250
SUPPLY CURRENT IN HIGH-POWER MODE
vs. OUTPUT POWER
MAX3507 toc03
SUPPLY CURRENT
vs. TEMPERATURE
0.7
0.6
0.5
0.4
0.3
LOW-NOISE MODE
0.2
-74
-24
-94
-34
1
10
100
INPUT FREQUENCY (MHz)
1000
0.1
0
20
40
60
80
GAIN CODE
100
120
140
60
70
80
90
100
110
120
130
GAIN CODE
_______________________________________________________________________________________
5
MAX3507
Typical Operating Characteristics
(MAX3507 EV Kit, VCC = +5.0V, VIN = +34dBmV, TXEN = SHDN = VCC, fIN = 20MHz, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(MAX3507 EV Kit, VCC = +5.0V, VIN = +34dBmV, TXEN = SHDN = VCC, fIN = 20MHz, TA = +25°C, unless otherwise noted.)
0.7
0.6
0.5
0.4
0.3
0.2
50
-10
45
40
HIGH POWER MODE
-20
STEP SIZE (mV)
0.8
0
MAX3507 toc11
0.9
NOISE (dBm/Hz at BW = 160kHz)
MAX3507 toc10
1.0
-30
-40
35
30
25
ENABLE
20
15
LOW NOISE MODE
10
-50
0.1
5
0
30
40
50
60
70
80
90 100 110 120
DISABLE
0
-60
30
50
70
90
110
130
60
70
80
90
100
110
120
130
GAIN CODE
GAIN CODE
GAIN CODE
TRANSMIT ENABLE/DISABLE TRANSIENT
IN LOW-NOISE MODE vs. GAIN CODE
2ND-ORDER HARMONIC DISTORTION
IN HIGH-POWER MODE vs. FREQUENCY
3RD-ORDER HARMONIC DISTORTION
IN HIGH-POWER MODE vs. FREQUENCY
3
ENABLE
2
1
VOUT = 64dBmV
-45
VOUT = 60dBmV
-45
HARMONIC DISTORTION (dBc)
4
-40
MAX3507 toc14
5
-40
HARMONIC DISTORTION (dBc)
MAX3507 toc13
6
MAX3507 toc15
GAIN STEP (dB)
TRANSMIT ENABLE/DISABLE TRANSIENT
IN HIGH-POWER MODE vs. GAIN CODE
TRANSMIT NOISE vs. GAIN CODE
MAX3507 toc12
GAIN STEP IN LOW-NOISE MODE
vs. GAIN CODE
TRANSIENT (mVp-p)
-50
-55
-60
-65
-70
-50
-55
-60
-65
-70
-75
-75
DISABLE
0
-80
-80
30
50
70
90
110
5
130
GAIN CODE
15
25
35
45
55
5
65
15
25
PASSBAND FLATNESS vs. RC
21.6dB
VCC = +5.0V
D7 = 1
GC = 119
R = 301Ω
C = 22pF
0.2dB/
div
R = 680Ω
C = 10pF
NO EQUALIZATION
19.6dB
1MHz
6
6.9MHz/div
35
45
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
MAX3507 toc16
MAX3507
Upstream CATV Amplifier with
On-Chip Anti-Alias Filter
70MHz
_______________________________________________________________________________________
55
65
Upstream CATV Amplifier with
On-Chip Anti-Alias Filter
PIN
NAME
DESCRIPTION
1
BIASF
2
DC+
Filter Offset Correction. Connect 0.1µF capacitor between this pin and DC-.
3
DC-
Filter Offset Correction. Connect 0.1µF capacitor between this pin and DC+.
4, 8, 12, 23, 26
GND
Ground
5, 22, 25
VCC
+5V Supply. Bypass this pin to GND with a 0.1µF capacitor as close to the part as possible.
6
IN+
Positive Input. Along with IN-, this port forms a high-impedance differential input to the filter.
7
IN-
Negative Input. When not used, this port must be AC-coupled to ground. See IN+.
9
CS
Serial Interface Enable (Chip Select). TTL-compatible input. See Serial Interface section.
10
SDA
Serial Interface Data (Serial Data). TTL-compatible input. See Serial Interface section.
11
SCLK
Serial Interface Clock (Serial Clock). TTL-compatible input. See Serial Interface section.
Filter Bias. Connect to GND.
13, 15, 17, 20, 24
N.C.
14
SHDN
Shutdown. When SHDN is set low, all functions (including the serial interface) are disabled.
No Connection. Not internally connected.
16
CEXT
RF Output Bypass. Bypass to ground with a 0.1µF capacitor.
18
OUT-
Negative Output. Along with OUT+, this port forms a 300Ω impedance output. This port is matched
to a 75Ω load using a 2:1 (voltage ratio) transformer.
19
OUT+
Positive Output. See OUT-.
21
TXEN
Signal Path Enable. Setting this pin low turns off the PGA and power amplifier, leaving the filter
and serial interface enabled to save the last gain setting.
27
EQ+
Positive Equalizer. Connect an RC network if equalization of the filter passband is desired; leave
open otherwise. See Typical Operating Characteristics.
28
EQ-
Negative Equalizer. Connect an RC network if equalization of the filter passband is desired; leave
open otherwise. See Typical Operating Characteristics.
Detailed Description
Internal Filter
The internal filter consists of an input transconductance
amplifier, a balanced fifth-order elliptic active lowpass
filter, and an offset-correction feedback network. The
signal at the output of the filter is level-shifted into the
programmable-gain amplifier.
The transconductance amplifier provides a high input
impedance to the user, and current drives the filter to
minimize insertion loss. The filter is a Gm-C topology to
provide sufficient bandwidth and linearity. The cutoff
frequency of the filter is fixed at 75MHz, while the specified stopband attenuation is met at 120MHz.
The internal offset-correction feedback network
removes any DC offset at the output of the filter. An offset voltage at this node would generate a transient during a TX-enable or -disable transition, which would not
be acceptable. The offset-correction loop effectively
AC-couples the filter output to the programmable-gain
amplifier input. The network generates a highpass corner frequency at:
f-3dB(kHz) = 12.5/C(µF)
Specified performance is achieved when the input is
driven differentially. The MAX3507 may be driven single-ended. To drive the device in this manner, one of
the input pins must be capacitively coupled to ground.
Use a capacitor whose value is large enough to allow
for a low-impedance path to ground at the lowest frequency of operation. For operation down to 5MHz, a
0.001µF capacitor is suggested.
Programmable-Gain Amplifier
The programmable-gain amplifier (PGA) consists of the
variable-gain amplifier (VGA) and the digital-to-analog
converter (DAC), which provide better than 55dB of
output-level control in 0.5dB steps. The PGA is implemented as a programmable Gilbert-cell attenuator. It
uses a differential architecture to achieve maximum linearity. The gain of the PGA is determined by a 7-bit
_______________________________________________________________________________________
7
MAX3507
Pin Description
MAX3507
Upstream CATV Amplifier with
On-Chip Anti-Alias Filter
word (D6–D0) programmed through the serial data
interface (Tables 1 and 2).
Equalizer Function
It is possible to add passband amplitude equalization
to the MAX3507. This is accomplished by adding polezero peaking to the Gm stage of the PGA. Placing a
series RC network between pins EQ+ and EQ- realizes
the peaking function. Refer to Typical Operating
Characteristics for typical values and the associated
degree of equalization.
Power Amplifier
The power amplifier is a Class A differential amplifier
capable of driving +64dBmV (QPSK) differentially. This
architecture provides superior even-order distortion
performance but requires that a transformer be used to
convert to a single-ended output. In transmit-disable
mode, the output amplifier is shut off. Disabling the output devices also allows the lowest standby noise.
To achieve the proper load line, the output impedance
of the power amplifier is 300Ω differential. To match the
output impedance to a 75Ω load, the transformer must
have a turns ratio (voltage ratio) of 2:1 (4:1 impedance
ratio). The differential amplifier is biased directly from
the +5V supply using the center tap of the output transformer. This provides a significant benefit when switching between transmit mode and transmit disable mode.
Stored energy due to bias currents will cancel within
the transformer and prevent switching transients from
reaching the load.
Table 1. Serial-Interface Control Word
BIT
MNEMONIC
DESCRIPTION
7 (MSB)
D7
High-Power/Low-Noise Mode
Select
6
D6
Gain Code, Bit 6
5
D5
Gain Code, Bit 5
4
D4
Gain Code, Bit 4
3
D3
Gain Code, Bit 3
2
D2
Gain Code, Bit 2
1
D1
Gain Code, Bit 1
0 (LSB)
D0
Gain Code, Bit 0
for significantly lower output noise and lower
transmit/transmit disable transients.
The full range of gain codes (D6–D0) may be used in
either mode. For DOCSIS applications, HP mode is recommended for output levels at or above +42dBmV, and
LN mode is recommended for output levels below
+42dBmV.
Shutdown Mode
In normal operation, the shutdown pin (SHDN) is held
high. When SHDN is set low, all circuits within the
device are disabled. Only leakage currents flow in this
state. Data stored within the serial data interface latches will be lost upon entering this mode. Current consumption is reduced to 1µA (typ) in shutdown mode.
Serial Interface
The serial interface has an active-low enable (CS) to
bracket the data, with data clocked in MSB first on the
rising edge of SCLK. Data is stored in the storage latch
on the rising edge of CS. The serial interface controls
the gain state of the PGA and the output amplifier.
Tables 1 and 2 show the register format. Serial interface
timing is shown in Figure 1.
Applications Information
Transmit High-Power and Low-Noise Modes
The MAX3507 has two transmit modes, high-power
(HP) mode and low-noise (LN) mode. Each of these
modes is controlled by D7 (MSB) of the 8-bit programming word. When D7 is a logical 1, HP mode is
enabled. When D7 is a logical 0, LN mode is enabled.
Each of these modes is characterized by the activation
of a distinct output stage. In HP mode, the output stage
exhibits a gain that is 15dB higher than gain in LN
mode. In LN mode, the lower gain output stage allows
8
Output Match
The MAX3507 output impedance is internally matched
to 300Ω. This 300Ω internal resistor is placed across
the OUT+ and OUT- terminals. When used in conjunction with a 2:1 (voltage ratio) transformer, the MAX3507
output impedance is matched to 75Ω.
To improve the output impedance matching for the highend frequency range (65MHz), a reactive match may be
employed as part of the ensuing diplex filter. The reactive match normally consists of a series inductor (180nH
typ) followed by a shunt capacitor (33pF typ), and is
placed directly after the output transformer. This match
will also improve the gain flatness substantially.
As mentioned above, the matching components may be
incorporated into the diplex filter design. Optimize the
input impedance of the diplex filter to be 35 + j35 (typ)
at 65MHz when using the specified output transformer.
Transformer
To match the output of the MAX3507 to a 75Ω load, a
2:1 (voltage ratio) transformer is required. This trans-
_______________________________________________________________________________________
Upstream CATV Amplifier with
On-Chip Anti-Alias Filter
D7
C
B
D6
D5
D4
D3
D
D2
D1
E
MAX3507
G
A
F
D0
E. tSCLKH
F. tSENH
G. tDATAH/tDATAL
A. tSENS
B. tSDAS
C. tSDAH
D. tSCLKL
Figure 1. Serial Interface Timing Diagram
Table 2. Chip-State Control Bits
SHDN
TXEN
D7
D6
D5
D4
D3
D2
D1
D0
GAIN STATE
(DECIMAL)
GAIN
(dB)
0
X
X
X
X
X
X
X
X
X
—
—
Shutdown
1
0
X
X
X
X
X
X
X
X
—
—
Transmit Disable Mode
1
1
1
X
X
X
X
X
X
X
—
—
Transmit Enable Mode,
High Power
1
1
0
X
X
X
X
X
X
X
—
—
Transmit Enable Mode,
Low Noise
1
1
0
0
1
1
0
0
0
0
48
-22.6
—
1
1
0
1
0
1
0
0
0
0
80
-6.29
—
1
1
0
1
1
0
1
1
1
0
110
8.68
—
1
1
1
1
0
1
0
1
1
0
86
11.69
—
1
1
1
1
1
0
1
1
1
0
110
23.7
—
1
1
1
1
1
1
1
1
0
1
125
31.0
—
STATES
Typical gain at TA = +25°C and VCC = +5V.
former must have adequate bandwidth to cover the
intended application. Note that most RF transformers
specify bandwidth with a 50Ω source on the primary
and a matching resistance on the secondary winding.
Operating in a 75Ω system will tend to shift the low-frequency edge of the transformer bandwidth specification up by a factor of 1.5, due to primary inductance.
Keep this in mind when specifying a transformer.
Bias to the output stage is provided through the center
tap on the transformer primary. This greatly diminishes
the on/off transients present at the output when switching between transmit and transmit disable modes.
Commercially available transformers typically have
adequate balance between half-windings to achieve
substantial transient cancellation.
Finally, keep in mind that transformer core inductance
varies proportionally with temperature. If the application
requires low temperature extremes (less than 0°C),
adequate primary inductance must be present to sustain low-frequency output capability as temperatures
_______________________________________________________________________________________
9
drop. In general, this will not be a problem, as modern
RF transformers have adequate bandwidth.
Input Circuit
To achieve rated performance, the inputs of the
MAX3507 must be driven differentially with an appropriate input level. The differential input impedance is
approximately 4kΩ. The MAX3507 has sufficient gain to
produce an output level of +64dBmV (QPSK through a
2:1 transformer) when driven with a +34dBmV input signal. Rated performance is achieved with this input level.
When a lower input level is present, the maximum output level will be reduced proportionally and output linearity will increase. If an input level greater than
+34dBmV is used, the 3rd-order distortion performance
will degrade.
If a single-ended source drives the MAX3507, one of
the input terminals must be capacitively coupled to
ground (IN+ or IN-). The value of this capacitor must be
large enough to look like a short circuit at the lowest frequency of interest. For operation at 5MHz with a 75Ω
source impedance, a value of 0.001µF will suffice.
Layout Issues
A well-designed PC board is an essential part of an RF
circuit. For best performance pay attention to powersupply layout issues as well as the output circuit layout.
pling capacitor at the central power-supply node. The
power-supply traces branch out from this node, each
going to a separate power-supply node in the circuit. At
the end of each of these traces is a decoupling capacitor that provides very low impedance at the frequency
of interest. This arrangement provides local power-supply decoupling at each power-supply pin. The powersupply traces must be made as thick as practical.
Ground inductance degrades distortion performance.
Therefore, ground plane connections to pins 4, 8, 12, 23,
and 26 should be made with multiple vias if necessary.
Output Circuit Layout
The differential implementation of the MAX3507’s output
has the benefit of significantly reducing even-order distortion, the most significant of which is 2nd-harmonic
distortion. The degree of distortion cancellation
depends on the amplitude and phase balance of the
overall circuit. It is important to keep the trace lengths
from the output pins equal.
Chip Information
TRANSISTOR COUNT: 1457
Power-Supply Layout
For minimal coupling between different sections of the
MAX3507, the ideal power-supply layout is a star configuration. This configuration has a large-value decou-
10
EQ-
EQ+
GND
VCC
N.C.
GND
VCC
27
26
25
24
23
22
TOP VIEW
28
Pin Configuration
BIASF
1
21
TXEN
DC+
2
20
N.C.
19
OUT+
18
OUT-
DC-
3
GND
4
VCC
5
17
N.C.
IN+
6
16
CEXT
IN-
7
15
N.C.
10
11
12
13
14
SDA
GND
N.C.
SHDN
9
CS
SCLK
8
MAX3507
GND
MAX3507
Upstream CATV Amplifier with
On-Chip Anti-Alias Filter
______________________________________________________________________________________
Upstream CATV Amplifier with
On-Chip Anti-Alias Filter
______________________________________________________________________________________
11
MAX3507
Package Information
Upstream CATV Amplifier with
On-Chip Anti-Alias Filter
MAX3507
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.