PD - 97126
IRFP3077PbF
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
Benefits
l Worldwide Best RDS(on) in TO-247
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
HEXFET® Power MOSFET
D
G
S
VDSS
RDS(on) typ.
max.
ID (Silicon Limited)
75V
2.8m:
3.3m:
200A c
ID (Package Limited)
120A
D
G
D
S
TO-247AC
G
D
S
G ate
Drain
Source
Absolute Maximum Ratings
Max.
Units
ID @ TC = 25°C
Symbol
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Parameter
200c
A
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
140c
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Wire Bond Limited)
120
IDM
Pulsed Drain Current d
850
PD @TC = 25°C
Maximum Power Dissipation
340
W
W/°C
V
Linear Derating Factor
2.3
VGS
Gate-to-Source Voltage
± 20
dV/dt
TJ
Peak Diode Recovery f
2.5
Operating Junction and
-55 to + 175
TSTG
Storage Temperature Range
V/ns
°C
300
Soldering Temperature, for 10 seconds
(1.6mm from case)
10lbxin (1.1Nxm)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
EAS (Thermally limited)
Single Pulse Avalanche Energy e
IAR
Avalanche Currentc
EAR
Repetitive Avalanche Energy g
mJ
200
See Fig. 14, 15, 22a, 22b,
A
mJ
Thermal Resistance
Typ.
Max.
RθJC
Symbol
Junction-to-Case j
–––
0.44
RθCS
Case-to-Sink, Flat Greased Surface
0.24
–––
RθJA
Junction-to-Ambient j
–––
40
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Parameter
Units
°C/W
1
3/3/08
IRFP3077PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
V(BR)DSS
ΔV(BR)DSS/ΔTJ
RDS(on)
VGS(th)
IDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Input Resistance
RG
Min. Typ. Max. Units
75
–––
–––
2.0
–––
–––
–––
–––
–––
––– –––
0.091 –––
2.8
3.3
–––
4.0
–––
20
––– 250
––– 100
––– -100
1.2
–––
Conditions
V VGS = 0V, ID = 250μA
V/°C Reference to 25°C, ID = 5mA
mΩ VGS = 10V, ID = 75A
V VDS = VGS, ID = 250μA
μA VDS = 75V, VGS = 0V
VDS = 75V, VGS = 0V, TJ = 125°C
nA VGS = 20V
VGS = -20V
Ω f = 1MHz, open drain
d
g
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Parameter
Min. Typ. Max. Units
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
i
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
h
160
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
160
37
42
25
87
69
95
9400
820
350
1090
1260
–––
220
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
nC
ns
pF
Conditions
VDS = 50V, ID = 75A
ID = 75A
VDS = 38V
VGS = 10V
VDD = 38V
ID = 75A
RG = 2.1Ω
VGS = 10V
VGS = 0V
VDS = 50V
ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 60V
VGS = 0V, VDS = 0V to 60V
g
g
j, See Fig.11
h, See Fig. 5
Diode Characteristics
Symbol
Parameter
IS
Continuous Source Current
ISM
(Body Diode)
Pulsed Source Current
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
(Body Diode)di
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 120A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.028mH
RG = 25Ω, IAS = 120A, VGS =10V. Part not recommended for use
above this value .
ISD ≤ 75A, di/dt ≤ 400A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
2
Min. Typ. Max. Units
–––
–––
––– 200
–––
c
850
A
Conditions
MOSFET symbol
D
showing the
integral reverse
G
p-n junction diode.
––– –––
1.3
V TJ = 25°C, IS = 75A, VGS = 0V
VR = 64V,
–––
42
63
ns TJ = 25°C
IF = 75A
TJ = 125°C
–––
50
75
di/dt = 100A/μs
–––
59
89
nC TJ = 25°C
TJ = 125°C
–––
86
130
–––
2.5
–––
A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
g
S
g
Pulse width ≤ 400μs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
Rθ is measured at TJ approximately 90°C
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IRFP3077PbF
1000
1000
BOTTOM
100
4.5V
BOTTOM
4.5V
100
≤ 60μs PULSE WIDTH
Tj = 175°C
≤ 60μs PULSE WIDTH
Tj = 25°C
10
10
0.1
1
10
0.1
100
Fig 1. Typical Output Characteristics
10
100
Fig 2. Typical Output Characteristics
1000
2.5
100
TJ = 25°C
VDS = 25V
≤ 60μs PULSE WIDTH
1
2.0
3.0
4.0
5.0
VGS = 10V
2.0
(Normalized)
TJ = 175°C
10
ID = 75A
RDS(on) , Drain-to-Source On Resistance
ID, Drain-to-Source Current(Α)
1
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
6.0
7.0
1.5
1.0
0.5
8.0
-60 -40 -20
VGS, Gate-to-Source Voltage (V)
16000
VGS, Gate-to-Source Voltage (V)
Coss = Cds + Cgd
Ciss
8000
4000
Coss
Crss
10
100
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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ID= 75A
VDS = 60V
16
VDS= 38V
VDS= 17V
12
8
4
0
0
1
20 40 60 80 100 120 140 160 180
Fig 4. Normalized On-Resistance vs. Temperature
20
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
12000
0
TJ , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
C, Capacitance (pF)
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
0
40
80
120
160
200
240
280
QG Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFP3077PbF
10000
ID, Drain-to-Source Current (A)
ISD , Reverse Drain Current (A)
1000.0
TJ = 175°C
100.0
10.0
TJ = 25°C
1.0
OPERATION IN THIS AREA
LIMITED BY R DS (on)
1000
100μsec
10msec
100
LIMITED BY PACKAGE
10
1
0.1
0.1
0.0
0.4
0.8
1.2
1.6
0.1
2.0
LIMITED BY PACKAGE
ID , Drain Current (A)
200
160
120
80
40
0
75
100
125
150
175
V(BR)DSS , Drain-to-Source Breakdown Voltage
240
50
100.0
100
90
80
70
-60 -40 -20
TC , Case Temperature (°C)
0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Drain-to-Source Breakdown Voltage
3.0
EAS, Single Pulse Avalanche Energy (mJ)
1000
2.5
2.0
Energy (μJ)
10.0
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
25
1.0
VDS , Drain-toSource Voltage (V)
VSD , Source-to-Drain Voltage (V)
1.5
1.0
0.5
0.0
ID
22A
40A
BOTTOM 120A
TOP
800
600
400
200
0
0
20
40
60
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
DC
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
1msec
80
25
50
75
100
125
150
175
Starting TJ, Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
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IRFP3077PbF
1
Thermal Response ( Z thJC )
D = 0.50
0.1
0.20
0.10
0.05
0.01
0.02
0.01
τJ
τJ
τ1
R2
R2
R3
R3
Ri (°C/W)
τC
τ2
τ1
τ3
τ2
Ci= τi/Ri
Ci= τi/Ri
SINGLE PULSE
( THERMAL RESPONSE )
0.001
R1
R1
τ3
τ
τι (sec)
0.083889 0.000083
0.190848 0.000995
0.165682 0.007038
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
100
0.01
0.05
0.10
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
240
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 120A
200
160
120
80
40
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFP3077PbF
24
ID = 1.0A
ID = 1.0mA
ID = 250μA
20
3.0
16
IRRM - (A)
VGS(th) Gate threshold Voltage (V)
4.0
2.0
12
8
IF = 30A
VR = 64V
4
1.0
-75
-50 -25
0
25
50
75
TJ = 125°C
TJ = 25°C
0
100 125 150 175
100 200 300 400 500 600 700 800 900 1000
TJ , Temperature ( °C )
dif / dt - (A / μs)
Fig 16. Threshold Voltage Vs. Temperature
Fig. 17 - Typical Recovery Current vs. dif/dt
24
400
20
300
QRR - (nC)
IRRM - (A)
16
12
8
4
IF = 45A
VR = 64V
200
IF = 30A
VR = 64V
100
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
0
0
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
dif / dt - (A / μs)
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
400
QRR - (nC)
300
200
100
0
IF = 45A
VR = 64V
TJ = 125°C
TJ = 25°C
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFP3077PbF
D.U.T
Driver Gate Drive
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
RG
+
V
- DD
IAS
VGS
20V
tp
A
0.01Ω
I AS
Fig 22a. Unclamped Inductive Test Circuit
LD
Fig 22b. Unclamped Inductive Waveforms
VDS
VDS
90%
+
VDD -
10%
D.U.T
VGS
VGS
Pulse Width < 1μs
Duty Factor < 0.1%
td(on)
Fig 23a. Switching Time Test Circuit
tr
td(off)
tf
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
L
DUT
0
VCC
Vgs(th)
1K
Qgs1 Qgs2
Fig 24a. Gate Charge Test Circuit
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Qgd
Qgodr
Fig 24b. Gate Charge Waveform
7
IRFP3077PbF
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
TO-247AC Part Marking Information
EXAMPLE: THIS IS AN IRFPE30
WIT H AS S EMBLY
LOT CODE 5657
AS S EMBLED ON WW 35, 2001
IN T HE AS S EMBLY LINE "H"
Note: "P" in ass embly line pos ition
indicates "Lead-Free"
INTERNATIONAL
RECT IFIER
LOGO
PART NUMBER
IRFPE30
56
135H
57
AS S EMBLY
LOT CODE
DAT E CODE
YEAR 1 = 2001
WEEK 35
LINE H
TO-247AC packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
8
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 03/08
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