19-3251; Rev 0; 4/04 200Mbps SFP Limiting Amplifier Features The MAX3969 limiting amplifier with PECL data outputs is ideal for low-cost ATM, Fast Ethernet, FDDI and ESCON fiber optic receivers. The MAX3969 features 1mVP-P input sensitivity and an integrated power detector that senses the input signal power. It provides a received-signal-strength indicator (RSSI), which is an analog indication of the power level. Signal strength is also indicated by the complementary TTL loss-of-signal (LOS) outputs and the PECL signaldetect (SD) output, both of which indicate the power level relative to a programmable threshold. The threshold can be adjusted to detect signal amplitudes as low as 2.7mVP-P. An optional squelch function disables switching of the data outputs by holding them at a known state when the signal is below the programmed threshold. ♦ 1mVP-P Input Sensitivity ♦ Loss-of-Signal Detector with Programmable Threshold ♦ TTL LOS and PECL Signal Detect ♦ Analog Received-Signal-Strength Indicator ♦ Output Squelch Function ♦ Compatible with 4B/5B Data Coding Ordering Information The MAX3969 is available in die form and a 4mm x 4mm, 20-pin thin QFN package. PART TEMP RANGE MAX3969ETP Applications -40°C to +85°C 20 Thin QFN MAX3969E/D** SFP/SFF Transceivers PINPACKAGE — PKG CODE T2044-2 Dice* — *Dice are designed to operate over a -40°C to +100°C junction temperature (TJ) range, but are tested and guaranteed only at TA = +25°C. Fast Ethernet/FDDI Transceivers 155Mbps LAN ATM Transceivers **Future product—contact factory for availability. ESCON Receivers FTTx Transceivers Typical Application Circuits SFP OPTICAL RECEIVER WITH DIAGNOSTICS HOST BOARD VCC +2.97V TO +3.63V CAZ 0.027µF CFILTER 0.01µF DIAGNOSTIC MONITOR CZP CZN 0.01µF FILTER RSSI VCC RLOS 4.7kΩ TO 10kΩ VCCO LOS VCC CIN 0.01µF VCC FILT OUT- LOS SQUELCH SD MAX3969 IN- 0.1µF OUT- IN MAX3657 GND OUT+ IN+ CIN 0.01µF OUT+ INV VTH 0.1µF GND 150Ω R1 100kΩ 150Ω R2 Typical Application Circuits continued at end of data sheet. Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3969 General Description MAX3969 200Mbps SFP Limiting Amplifier ABSOLUTE MAXIMUM RATINGS Power-Supply Voltage Range (VCC, VCCO) ..........-0.5V to +7.0V Voltage at FILTER, RSSI, IN+, IN-, CZP, CZN, SQUELCH, INV, VTH..................................................-0.5V to (VCC + 0.5V) TTL Output Current (LOS, LOS) .........................................±9mA PECL Output Current (OUT+, OUT-, SD) .........................±50mA Differential Voltage Between CZP and CZN..........-1.5V to +1.5V Differential Voltage Between IN+ and IN- .............-1.5V to +1.5V Continuous Power Dissipation (TA = +85°C) 20-Pin Thin QFN (derate 16.9mW/°C above +85°C) ....1099mW Operating Junction Temperature Range (die).....-40°C to +150°C Die Attach Temperature...................................................+400°C Storage Temperature Range .............................-50°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +2.97V to +5.5V, PECL outputs terminated with 50Ω to VCC - 2V, R1 = 100kΩ, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) (Note 1) PARAMETER CONDITIONS Supply Current PECL outputs open LOS Hysteresis Input = 4.0mVP-P (Note 2) MIN 3.0 Squelch Input Current TYP MAX UNITS 22 45 mA 5 8.0 dB 27 100 µA PECL Output-Voltage High (Note 3) -1085 -880 mV PECL Output-Voltage Low (Note 3) -1830 -1550 mV Input = 7mVP-P or 90mVP-P, 0°C to +85°C -3.0 +3.0 dB Input = 7mVP-P or 90mVP-P, -40°C to +85°C -3.6 +3.6 dB 2.7 mVP-P LOS Assert Accuracy Minimum LOS Assert Input Maximum LOS Deassert Input 143 Input Sensitivity (Note 4) Input Overload (Note 4) TTL Output High RLOS = 4.7kΩ to 10kΩ mVP-P 1 2.4 (Note 5) TTL Output Low IOL = 800µA Data Output Transition Time 20% to 80%, Input > 4mVP-P (Note 4) Pulse-Width Distortion Input > 4mVP-P (Notes 4, 6) LOS, SD Assert/Deassert Time CFILTER = 0.01µF 10 2 0.35 mVP-P mVP-P 3.0 TTL Output Leakage Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: 4 1500 V 1 20 µA 0.2 0.5 V 0.8 1.20 ns 50 250 ps Dice are tested and guaranteed only at TA = +25°C. LOS hysteresis = 20log(VLOS-DEASSERT / VLOS-ASSERT). Relative to supply voltage (VCCO). AC characteristics are guaranteed by design and characterization. Input < LOS threshold (LOS = HIGH), VLOS = 2.4V. Pulse-width distortion = [(width of wider pulse) - (width of narrower pulse)] / 2, measured with 100Mbps 1-0 pattern. _______________________________________________________________________________________ µs 200Mbps SFP Limiting Amplifier OUTPUT EYE DIAGRAM (VIN = 2mVP-P, 155Mbps, 223 - 1 PRBS) SUPPLY CURRENT vs. TEMPERATURE (PECL OUTPUTS OPEN) SUPPLY CURRENT (mA) MAX3969 toc03 MAX3969 toc01 60 OUTPUT EYE DIAGRAM (VIN = 1500mVP-P, 155Mbps, 223 - 1 PRBS) MAX3969 toc02 55 50 45 40 35 30 200mV/div 200mV/div 25 20 15 10 5 0 -40 -15 10 35 60 1ns/div 1ns/div BIT ERROR RATIO vs. DIFFERENTIAL INPUT VOLTAGE RSSI VOLTAGE vs. DIFFERENTIAL INPUT VOLTAGE 85 2.40 10-06 10-07 10-08 1.20 10-12 1.00 0.2 0.3 0.4 0.5 0.6 0.7 DIFFERENTIAL INPUT VOLTAGE (mVP-P) RSSI VOLTAGE vs. TEMPERATURE (LOS LOW, RSSI LOAD > 10kΩ) POWER-DETECT THRESHOLD vs. R2 (R1 = 100kΩ) MAX3969 toc07 2.3 2.2 INPUT = 100mVP-P 2.1 2.0 INPUT = 50mVP-P 1.9 1.8 1.7 INPUT = 10mVP-P 1.6 1.5 0 1000 10,000 INPUT = 5mVP-P 0.1 1000 100 0.8 SD LOW/ LOS HIGH 155Mbps 223 - 1 PRBS -40 -20 0 20 40 60 AMBIENT TEMPERATURE (°C) 80 100 1000 100 10 155Mbps 223-1 PRBS 9 8 7 R2 = 50kΩ 6 5 4 R2 = 10kΩ 3 2 1 0 1 1.4 10 LOSS-OF-SIGNAL HYSTERESIS vs. TEMPERATURE SD HIGH/ LOS LOW 10 1 DIFFERENTIAL INPUT VOLTAGE (mVP-P) MAX3969 toc08 100 DIFFERENTIAL INPUT VOLTAGE (mVP-P) 10 LOS HIGH 1.40 10-11 DIFFERENTIAL INPUT VOLTAGE (mVP-P) 1 LOS LOW 2.00 1.60 10-10 0.1 2.20 1.80 10-09 800 0.01 2.60 10-05 MAX3969 toc09 1000 RSSI LOAD > 10kΩ 155Mbps 223 - 1 PRBS 2.80 VRSSI (V) 1200 3.00 20log (VDEASSERT / VASSERT) (dB) 1400 155Mbps 223 - 1 PRBS 10-04 BIT ERROR RATIO 1600 600 VRSSI (V) 10-03 MAX3969 toc04 DIFFERENTIAL OUTPUT VOLTAGE (mVP-P) 1800 MAX3969 toc05 TRANSFER FUNCTION MAX3969 toc06 AMBIENT TEMPERATURE (°C) 10 20 30 40 50 60 70 80 90 100 110 120 R2 (kΩ) -40 -15 10 35 60 85 AMBIENT TEMPERATURE (°C) _______________________________________________________________________________________ 3 MAX3969 Typical Operating Characteristics (VCC = +3.3V, PECL outputs terminated with 50Ω to VCC - 2V, R1 = 100kΩ, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VCC = +3.3V, PECL outputs terminated with 50Ω to VCC - 2V, R1 = 100kΩ, TA = +25°C, unless otherwise noted.) POWER-DETECT TIMING WITH SQUELCH (INPUT = 12mVP-P, CFILTER = 0.01µF, R2 = 15kΩ, 155Mbps, 223 - 1 PRBS) 100Mbps 1-0 PATTERN 90 LOS SD 70 60 INPUT DATA THROUGH 117MHz FILTER 50 40 UNFILTERED INPUT DATA 30 20 1.4 TRANSITION TIME (ns) OUT 80 1.6 1.2 1.0 0.8 0.6 0.4 0.2 10 0 0 1 10µs/div MAX3969 toc12 100 MAX3969 toc11 MAX3969 toc10 IN DATA OUTPUT TRANSITION TIME vs. TEMPERATURE PULSE-WIDTH DISTORTION vs. DIFFERENTIAL INPUT VOLTAGE PULSE-WIDTH DISTORTION (ps) MAX3969 200Mbps SFP Limiting Amplifier 10 100 1000 10,000 -40 DIFFERENTIAL INPUT VOLTAGE (mVP-P) -15 10 35 60 85 AMBIENT TEMPERATURE (°C) Pin Description 4 PIN NAME FUNCTION 1 INV Inverting Input of Internal Op Amp that Sets Power-Detect Threshold Voltage (Figure 1). Connect a resistor from VTH to INV (R2), and from INV to ground (R1 = 100kΩ), to program the desired threshold voltage. 2 FILTER 3 RSSI Filter Output of Logarithmic Full-Wave Detectors (FWDs). The FWD outputs are summed together at FILTER to generate the RSSI output. Connect a capacitor from FILTER to VCC for proper operation. Received-Signal-Strength Indicator Output. The voltage at RSSI indicates the input-signal power. The RSSI output is reduced approximately 120mV when LOS is asserted. 4 IN- Inverting Data Input 5 IN+ Noninverting Data Input 6 , 7, 8 GND Ground 9 CZP Autozero Capacitor Input. Connect a 0.027µF capacitor between CZP and CZN. 10 CZN Autozero Capacitor Input. Connect a 0.027µF capacitor between CZP and CZN. 11 VCCO Output-Buffer Supply Voltage. Connect to the same potential as VCC. 12 OUT+ Noninverting PECL Data Output. Terminate with 50Ω to (VCC - 2V). 13 OUT- Inverting PECL Data Output. Terminate with 50Ω to (VCC - 2V). Signal Detect, PECL Output. The SD output is high when input power is above the power-detect threshold, and low when input power is below the power-detect threshold. This pin is PECLcompatible and should be terminated with 50Ω to (VCC - 2V) or equivalent. 14 SD 15 LOS Loss-of-Signal Output, TTL Open Collector (with ESD Protection). The LOS output is high when input power is below the power-detect threshold, and low when input power is above the power-detect threshold. 16 LOS Inverted Loss-of-Signal Output, TTL Open Collector (with ESD Protection). The LOS output is low when input power is below the power-detect threshold, and high when input power is above the power-detect threshold. _______________________________________________________________________________________ 200Mbps SFP Limiting Amplifier PIN NAME FUNCTION 17, 18 VCC 19 SQUELCH 20 VTH EP Exposed Pad Supply Voltage Squelch Input. The squelch function disables the data outputs by forcing OUT- low and OUT+ high when the signal is below the power-detect threshold. Connect to GND or leave unconnected to disable squelch. Connect to VCC to enable squelch. Output of Internal Op Amp that Sets Power-Detect Threshold Voltage (Figure 1). Connect a resistor from VTH to INV (R2) and from INV to ground (R1 = 100kΩ), to program the desired threshold voltage. Ground. The exposed pad must be soldered to the circuit board ground for proper thermal and electrical performance. CAZ CZP VCC VCCO CZN OFFSET CORRECTION 1 CIN IN- MAX3969 1 PECL O OUT+ IN+ SQUELCH CIN VCC OUT- FWD FWD FWD RSSI FILTER TTL CFILTER LOS 1.2V REFERENCE PECL R1 100kΩ LOS INV SD VTH R2 GND Figure 1. Functional Diagram Detailed Description The MAX3969 contains a series of limiting amplifiers and power detectors, offset correction, data-squelch circuitry, TTL buffers for LOS outputs, and PECL output buffers for signal detect (SD) and data outputs. See Figure 1 for the functional diagram. Gain Stages and Offset Correction A cascade of limiting amplifiers provides approximately 65dB of combined small-signal gain. The large gain makes the amplifier susceptible to small DC offsets in the signal path. To correct DC offsets, the amplifier has an internal feedback loop that acts as a DC autozero circuit. By correcting the DC offsets, the limiting amplifier sensitivity and power-detector accuracy are improved. The offset correction is optimized for data streams with a 50% duty cycle. A different average duty cycle results in increased pulse-width distortion and loss of sensitivity. The offset-correction circuitry is less sensitive to variations of input duty cycle (for example, the 40% to 60% duty cycle encountered in 4B/5B coding) when the input is less than 30mVP-P. The data inputs must be AC-coupled for the offset correction loop to function properly. Differential input impedance is >5kΩ. _______________________________________________________________________________________ 5 MAX3969 Pin Description MAX3969 200Mbps SFP Limiting Amplifier Power Detector PECL Outputs Each amplifier stage contains a logarithmic FWD, which indicates the RMS input signal power. The FWD outputs are summed together at the FILTER pin where the signal is filtered by an external capacitor (CFILTER) connected between FILTER and VCC. The FILTER signal generates the RSSI output voltage (VRSSI), which is proportional to the input power in decibels. When LOS is low, VRSSI is approximated by the following equation: VRSSI (V) = 1.2V + 0.5log (VIN) where, VIN is the data input voltage measured in mVP-P. The data outputs (OUT+, OUT-) and signal-detect output (SD) are supply-referenced PECL outputs. See Figure 2 for the equivalent output circuit. Both data outputs must be terminated for proper operation, but the SD output can be left open if not required in the application. The proper termination for a PECL output is 50Ω to (VCC - 2V), but other standard termination techniques can be used. For more information on PECL terminations and how to interface with other logic families, refer to Maxim Application Note HFAN-01.0: Introduction to LVDS, PECL, and CML. This relation translates to a 25mV increase in VRSSI for every 1dB increase in VIN. The RSSI output is reduced approximately 120mV when LOS is high. Typically the RSSI output is connected to an A/D converter for diagnostic monitoring. This output can be left open if not required in the application. The RSSI output is designed to drive a minimum load resistance of 10kΩ to ground, and a maximum capacitance of 10pF. A 10kΩ series resistor is required to buffer loads greater than 10pF. The LOS outputs (LOS, LOS) are implemented with open-collector, Schottky-clamped, ESD-protected, TTLcompatible outputs. See Figure 3 for the equivalent output circuit. The LOS outputs require external pullup resistors for proper operation. Resistor values between 4.7kΩ and 10kΩ are recommended. If the LOS outputs are not required for the application, they can be left open. Signal-Strength Comparator Design Procedure A comparator is used to indicate the input signal strength relative to a user-programmable threshold. One of the comparator inputs is connected to the RSSI output signal, and the other is connected to the threshold voltage (VTH), which is set externally and provides a trip point for signal-strength indication. When the signal strength is above the threshold, the SD output asserts high and the LOS output deasserts low. Likewise, when the signal strength falls below the threshold, SD deasserts low and LOS asserts high. To ensure chatter-free operation, the comparator is designed with approximately 5dB of hysteresis. Squelch The squelch function disables the data outputs by forcing OUT- low and OUT+ high when the input signal is below the programmed threshold. This function ensures that when there is a loss of signal, the limiting amplifier and all downstream devices do not respond to input noise. Connect SQUELCH to GND or leave it unconnected to disable squelch. Connect SQUELCH to VCC to enable squelch. 6 TTL Outputs Program the Power-Detect Threshold The suggested procedure for setting the power-detect threshold is given below and is illustrated in Figure 4. 1) Determine the maximum receiver sensitivity (RX_MAX) in dBm and the PIN-TIA responsivity (G) in V/W. 2) Calculate the differential voltage swing (VIN_SEN) at the MAX3969 inputs while operating at sensitivity. VIN_SEN = 10(RX_MAX / 10) x 2 x G 3) Calculate the threshold voltage (VIN_TH) at which LOS must be low (SD must be high) by allowing 3.6dB (1.8dB optical) margin for power-detector accuracy. VIN_TH = VIN_SEN x 0.66 4) Use VIN_TH and the line labeled (SD HIGH / LOS LOW) in the Power-Detect Threshold vs. R2 graph in the Typical Operating Characteristics to determine the value of R2. Select R1=100kΩ. _______________________________________________________________________________________ 200Mbps SFP Limiting Amplifier MAX3969 10 log(OPTICAL POWER) VCCO PIN-TIA RESPONSIVITY = G RX_MAX (SENSITIVITY) 1.8dB SD HIGH / LOS LOW 2.5dB SD LOW / LOS HIGH OUTOUT+ ESD STRUCTURES 5dB 3.6dB VIN_TH VIN_SEN 20 log(VIN) Figure 4. Signal Levels for Power-Detect Threshold Select CFILTER For SFP/SFF, FDDI, 155Mbps ATM LAN, Fast Ethernet, and ESCON receivers, Maxim recommends CFILTER = 0.01µF. This capacitor value ensures chatter-free LOS/SD and provides a typical assert/deassert time of 10µs. For other applications, the value of CFILTER can be calculated using the following equation: CFILTER = τ / 825Ω where τ is the desired time constant of the power detector. Figure 2. Equivalent PECL Output Circuit VCCO Select CAZ and CIN LOS/LOS ESD STRUCTURES External-coupling capacitors (CIN) are required on the data inputs for the offset correction loop to function properly. The offset correction loop bandwidth is determined by the external capacitor (C AZ ) connected between CZP and CZN. The poles associated with CIN and CAZ must work together to provide a flat response at the lower -3dB corner frequency. For SFP/SFF, FDDI, 155Mbps ATM LAN, Fast Ethernet, and ESCON receivers, Maxim recommends the following: CIN = 0.01µF CAZ = 0.027µF Figure 3. Equivalent TTL Output Circuit _______________________________________________________________________________________ 7 Applications Information Wire Bonding For high-current density and reliable operation, the MAX3969 uses gold metalization. For best results, use gold-wire ball-bonding techniques. Use caution if attempting wedge bonding. Die pad size is 4 mils x 4 mils. Die thickness is 16 mils. Table 1 lists the bond pad coordinates for the MAX3969. The origin for pad coordinates is defined as the bottom left corner of the bottom left pad. All pad locations are referenced from the origin and indicate the center of the pad where the bond wire should be connected. Refer to Maxim Application Note HFAN-08.0.1: Understanding Bonding-Coordinates and Physical Die Size for detailed information. VCC VCC LOS 20 19 18 17 16 1 FILTER 2 RSSI 3 ININ+ 15 SD 13 OUT- 4 12 OUT+ 5 11 VCCO 6 7 8 9 10 GND CZP CZN MAX3969 THIN QFN 8 LOS 14 GND INV SQUELCH TOP VIEW VTH Pin Configuration GND MAX3969 200Mbps SFP Limiting Amplifier Table 1. Bond Pad Coordinates PAD NAME COORDINATES (µm) X Y 1 INV 46.6 659.5 2 FILTER 46.6 505.6 3 RSSI 46.6 351.7 4 IN- 46.6 197.8 5 IN+ 46.6 46.6 6 GND 195.1 -99.1 7 GND 432.7 -99.1 8 GND 589.3 -99.1 9 CZP 743.2 -99.1 10 CZN 945.7 -99.1 11 VCCO 1204.9 -96.4 12 OUT+ 1204.9 81.7 13 OUT- 1204.9 262.6 14 SD 1204.9 492.1 15 LOS 1204.9 697.3 16 LOS 1053.7 818.8 17 VCC 808.0 818.8 18 VCC 586.6 818.8 19 SQUELCH 432.7 818.8 20 VTH 195.1 818.8 Chip Information TRANSISTOR COUNT: 915 SUBSTRATE CONNECTED TO GND PROCESS: Silicon Bipolar DIE THICKNESS: 16 mils _______________________________________________________________________________________ 200Mbps SFP Limiting Amplifier INV 1 FILTER 2 RSSI 3 IN- 4 IN+ 5 ORIGIN VTH SQUELCH VCC VCC LOS 20 19 18 17 16 15 LOS 14 SD 47mil (1.19mm) 6 7 8 9 10 GND GND GND CZP CZN 13 OUT- 12 OUT+ 11 VCCO 57mil (1.45mm) _______________________________________________________________________________________ 9 MAX3969 Chip Topography 200Mbps SFP Limiting Amplifier MAX3969 Typical Application Circuits (continued) CAZ 0.027µF VCC CFILTER 0.01µF SFF OR 1 x 9 MSA RECEIVER CZP CZN 0.01µF FILTER RSSI VCC VCCO LOS VCC CIN 0.01µF VCC FILT OUT- LOS SQUELCH SD MAX3969 IN- OUTIN MAX3657 GND OUT+ IN+ CIN 0.01µF OUT+ INV R1 100kΩ VTH GND 50Ω 50Ω R2 VCC - 2V 10 ______________________________________________________________________________________ 50Ω 200Mbps SFP Limiting Amplifier 24L QFN THIN.EPS PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm 21-0139 C 1 2 PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm 21-0139 C 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX3969 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)