UX 2103 TTL output Limiting Amplifier General Description Pin Configuration The UX2103 is a high gain limiting amplifier designed for PDH fiber optical receiver systems, accepting a wide range of input AC voltages and providing TTL output level. It integrates a signal detector, with programmable LOS threshold. It is available in TSSOP 16-pin packages. Features +3.3V or +5V Power Supply 1mV Differential Input Sensitivity (BER=10-10) CMOS Configuration output with TTL Figure 1. Pin Configuration TSSOP 16 level Alarm Level Compatible with PECL, TTL and CMOS Level Typical Application Circuit Figure 2. Typical Application Circuit 2007 Preliminary Datasheet www.uxfastic.com 1 UX 2103 TTL output Limiting Amplifier Pin Description Pin No. Name Function Auto-zero capacitor pin. A capacitor connected between this pin and AZ2 sets the 1 AZ1 time constant of the offset correction loop. The offset correction is disabled when the AZ1 and AZ2 pins are shorted together. See AZ1. 2 AZ2 3 GNDA 4 INP Positive data input 5 INN Negative data input 6 VCCA 7 CF 8 JAM Analog Supply Ground. Must be at same potential as GNDE pin. Analog Supply Voltage. Must be at the same potential as the VCCE pin. Level-detect filter capacitor pin. Connect a capacitor between this pin and VCCA. The squelch function is disabled when JAM is connected to ground. The automatic squelch function is enabled when JAM is connected to the LOSP. Positive Loss-of-Signal output, CMOS level, compatible with PECL and TTL. LOSP is 9 LOSP low when the level of the input signal is above the preset threshold set by the VSET input. LOSP is high when the signal level drops below the threshold. Normally connected to JAM pin to enable automatic squelch function to operate. Negative Loss-of-signal output, CMOS level, compatible with PECL and TTL. LOSN is 10 LOSN high when the level of the input signal is above the preset threshold set by the VSET input. LOSN is low when the signal level drops below the threshold. Indicates Input signal level status. 11 GNDE Digital Supply Ground. Must be the same potential as the GNDA pin. 12 N.C. No Connection. 13 OUTP Positive data output, CMOS Configuration with TTL level. 14 VCCE Digital Supply Voltage. Must be at the same potential as the VCCA pin. 15 V3V 5V to 3V conversion output pin.No connection or can connect a capacitor between this pin and GND. Loss-of-Signal Threshold Pin. Resistor (RSET) to ground sets the LOS threshold. This 16 VSET pin can be left open if the LOS detect function is not required and JAM is connected to ground, otherwise connect VSET to ground. Absolute Maximum Ratings Symbol Parameter Rating Units 6 V VCC Power supply(Note 1) TA Operating ambient -40 to +85 °C Storage temperature -65 to +150 °C TSTG 2007 Preliminary Datasheet www.uxfastic.com 2 UX 2103 TTL output Limiting Amplifier Recommended Operating Conditions Symbol Parameter Rating Units VCC Power supply(Note 1) 3.0 to 5.5 V TA Operating ambient -40 to +85 °C Note 1: Related to Ground DC Characteristics Symbol Parameter VOS Equivalent input Offset Voltage VTH LOS Sensitivity Range VOH High output VOL Low output HYS LOS Hysteresis (Note 2) ICC Min Typ 2 Max Units 50 mV 20 mVP-P VCC GND 1 2 Power-Supply Current (Note 3) V 0.5 V 4 dB 25.3 mA Note 2: Optical, 10log (VDEASSERT/VASSERT). Note 3: LOSN is at CMOS level, no load terminated to the outputs, with I/O current in the output buffer. AC Characteristics (VCC=+3.0V to +5.5V, Typical values are at VCC = +5V, TA = +25°C, unless otherwise noted.) Symbol Parameter VIN Input signal voltage RIN Input Resistance CIN Input Capacitance Min Single ended Differential Typ Max 0.5 800 1 1600 20 TR, TF Data Output Transition Time (Note 5) TPWD Pulse-Width Distortion(Note 6) TLOS LOS Assert/Deassert Time 780 Units mV KΩ 2 pF 1900 ps 150 ps 100 μs Note 4: Single ended; the output buffer is CMOS structure, shown in Figure3. Note 5: 20% to 80% Note 6: TPWD= [(width of wider pulse)-(width of narrower pulse)]/2. 2007 Preliminary Datasheet www.uxfastic.com 3 UX 2103 TTL output Limiting Amplifier Applications Information TTL output CMOS structure.,but it operates TTL level,usually teminated by a pull up resistor (4.7～10KΩ), see Figure3. Figure 3. TTL Termination Circuit at OUT LOS Output Terminations In UX2103, the LOS interface operates three logic states with different termination techniques respectively. When LOSN is connected directly to external circuits, it operates CMOS level; When terminated by a pull up resistor (4.7～10KΩ), see Figure4, it compatible with TTL level; When terminated by 50Ω to (VCC-2V), see Figure5, it compatible with PECL level. The corresponding logic states list in table LOS Level Status. Figure 4. Equivalent TTL Termination Circuit Figure 5. Equivalent PECL Termination at LOSN Circuit at LOSN LOS level status Logic State CMOS PECL TTL High VCC VCC-0.9V VCC Low Ground VCC-2.2V Ground to 0.5V 2007 Preliminary Datasheet www.uxfastic.com 4 UX 2103 TTL output Limiting Amplifier Package Outline Details of ‘A’ part Figure 6. TSSOP16 Package 2007 Preliminary Datasheet www.uxfastic.com 5