SIMTEK STK17T88_08

STK17T88
32K x 8 AutoStore nvSRAM with Real-Time Clock
FEATURES
DESCRIPTION
• nvSRAM Combined With Integrated Real-Time
Clock Functions (RTC, Watchdog Timer, Clock
Alarm, Power Monitor)
The Simtek STK17T88 combines a 256Kb non-volatile static RAM (nvSRAM) with a full-featured realtime clock in a reliable, monolithic integrated circuit.
• Capacitor or Battery Backup for RTC
The 256Kbit nvSRAM is a fast static RAM with a
non-volatile Quantum Trap storage element
included with each memory cell.
• 25, 45 ns Read Access & R/W Cycle Time
• Unlimited Read/Write Endurance
• Automatic Non-volatile STORE on Power Loss
• Non-Volatile STORE Under Hardware or Software Control
• Automatic RECALL to SRAM on Power Up
• Unlimited RECALL Cycles
• 200K STORE Cycles
The SRAM provides the fast access & cycle times,
ease of use and unlimited read & write endurance of
a normal SRAM. Data transfers automatically to the
non-volatile storage cells when power loss is
detected (the STORE operation). On power up, data
is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations
are also available under software control.
The real time clock function provides an accurate
clock with leap year tracking and a programmable,
high accuracy oscillator. The Alarm function is programmable for one-time alarms or periodic minutes,
hours, or days alarms. There is also a programmable watchdog timer for processor control.
• 20-Year Non-volatile Data Retention
• Single 3 V +20%, -10% Power Supply
• Commercial and Industrial Temperatures
• 48-pin 300-mil SSOP Package (RoHSCompliant)
BLOCK DIAGRAM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
STORE
STATIC RAM
ARRAY
512 X 512
RECALL
VCC
VCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
VRTCbat
VRTCcap
HSB
SOFTWARE
DETECT
INPUT BUFFERS
A5
A6
A7
A8
A9
A11
A12
A13
A14
ROW DECODER
Quantum Trap
512 X 512
A13 – A0
COLUMN I/O
COLUMN DEC
RTC
X1
X2
INT
A 0 A 1 A 2 A 3 A 4 A10
MUX
A14 – A0
G
E
W
This product conforms to specifications per the
terms of Simtek standard warranty. The product
has completed Simtek internal qualification testing
and has reached production status.
1
Document Control #ML0024 Rev 2.0
Jan, 2008
STK17T88
VCAP
1
48
NC
A14
2
47
VCC
NC
3
46
HSB
A12
A7
4
5
45
44
A6
A5
6
43
W
A13
A6
7
42
A9
INT
8
41
NC
A4
9
40
A11
NC
10
39
NC
NC
11
38
NC
NC
VSS
12
37
NC
13
36
NC
14
35
VRTCbat
15
34
VSS
NC
VRTCcap
DQ0
16
33
DQ6
A3
A2
17
32
G
18
31
A10
A1
19
30
E
20
29
21
28
DQ7
DQ5
22
23
27
X1
26
DQ4
DQ3
X2
24
25
VCC
A0
DQ1
DQ2
(TOP)
SSOP
Pin Configurations
For detailed package size
specifications, see page 27.
48 Pin SSOP
PIN DESCRIPTIONS
Pin Name
I/O
Description
A14-A0
Input
Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array or one of 16 bytes in the clock
register map
DQ7-DQ0
I/O
Data: Bi-directional 8-bit data bus for accessing the nvSRAM and RTC
E
Input
Chip Enable: The active low E input selects the device
W
Input
Write Enable: The active low W enables data on the DQ pins to be written to the address location selected on
the falling edge of E
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high
caused the DQ pins to tri-state.
X1
Output
Crystal Connection, drives crystal on startup
X2
Input
Crystal Connection for 32.768 kHz crystal
VRTCcap
Power Supply
Capacitor supplied backup RTC supply voltage (Left unconnected if VRTCbat is used)
VRTCbat
Power Supply
Battery supplied backup RTC supply voltage (Left unconnected if VRTCcap is used)
VCC
Power Supply
Power: 3.0V, +20%, -10%
HSB
I/O
Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low external to the
chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if not connected.
(Connection Optional).
INT
Output
Interrupt Control: Can be programmed to respond to the clock alarm, the watchdog timer and the power monitor.
Programmable to either active high (push/pull) or active low (open-drain)
VCAP
Power Supply
AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile storage elements.
VSS
Power Supply
Ground
(Blank)
No Connect
Unlabeled pins have no internal connections.
Document Control #ML0024 Rev 2.0
Jan, 2008
2
STK17T88
ABSOLUTE MAXIMUM RATINGSa
Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 4.1V
Voltage on Input Relative to VSS . . . . . . . . . . –0.5V to (VCC + 0.5V)
Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . –55°C to 140°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RF (SSOP-48) PACKAGE THERMAL CHARACTERISTICS
θjc 6.2 C/W; θja 51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm].
(VCC = 2.7V-3.6V)
DC CHARACTERISTICS
COMMERCIAL
SYMBOL
MIN
ICC1
INDUSTRIAL
PARAMETER
MAX
MIN
UNITS
NOTES
tAVAV = 25ns
tAVAV = 45ns
Dependent on output loading and cycle
rate. Values obtained without output
loads.
MAX
Average VCC Current
ICC2
Average VCC Current during STORE
ICC3
Average VCC Current at tAVAV = 200ns
3V, 25°C, Typical
65
50
70
55
mA
mA
3
3
mA
All Inputs Don’t Care, VCC = max
Average current for duration of STORE
cycle (tSTORE)
10
10
mA
W ≥ (V CC – 0.2V)
All Other Inputs Cycling at CMOS Levels
Dependent on output loading and cycle
rate. Values obtained without output
loads.
All Inputs Don’t Care
Average current for duration of STORE
cycle (tSTORE)
ICC4
Average VCAP Current during AutoStore
Cycle
3
3
mA
ISB
VCC Standby Current
(Standby, Stable CMOS Levels)
3
3
mA
±1
±1
μA
VCC = max
VIN = VSS to VCC
±1
±1
μA
VCC = max
VIN = VSS to VCC, E or G ≥ VIH
E ≥ (VCC -0.2V)
All Others VIN≤ 0.2V or ≥ (VCC-0.2V)
Standby current level after nonvolatile
cycle complete
IILK
Input Leakage Current
IOLK
Off-State Output Leakage Current
VIH
Input Logic “1” Voltage
2.0
VCC + 0.5
2.0
VCC + 0.5
V
All Inputs
VIL
Input Logic “0” Voltage
VSS –0.5
0.8
VSS –0.5
0.8
V
All Inputs
VOH
Output Logic “1” Voltage
VOL
Output Logic “0” Voltage
TA
Operating Temperature
0
70
VCC
Operating Voltage
2.7
3.6
VCAP
Storage Capacitance
17
57
NVC
Nonvolatile STORE operations
200
200
K
DATAR
Data Retention
20
20
Years
2.4
2.4
V
IOUT = – 2mA
0.4
V
IOUT = 4mA
– 40
85
°C
2.7
3.6
V
3.0V +20%, -10%
17
57
μF
Between VCAP pin and VSS, 5V rated.
0.4
@ 55 deg C
Note: The HSB pin has IOUT=-10 µA for VOH of 2.4 V, this parameter is characterized but not tested.
Note: The INT pin is open-drain and does not source or sink high current when Interrupt Register bit D3 is low.
Document Control #ML0024 Rev 2.0
Jan, 2008
3
STK17T88
AC
TESTDIAGRAM
CONDITIONS
BLOCK
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 and 2
CAPACITANCEb (TA = 25°C, f = 1.0MHz)
SYMBOL
PARAMETER
MAX
UNITS
CONDITIONS
CIN
Input Capacitance
7
pF
ΔV = 0 to 3V
COUT
Output Capacitance
7
pF
ΔV = 0 to 3V
Note b: These parameters are guaranteed but not tested.
3.0V
3.0V
577 Ohms
577 Ohms
OUTPUT
OUTPUT
789 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
789 Ohms
Figure 1. AC Output Loading
Document Control #ML0024 Rev 2.0
Jan, 2008
5 pF
INCLUDING
SCOPE AND
FIXTURE
Figure 2. AC Output Loading for tristate specs
(THZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ)
4
STK17T88
RTC DC CHARACTERISTICS
Symbol
IBAK
VRTCbat
VRTCcap
tOSCS
Parameter
RTC Backup
Current
RTC Battery Pin
Voltage
RTC Capacitor
Pin Voltage
RTC Oscillator
time to start
Commercial
Min
Max
Industrial
Min
Max
Units
—
300
—
350
nA
1.8
3.3
1.8
3.3
V
1.2
2.7
1.2
2.7
V
—
10
—
10
sec
—
5
—
5
sec
Notes
From either VRTCcap or
VRTCbat
Typical = 3.0 Volts during
normal operation
Typical = 2.4 Volts during
normal operation
@ MIN Temperature from
Power up or Enable
@ 25°C from Power up or
Enable
Y1
C2
RF
C1
RTC RECOMMENDED COMPONENT CONFIGURATION
X1
X2
Recommended Values
Y1 = 32.768 KHz
RF = 10M Ohm
C1 = 0 (install cap footprint,
but leave unloaded)
C2 = 56 pF ± 10% (do not vary from this value)
Figure 3. RTC COMPONENT CONFIGURATION
Document Control #ML0024 Rev 2.0
Jan, 2008
5
STK17T88
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1
#2
1
PARAMETER
Alt.
STK17T88-25
STK17T88-45
MIN
MIN
MAX
tELQV
tACS
Chip Enable Access Time
2
tAVAVc
tELEHe
tRC
Read Cycle Time
3
tAVQVd
tAVQVf
tAA
Address Access Time
25
45
ns
tGLQV
tOE
Output Enable to Data Valid
12
20
ns
tAXQX
tOH
Output Hold after Address Change
3
3
tELQX
tLZ
Address Change or Chip Enable to
Output Active
3
3
4
5
tAXQXd
6
7
tEHQZ
tHZ
25
UNITS
MAX
45
25
Address Change or Chip Disable to
Output Inactive
8
tGLQX
tOLZ
Output Enable to Output Active
9
tGHQZe
tOHZ
Output Disable to Output Inactive
10
tELICCLc
tPA
Chip Enable to Power Active
11
tEHICCHc
tPS
Chip Disable to Power Standby
ns
45
10
ns
ns
ns
ns
15
0
0
10
ns
15
0
ns
0
25
ns
45
ns
Note c: W must be high during SRAM READ cycles.
Note d: Device is continuously selected with E and G both low
Note e: Measured ± 200mV from steady state output voltage.
Note f: HSB must remain high during READ and WRITE cycles.
SRAM READ CYCLE #1: Address Controlledc,d,f
2
t AVAV
ADDRESS
3
t AVQV
5
t AXQX
DQ (DATA OUT)
DATA VALID
SRAM READ CYCLE #2: E and G Controlleda,f
ADDR ESS
2
E
27
t E LE H
1
tEL Q V
6
29
t EHAX
11
t EHI CC L
t ELQ X
7
t EHQ Z
3
t AV QV
G
8
tG L Q X
9
t GH Q Z
4
t G L QV
DQ (D ATA OUT)
DAT A VAL ID
10
t ELI CC H
AC T IVE
I CC
ST AND BY
Document Control #ML0024 Rev 2.0
Jan, 2008
6
STK17T88
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
STK17T88-25
STK17T88-45
MIN
MIN
PARAMETER
UNITS
#1
#2
Alt.
MAX
MAX
12
tAVAV
tAVAV
tWC
Write Cycle Time
25
45
ns
13
tWLWH
tWLEH
tWP
Write Pulse Width
20
30
ns
14
tELWH
tELEH
tCW
Chip Enable to End of Write
20
30
ns
15
tDVWH
tDVEH
tDW
Data Set-up to End of Write
10
15
ns
16
tWHDX
tEHDX
tDH
Data Hold after End of Write
0
0
ns
17
tAVWH
tAVEH
tAW
Address Set-up to End of Write
20
30
ns
18
tAVWL
tAVEL
tAS
Address Set-up to Start of Write
0
0
ns
19
tWHAX
tEHAX
tWR
Address Hold after End of Write
0
0
ns
20
t WLQZ ,
tWZ
Write Enable to Output Disable
21
tWHQX
tOW
Output Active after End of Write
10
3
15
ns
3
ns
note g: If W is low when E goes low, the outputs remain in the high-impedance state.
note h: E or W must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledg,h
12
tAVAV
ADDRESS
19
tWHAX
14
tELWH
E
17
tAVWH
18
tAVWL
13
tWLWH
W
15
16
tDVWH
DATA IN
tWHDX
DATA VALID
20
tWLQZ
DATA OUT
21
tWHQX
HIGH IMPEDANCE
PREVIOUS DATA
SRAM WRITE CYCLE #2: E Controlledg,h
12
tAVAV
ADDRESS
18
14
tAVEL
19
tELEH
tEHAX
E
17
tAVEH
13
W
tWLEH
15
16
tDVEH
DATA IN
DATA OUT
Document Control #ML0024 Rev 2.0
Jan, 2008
tEHDX
DATA VALID
HIGH IMPEDANCE
7
STK17T88
AutoStore™/POWER-UP RECALL
SYMBOLS
STK17T88
NO.
PARAMETER
Standard
Alternate
MIN
UNITS
NOTES
40
ms
i
j,k
MAX
22
tHRECALL
23
tSTORE
STORE Cycle Duration
12.5
ms
24
VSWITCH
Low Voltage Trigger Level
2.65
V
25
VCCRISE
VCC Rise Time
note i:
note j:
note k:
Power-up RECALL Duration
tHLHZ
μS
150
tHRECALL starts from the time VCC rises above VSWITCH
If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place
Industrial Grade Devices require 15 ms MAX.
AutoStore™/POWER-UP RECALL
STORE occurs only if a
SRAM write has
happened.
No STORE occurs
without at least one
SRAM write.
VCC
24
VSWITCH
25
tVCCRISE
AutoStoreTM
23
tSTORE
23
tSTORE
POWER-UP RECALL
22
tHRECALL
22
tHRECALL
Read & Write Inhibited
POWER-UP
RECALL
BROWN OUT
TM
AutoStore
POWER-UP
RECALL
POWER DOWN
TM
AutoStore
Note: Read and Write cycles will be ignored during STORE, RECALL and while VCC is below VSWITCH
Document Control #ML0024 Rev 2.0
Jan, 2008
8
STK17T88
SOFTWARE-CONTROLLED STORE/RECALL CYCLEl,m
SYMBOLS
STK17T88-35
NO.
STK17T88-45
PARAMETER
UNITS NOTES
E Cont
Alternate
26
tAVAV
tRC
STORE / RECALL Initiation Cycle Time
25
45
ns
27
tAVEL
tAS
Address Set-up Time
0
0
ns
28
tELEH
tCW
Clock Pulse Width
20
30
ns
29
tEHAX
Address Hold Time
1
1
ns
30
tRECALL
RECALL Duration
MIN
MAX
MIN
100
MAX
100
m
μs
note l: The software sequence is clocked on the falling edge of E controlled READs
note m: The six consecutive addresses must be read in the order listed in the Software STORE/RECALL Mode Selection Table. W must be high
during all six consecutive cycles.
SOFTWARE STORE/RECALL CYCLE: E CONTROLLEDm
ADDRESS
E
27
tAVEL
26
tAVAV
26
tAVAV
ADDRESS #1
ADDRESS #6
28
tELEH
29
tEHAX
G
23
tSTORE
DQ (DATA)
DATA VALID
DATA VALID
Document Control #ML0024 Rev 2.0
Jan, 2008
9
/t
30
RECALL
HIGH IMPEDENCE
STK17T88
HARDWARE STORE CYCLE
SYMBOLS
STK17T88
PARAMETER
Standard
Alternate
31
tDELAY
tHLQZ
32
tHLHX
MIN
MAX
Hardware STORE to SRAM Disabled
1
70
Hardware STORE Pulse Width
15
UNITS
NOTES
μs
n
ns
Note n: On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read/write cycles to complete
HARDWARE STORE CYCLE
32
tHLHX
HSB (IN)
23
tSTORE
HSB (OUT)
31
tDELAY
DQ (DATA OUT)
SRAM Enabled
SRAM Enabled
Soft Sequence Commands
NO.
SYMBOLS
PARAMETER
STK17T88
Standard
33
MIN
tSS
NOTES
μs
o,p
MAX
70
Soft Sequence Processing Time
UNITS
note o: This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register
command.
note p: Commands like Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.
Soft Sequence Command
ADDRESS
ADDRESS #1
33
tSS
33
tSS
Soft Sequence Command
ADDRESS #1
ADDRESS #6
Vcc
Document Control #ML0024 Rev 2.0
Jan, 2008
10
ADDRESS #6
STK17T88
MODE SELECTION
E
W
G
A14-A0
Mode
I/O
Power
H
X
X
X
Not Selected
Output High Z
Standby
L
H
L
X
Read SRAM
Output Data
Active
L
L
X
X
Write SRAM
Input Data
Active
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Active
0x0FC0
Nonvolatile Store
Output High Z
ICC2
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
L
L
H
H
L
Notes
q,r,s
q,r,s
note q: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile
cycle.
note r: While there are 15 addresses on the STK17T88, only the lower 13 are used to control software modes
note s: I/O state depends on the state of G. The I/O table shown assumes G low
Document Control #ML0024 Rev 2.0
Jan, 2008
11
STK17T88
nvSRAM OPERATION
nvSRAM
SRAM WRITE
The STK17T88 nvSRAM is made up of two functional components paired in the same physical cell.
These are the SRAM memory cell and a nonvolatile
QuantumTrap cell. The SRAM memory cell operates
like a standard fast static RAM. Data in the SRAM
can be transferred to the nonvolatile cell (the
STORE operation), or from the nonvolatile cell to
SRAM (the RECALL operation). This unique architecture allows all cells to be stored and recalled in
parallel. During the STORE and RECALL operations
SRAM READ and WRITE operations are inhibited.
The STK17T88 supports unlimited read and writes
like a typical SRAM. In addition, it provides unlimited
RECALL operations from the nonvolatile cells and
up to 200K STORE operations.
A WRITE cycle is performed whenever E and W are
low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ0-7 will be written into memory if it is valid tDVWH
before the end of a W controlled WRITE or tDVEH
before the end of an E controlled WRITE.
SRAM READ
The STK17T88 stores data to nvSRAM using one of
three storage operations. These three operations
are Hardware Store (activated by HSB), Software
Store (activated by an address sequence), and
AutoStore (on power down).
The STK17T88 performs a READ cycle whenever E
and G are low while W and HSB are high. The
address specified on pins A0-14 determine which of
the 32,768 data bytes will be accessed. When the
READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle
#1). If the READ is initiated by E and G, the outputs
will be valid at tELQV or at tGLQV, whichever is later
(READ cycle #2). The data outputs will repeatedly
respond to address changes within the tAVQV access
time without the need for transitions on any control
input pins, and will remain valid until another
address change or until E or G is brought high, or W
and HSB is brought low.
W
AutoStore operation, a unique feature of Simtek
QuanumTrap technology that is a standard feature
on the STK17T88.
During normal operation, the device will draw current from VCC to charge a capacitor connected to
the VCAP pin. This stored charge will be used by the
chip to perform a single STORE operation. If the
voltage on the VCC pin drops below VSWITCH, the
part will automatically disconnect the VCAP pin from
VCC. A STORE operation will be initiated with power
provided by the VCAP capacitor.
To reduce unneeded nonvolatile stores, AutoStore
and Hardware Store operations will be ignored
unless at least one WRITE operation has taken
place since the most recent STORE or RECALL
cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation
Figure 4: AutoStore Mode
Document Control #ML0024 Rev 2.0
Jan, 2008
AutoStore OPERATION
Figure 5 shows the proper connection of the storage
capacitor (VCAP) for automatic store operation.
Refer to the DC CHARACTERISTICS table for the
size of the capacitor. The voltage on the VCAP pin is
driven to 5V by a charge pump internal to the chip. A
pull up should be placed on W to hold it inactive during power up.
0.1µF
VCC
VCAP
VCAP
10k Ohm
VCC
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes
low.
12
STK17T88
has taken place. The HSB signal can be monitored
by the system to detect an AutoStore cycle is in
progress.
HARDWARE STORE (HSB) OPERATION
The STK17T88 provides the HSB pin for controlling
and acknowledging the STORE operations. The HSB
pin can be used to request a hardware STORE
cycle. When the HSB pin is driven low, the
STK17T88 will conditionally initiate a STORE operation after tDELAY. An actual STORE cycle will only
begin if a WRITE to the SRAM took place since the
last STORE or RECALL cycle. The HSB pin has a
very resistive pullup and is internally driven low to
indicate a busy condition while the STORE (initiated
by any means) is in progress. This pin should be
externally pulled up if it is used to drive other inputs.
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK17T88 will
continue to allow SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may
take place. If a WRITE is in progress when HSB is
pulled low, it will be allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles
requested after HSB goes low will be inhibited until
HSB returns high.
During any STORE operation, regardless of how it
was initiated, the STK17T88 will continue to drive
the HSB pin low, releasing it only when the STORE is
complete. Upon completion of the STORE operation, the STK17T88 will remain disabled until the
HSB pin returns high.
If HSB is not used, it should be left unconnected.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1 Read A ddress 0x0E38 V alid REA D
2 Read A ddress 0x31C7 V alid REA D
3 Read A ddress 0x03E0 V alid REA D
4 Read A ddress 0x3C1F V alid REA D
5 Read A ddress 0x303F V alid REA D
6 Read A ddress 0x0FC0 Initiate STORE Cycle
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ
cycles and not WRITE cycles be used in the
sequence. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ
and WRITE operation.
SOFTWARE RECALL
Data can be transferred from the nonvolatile memory to the SRAM by a software address sequence. A
software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL
cycle, the following sequence of E controlled READ
operations must be performed:
1 Read A ddress 0x0E38 V alid REA D
2 Read A ddress 0x31C7 V alid REA D
3 Read A ddress 0x03E0 V alid REA D
4 Read A ddress 0x3C1F V alid REA D
HARDWARE RECALL (POWER-UP)
During power up or after any low-power condition
(VCC<VSWITCH), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tHRECALL to complete.
SOFTWARE STORE
Data can be transferred from the SRAM to the nonvolatile memory by a software address sequence.
The STK17T88 software STORE cycle is initiated by
executing sequential E controlled READ cycles from
Document Control #ML0024 Rev 2.0
Jan, 2008
six specific address locations in exact order. During
the STORE cycle, previous data is erased and then
the new data is programmed into the nonvolatile elements. Once a STORE cycle is initiated, further
memory inputs and outputs are disabled until the
cycle is completed.
13
5 Read A ddress 0x303F V alid REA D
6 Read A ddress 0x0C63 Initiate RECA LL Cycle
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells.
After the tRECALL cycle time, the SRAM will once
again be ready for READ or WRITE operations. The
RECALL operation in no way alters the data in the
nonvolatile storage elements.
STK17T88
DATA PROTECTION
The STK17T88 protects data from corruption during
low-voltage conditions by inhibiting all externally
initiated STORE and WRITE operations. The lowvoltage condition is detected when VCC<VSWITCH.
If the STK17T88 is in a WRITE mode (both E and W
low) at power-up, after a RECALL, or after a
STORE, the WRITE will be inhibited until a negative
transition on E or W is detected. This protects
against inadvertent writes during power up or brown
out conditions.
NOISE CONSIDERATIONS
The STK17T88 is a high-speed memory and so
must have a high-frequency bypass capacitor of 0.1
µF connected between both VCC pins and VSS
ground plane with no plane break to chip VSS. Use
leads and traces that are as short as possible. As
with all high-speed CMOS ICs, careful routing of
power, ground, and signals will reduce circuit noise..
PREVENTING AutoStore
Because of the use of nvSRAM to store critical RTC
data, the AutoStore function can not be disabled on
the STK17T88.
BEST PRACTICES
nvSRAM products have been used effectively for
over 15 years. While ease-of-use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the
following suggestions as best practices:
• The non-volatile cells in an nvSRAM are programmed on the test floor during final test and
quality assurance. Incoming inspection routines
at customer or contract manufacturer’s sites will
sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55,
00, FF, A5, or 5A. End product’s firmware should
not assume an NV array is in a set programmed
state. Routines that check memory content values to determine first time system configuration,
cold or warm boot status, etc. should always program a unique NV pattern (e.g., complex 4-byte
pattern of 46 E6 49 53 hex or more random
bytes) as part of the final system manufacturing
Document Control #ML0024 Rev 2.0
Jan, 2008
14
test to ensure these system routines work consistently.
• Power up boot firmware routines should rewrite
the nvSRAM into the desired state (autostore
enabled, etc.). While the nvSRAM is shipped in a
preset state, best practice is to again rewrite the
nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently
(program bugs, incoming inspection routines,
etc.).
• The OSCEN bit in the Calibration register at
0x7FF8 should be set to 1 to preserve battery life
when the system is in storage (see STOPPING
AND STARTING THE RTC OSCILLATOR on
page 16).
• The Vcap value specified in this datasheet
includes a minimum and a maximum value size.
Best practice is to meet this requirement and not
exceed the max Vcap value because the nvSRAM
internal algorithm calculates Vcap charge time
based on this max Vcap value. Customers that
want to use a larger Vcap value to make sure
there is extra store charge and store time should
discuss their Vcap size selection with Simtek to
understand any impact on the Vcap voltage level
at the end of a tRECALL period.
STK17T88
LOW AVERAGE ACTIVE POWER
CMOS technology provides the STK17T88 with the
benefit of power supply current that scales with
cycle time. Less current will be drawn as the memory cycle time becomes longer than 50 ns. Figure 5
shows the relationship between ICC and READ/
WRITE cycle time. Worst-case current consumption
is shown for commercial temperature range,
VCC=3.6V, and chip enable at maximum frequency.
Only standby current is drawn when the chip is disabled. The overall average current drawn by the
STK17T88 depends on the following items:
1.
2.
3.
4.
5.
6.
The duty cycle of chip enable.
The overall cycle rate for accesses.
The ratio of READs to WRITEs.
The operating temperature.
The VCC level.
I/O loading.
Figure 5. Current vs. Cycle Time
Document Control #ML0024 Rev 2.0
Jan, 2008
15
STK17T88
REAL TIME CLOCK OPERATION
REAL TIME CLOCK
The clock registers maintain time up to 9,999 years
in one-second increments. The user can set the time
to any calendar time and the clock automatically
keeps track of days of the week and month, leap
years, and century transitions. There are eight registers dedicated to the clock functions which are used
to set time with a write cycle and to read time during
a read cycle. These registers contain the Time of
Day in BCD format. Bits defined as “0” are currently
not used and are reserved for future use by Simtek.
READING THE CLOCK
The user should halt internal updates to the real time
clock registers before reading clock data to prevent
reading of data in transition. Stopping the internal
register updates does not affect clock accuracy.
Write a “1” to the read bit “R” (in the Flags register at
0x7FF0) to capture the current time in holding registers. Clock updates do not restart until a “0” is written
to the read bit. The RTC registers can now be read
while the internal clock continues to run.
Within 20ms after a “0” is written to the read bit, all
real time clock registers are simultaneously updated.
SETTING THE CLOCK
Set the write bit “W” (in the Flags register at 0x7FF0)
to a “1” enable the time to be set. The correct day,
date and time can then be written into the real time
clock registers in 24-hour BCD format. The time written is referred to as the “Base Time.” This value is
stored in non-volatile registers and used in calculation of the current time. Reset the write bit to “0” to
transfer the time to the actual clock counters, The
clock will start counting at the new base time.
BACKUP POWER
The RTC is intended to keep time even when system
power is lost. When primary power, VCC, drops
below VSWITCH, the real time clock will switch to the
backup power supply connected to either the VRTCcap or VRTCbat pin.
Document Control #ML0024 Rev 2.0
Jan, 2008
16
The clock oscillator uses a maximum of 300 nanoamps at 2 volts to maximize the backup time available from the backup source.
You can power the real time clock with either a
capacitor or a battery. Factors to be considered
when choosing a backup power source include the
expected duration of power outages and the cost
and reliability trade-off of using a battery versus a
capacitor.
If you select a capacitor power source, connect the
capacitor to the VRTCcap pin and leave the VRTCbat
pin unconnected. Capacitor backup time values
based on maximum current specs are shown below.
Nominal times are approximately 3 times longer.
Capacitor Value
Backup Time
0.1 F
72 hours
0.47 F
14 days
1.0 F
30 days
A capacitor has the obvious advantage of being
more reliable and not containing hazardous materials. The capacitor is recharged every time the power
is turned on so that the real time clock continues to
have the same backup time over years of operation
If you select a battery power source, connect the battery to the VRTCbat pin and leave the VRTCcap pin
unconnected. A 3V lithium is recommended for this
application. The battery capacity should be chosen
for the total anticipated cumulative down-time
required over the life of the system.
The real time clock is designed with a diode internally connected to the VRTCbat pin. This prevents the
battery from ever being charged by the circuit.
STOPPING AND STARTING THE
RTC OSCILLATOR
The OSCEN bit in Calibration register at 0x7FF8
enables RTC oscillator operation. This bit is non-volatile and shipped to customers in the “enabled” state
(set to 0). OSCEN should be set to a 1 to preserve
battery life while the system is in storage. This will
turn off the oscillator circuit extending the battery life.
If the OSCEN bit goes from disabled to enabled, it
will typically take 5 seconds (10 seconds max) for
the oscillator to start.
STK17T88
The STK17T88 has the ability to detect oscillator
failure due to loss of backup power. The failure is
recorded by the OSCF (Oscillator Failed bit) of the
Flags register (at address 0x7FF0). When the
device is powered on (VCC goes above VSWITCH)
the OSCEN bit is checked for “enabled” status. If the
OSCEN bit is enabled and the oscillator is not active
within 5 ms, the OSCF bit is set. The user should
check for this condition and then write a 0 to clear
the flag. When the OSCF flag bit, the real time clock
registers are reset to the “Base Time” (see the section SETTING THE CLOCK on page 16), the value
last written to the real time clock registers.
binary 6 is loaded, the first 12 will be affected, and
so on. Therefore each calibration step has the effect
of adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles. That is
+4.068 or -2.034 ppm of adjustment per calibration
step in the Calibration register.
The value of OSCF should be reset to 0 when the
real time clock registers are written for the first time.
This will initialize the state of this bit since it may
have become set when the system was first powered on.
The calibration register value is determined during
system test by setting the CAL bit in the Flags register (at 0x7FF0) to 1. This causes the INT pin to toggle at a nominal 512 Hz. This frequency can be
measured with a frequency counter. Any deviation
measured from the 512 Hz will indicate the degree
and direction of the required correction. For example, a reading of 512.01024 Hz would indicate a +20
ppm error, requiring a -10 (001010) to be loaded into
the Calibration register. Note that setting or changing the calibration register does not affect the frequency test output frequency.
To reset OSCF, set the write bit “W” (in the Flags
register at 0x7FF0) to a “1” to enable writes to the
Flags register. Write a “0” to the OSCF bit and then
reset the write bit to “0” to disable writes.
To set or clear CAL, set the write bit “W” (in the Flags
register at 0x7FF0) to a “1” to enable writes to the
Flags register. Write a value to CAL and then reset
the write bit to “0” to disable writes.
CALIBRATING THE CLOCK
The RTC is driven by a quartz controlled oscillator
with a nominal frequency of 32.768 KHz. Clock
accuracy will depend on the quality of the crystal
specified (usually 35 ppm at 25 C). This error could
equate to 1.53 minutes gain or loss per month. The
STK17T88 employs a calibration circuit that can
improve the accuracy to +1/-2 ppm at 25 C. The calibration circuit adds or subtracts counts from the
oscillator divider circuit.
The number of time pulses added or subtracted
depends upon the value loaded into the five calibration bits found in Calibration register (at 0x7FF8).
Adding counts speeds the clock up; subtracting
counts slows the clock down. The Calibration bits
occupy the five lower order bits of the register.
These bits can be set to represent any value
between 0 and 31 in binary form. Bit D5 is a Sign bit,
where a “1” indicates positive calibration and a “0”
indicates negative calibration. Calibration occurs
during a 64 minute period. The first 62 minutes in the
cycle may, once per minute, have one second either
shortened by 128 or lengthened by 256 oscillator
cycles.
If a binary “1” is loaded into the register, only the first
2 minutes of the 64 minute cycle will be modified; if a
Document Control #ML0024 Rev 2.0
Jan, 2008
17
The default Calibration register value from the factory is 00h. The user calibration value loaded is
retained during a power loss.
ALARM
The alarm function compares a user-programmed
alarm time/date (stored in registers 0x7FF1-5) with
the real time clock time-of-day/date values. When a
match occurs, the alarm flag (AF) is set and an interrupt is generated if the alarm interrupt is enabled.
The alarm flag is automatically reset when the Flags
register is read.
Each of the alarm registers has a match bit as its
MSB. Setting the match bit to a 1 disables this alarm
register from the alarm comparison. When the
match bit is 0, the alarm register is compared with
the equivalent real time clock register. Using the
match bits, an alarm can occur as specifically as one
particular second on one day of the month or as frequently as once per minute.
Note: The product requires the match bit for seconds (0x7FF2, bit D7) be set to 0 for proper operation of the Alarm Flag and Interrupt.
The alarm value should be initialized on power-up by
software since the alarm registers are not nonvolatile.
STK17T88
To set or clear the Alarm registers, set the write bit
“W” (in the Flags register at 0x7FF0) to a “1” to
enable writes to the Alarm registers. Write an alarmvalue to the alarm registers and then reset the write
bit to “0” to disable writes.
WATCHDOG TIMER
The watchdog timer is designed to interrupt or reset
the processor should its program get hung in a loop
and not respond in a timely manner. The software
must reload the watchdog timer before it counts
down to zero to prevent this interrupt or reset.
The watchdog timer is a free-running-down counter
that uses the 32Hz clock (31.25 ms) derived from
the crystal oscillator. The watchdog timer function
does not operate unless the oscillator is running.
The watchdog counter is loaded with a starting value
from the load register and then counts down to zero,
setting the watchdog flag (WDF) and generating an
interrupt if the watchdog interrupt is enabled. The
watchdog flag bit is reset when the Flags register is
read. The operating software would normally reload
the counter by setting the watchdog strobe bit
(WDS) to 1 within the timing interval programmed
into the load register.
To use the watchdog timer to reset the processor on
timeout, the INT is tied to processor master reset
and Interrupt register is programmed to 24h to
enable interrupts to pulse the reset pin on timeout.
To load the watchdog timer, set a new value into the
load register by writing a “0” to the watchdog write bit
(WDW) of the watchdog register (at 0x7FF7). Then
load a new value into the load register. Once the
new value is loaded, the watchdog write bit is then
set to 1 to disable watchdog writes. The watchdog
strobe bit (WDS) is set to 1 to load this value into the
watchdog timer. Note: Setting the load register to
zero will disable the watchdog timer function.
The system software should initialize the watchdog
load register on power-up to the desired value since
the register is not non-volatile.
POWER MONITOR
When operating from the backup source, no data
may be read or written and the clock functions are
not available to the user. The clock continues to
operate in the background. Updated clock data is
available to the user tHRECALL delay after VCC has
been restored to the device.
When the power is lost, the PF flag in the Flags register is set to indicate the power failure and an interrupt is generated if the power fail interrupt is enabled
(interrupt register=20h). The INT line would normally
be tied to the processor master reset input to perform power-off reset.
INTERRUPTS
The STK17T88 has a Flags register, Interrupt register, and interrupt logic that can interrupt the microcontroller or general a power-up master reset signal.
There are three potential interrupt sources: the
watchdog timer, the power monitor, and the clock
alarm. Each can be individually enabled to drive the
INT pin by setting the appropriate bit in the Interrupt
register. In addition, each has an associated flag bit
in the Flags register that the host processor can
read to determine the interrupt source. Two bits in
the interrupt register determine the operation of the
INT pin driver.
A functional diagram of the interrupt logic is shown
below.
WDF
Watchdog
Timer
Power
Monitor
WIE
PF
P/L
PFE
Pin
Driver
H/L
VINT
AF
Clock
Alarm
AIE
Figure 6. Interrupt Block Diagram
The STK17T88 provides a power monitor function.
The power monitor is based on an internal band-gap
reference circuit that compares the VCC voltage to
VSWITCH.
Document Control #ML0024 Rev 2.0
Jan, 2008
When the power supply drops below VSWITCH, the
real time clock circuit is switched to the backup supply (battery or capacitor).
18
VCC
INT
VSS
STK17T88
INTERRUPT REGISTER
Watchdog Interrupt Enable (WIE). When set to 1,
the watchdog timer drives the INT pin when a watchdog time-out occurs. When WIE is set to 0, the
watchdog time-out only sets the WDF flag bit.
Alarm Interrupt Enable (AIE). When set to 1, the INT
pin is driven when an alarm match occurs. When set
to 0, the alarm match only sets the AF flag bit.
Power Fail Interrupt Enable (PFE). When set to 1,
the INT pin is driven by a power fail signal from the
power monitor. When set to 0, only the PF flag is set.
High/Low (H/L). When set to a 1, the INT pin is
active high and the driver mode is push-pull. The
INT pin can drive high only when VCC>VSWITCH.
When set to a 0, the INT pin is active low and the
drive mode is open-drain. The active low (open
drain) output is maintained even when power is lost.
Pulse/Level (P/L). When set to a 1, the INT pin is
driven for approximately 200 ms when the interrupt
occurs. The pulse is reset when the Flags register is
read. When P/L is set to a 0, the INT pin is driven
high or low (determined by H/L) until the Flags register is read.
The Interrupt register is loaded with the default value
00h at the factory. The user should configure the
Interrupt register to the value desired for their
desired mode of operation. Once configured, the
value is retained during power failures.
FLAGS REGISTER
The Flags register has three flag bits: WDF, AF, and
PF. These flags are set by the watchdog time-out,
alarm match, or power fail monitor respectively. The
processor can either poll this register or enable the
interrupts to be informed when a flag is set. The
flags are automatically reset once the register is
read.
The Flags register is automatically loaded with the
value 00h on power up (with the exception of the
OSCF bit).
Document Control #ML0024 Rev 2.0
Jan, 2008
19
STK17T88
RTC REGISTER MAP
Register
0x7FFF
0x7FFE
0x7FFD
D7
D6
D5
10s Years
0
0
0
0
0
0
0
0
OSCEN
[0]
0x7FF7
WDS
WDW
WIE[0]
AIE[0]
M
0
M
0
0x7FF5
0x7FF4
0x7FF3
0x7FF2
0x7FF1
0x7FF0
D2
10s
Months
10s Day of
Month
0
0
0
0
10s Hours
10s Minutes
10s Seconds
Cal
0
Sign
0x7FFC
0x7FFB
0x7FFA
0x7FF9
0x7FF8
0x7FF6
0
BCD Format Data
D4
D3
D1
Years
Months: 01-12
Day of Month: 0131
Day of week: 01-07
Hours: 00-23
Minutes: 00-59
Seconds: 00-59
Day of Month
0
Day of Week
Hours
Minutes
Seconds
Calibration [00000]
Calibration values*
WDT
PFE
0
[0]
10s Alarm
Date
10s Alarm
Hours
H/L
[1]
Watchdog*
P/L [0]
0
Alarm Hours
Alarm, hours: 00-23
M
10 Alarm Seconds
Alarm Seconds
0
Interrupts*
Alarm, Day of
Month: 01-31
Alarm Minutes
OSCF
0
Alarm Day
10 Alarm Minutes
10s Centuries
AF
PF
Function / Range
Years: 00-99
Months
M
WDF
D0
Centuries
CAL[0] W[0]
R[0]
Alarm, minutes: 0059
Alarm, seconds:
00-59
Centuries: 00-99
Flags*
*A binary value, not a BCD value.
0 - Not implemented, reserved for future use.
Default Settings of non-volatile Calibration and Interrupt registers from factory
Calibration Register=00h
Interrupt Register=00h
The User should configure to the desired value at startup or during operation and the value is then
retained during a power failure.
[ ] designates values shipped from the factory. See STOPPING AND STARTING THE RTC OSCILLATOR on page 16.
Document Control #ML0024 Rev 2.0
Jan, 2008
20
STK17T88
Register Map Detail
0x7FFF
0x7FFE
0x7FFD
0x7FFC
0x7FFB
Real Time Clock – Years
D6
D5
D4
D3
D2
D1
D0
10s Years
Years
Contains the lower two BCD digits of the year. Lower nibble contains the value for
years; upper nibble contains the value for 10s of years. Each nibble operates from 0
to 9. The range for the register is 0-99.
D7
Real Time Clock – Months
D7
D6
D5
D4
D3
D2
D1
D0
10s
0
0
0
Months
Month
Contains the BCD digits of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to
1. The range for the register is 1-12.
Real Time Clock – Date
D7
D6
D5
D4
D3
D2
D1
D0
0
0
10s Day of month
Day of month
Contains the BCD digits for the date of the month. Lower nibble contains the lower digit
and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 3.
The range for the register is 1-31. Leap years are automatically adjusted for.
Real Time Clock – Day
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
Day of week
Lower nibble contains a value that correlates to day of the week. Day of the week is a
ring counter that counts from 1 to 7 then returns to 1. The user must assign meaning
to the day value, as the day is not integrated with the date.
Real Time Clock – Hours
D7
D6
D5
D4
D3
D2
D1
D0
0
0
10s Hours
Hours
Contains the BCD value of hours in 24 hour format. Lower nibble contains the lower
digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and
operates from 0 to 2. The range for the register is 0-23.
Document Control #ML0024 Rev 2.0
Jan, 2008
21
STK17T88
0x7FFA
0x7FF9
0x7FF8
OSCEN
Calibration
Sign
Calibration
0x7FF7
WDS
WDW
WDT
Real Time Clock – Minutes
D7
D6
D5
D4
D3
D2
D1
D0
0
10s Minutes
Minutes
Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper minutes digit and operates from 0 to
5. The range for the register is 0-59.
Real Time Clock – Seconds
D7
D6
D5
D4
D3
D2
D1
D0
0
10s Seconds
Seconds
Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 5. The
range for the register is 0-59.
D7
Calibration
D4
D3
D6
D5
D2
D1
D0
Calibrat
OSCEN
0
Calibration
ion Sign
Oscillator Enable. When set to 1, the oscillator is disabled. When set to 0, the oscillator
is enabled. Disabling the oscillator saves battery/capacitor power during storage.
Determines if the calibration adjustment is applied as an addition to or as a subtraction
from the time-base.
These five bits control the calibration of the clock.
Watchdog Timer
D7
D6
D5
D4
D3
D2
D1
D0
WDS
WDW
WDT
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. The bit
is cleared automatically once the watchdog timer is reset. The WDS bit is write only.
Reading it always will return a 0.
Watchdog Write Enable. Set this bit to 1 to disable writing of the watchdog time-out
value (WDT5-WDT0). This allows the user to strobe the watchdog without disturbing
the time-out value. Setting this bit to 0 allows bits 5-0 to be written.
Watchdog time-out selection. The watchdog timer interval is selected by the 6-bit value
in this register. It represents a multiplier of the 32 Hz count (31.25 ms). The range or
time-out values is 31.25 ms (a setting of 1) to 2 seconds (setting of 3Fh). Setting the
watchdog timer register to 0 disables the timer. These bits can be written only if the
WDW bit was cleared to 0 on a previous cycle.
Document Control #ML0024 Rev 2.0
Jan, 2008
22
STK17T88
0x7FF6
WIE
AIE
PFIE
0
H/L
P/L
0x7FF5
M
0x7FF4
M
Interrupt
D7
D6
D5
D4
D3
D2
D1
D0
WIE
AIE
PFIE
ABE
H/L
P/L
0
0
Watchdog Interrupt Enable. When set to 1 and a watchdog time-out occurs, the
watchdog timer drives the INT pin as well as setting the WDF flag. When set to 0, the
watchdog time-out only sets the WDF flag.
Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin as well as
setting the AF flag. When set to 0, the alarm match only sets the AF flag.
Power-Fail Enable. When set to 1, a power failure drives the INT pin as well as setting
the PF flag. When set to 0, a power failure only sets the PF flag.
Reserved for Future Use
High/Low. When set to a 1, the INT pin is driven active high. When set to 0, the INT pin
is open drain, active low.
Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L) by an
interrupt source for approximately 200 ms. When set to a 0, the INT pin is driven to an
active level (as set by H/L) until the Flags register is read.
Alarm – Day
D7
D6
D5
D4
D3
D2
D1
D0
M
0
10s Alarm Date
Alarm Date
Contains the alarm value for the date of the month and the mask bit to select or
deselect the date value.
Match. Setting this bit to 0 causes the date value to be used in the alarm match. Setting
this bit to 1 causes the match circuit to ignore the date value.
Alarm – Hours
D7
D6
D5
D4
D3
D2
D1
D0
M
0
10s Alarm Hours
Alarm Hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours
value.
Match. Setting this bit to 0 causes the hours value to be used in the alarm match.
Setting this bit to 1 causes the match circuit to ignore the hours value.
Document Control #ML0024 Rev 2.0
Jan, 2008
23
STK17T88
0x7FF3
M
0x7FF2
M
0x7FF1
Alarm – Minutes
D4
D3
D7
D6
D5
D2
D1
D0
M
10s Alarm Minutes
Alarm Minutes
Contains the alarm value for the minutes and the mask bit to select or deselect the
minutes value.
Match. Setting this bit to 0 causes the minutes value to be used in the alarm match.
Setting this bit to 1 causes the match circuit to ignore the minutes value.
Alarm – Seconds
D7
D6
D5
D4
D3
D2
D1
D0
M
10s Alarm Seconds
Alarm Seconds
Contains the alarm value for the seconds and the mask bit to select or deselect the
seconds’ value.
Match. Setting this bit to 0 causes the seconds’ value to be used in the alarm match.
Setting this bit to 1 causes the match circuit to ignore the seconds value.
Real Time Clock – Centuries
D7
D6
D5
D4
D3
D2
D1
D0
10s Centuries
Centuries
Contains the BCD value of Centuries. Lower nibble contains the lower digit and
operates from 0 to 9; upper nibble contains the upper centuries digit and operates from
0 to 9. The range for the register is 0-99 centuries.
Document Control #ML0024 Rev 2.0
Jan, 2008
24
STK17T88
0x7FF0
WDF
AF
PF
OSCF
CAL
W
R
D7
WDF
D6
AF
D5
PF
Flags
D4
D3
OSCF
0
D2
CAL
D1
W
D0
R
Watchdog Timer Flag. This read-only bit is set to 1 when the watchdog timer is allowed
to reach 0 without being reset by the user. It is cleared to 0 when the Flags register is
read or on power-up
Alarm Flag. This read-only bit is set to 1 when the time and date match the values
stored in the alarm registers with the match bits = 0. It is cleared when the Flags
register is read or on power-up
Power-fail Flag. This read-only bit is set to 1 when power falls below the power-fail
threshold VSWITCH. It is cleared to 0 when the Flags register is read or on power-up.
Oscillator Fail Flag. Set to 1 on power-up only if the oscillator is enabled and not
running in the first 5ms of operation. This indicates that the RTC backup power failed
and the clock value is no longer valid. The user must reset this bit to 0 to clear this
condition.
Calibration Mode. When set to 1, a 512Hz square wave is output on the INT pin. When
set to 0, the INT pin resumes normal operation. This bit defaults to 0 (disabled) on
power up.
Write Time. Setting the W bit to 1 freezes updates of the RTC registers. The user can
then write to the RTC registers, Alarm registers, Calibration register, Interrupt register
and Flags register. Setting the W bit to 0 disables writes to the registers and causes the
contents of the real time clock registers to be transferred to the timekeeping counters if
the time has changed (a new base time is loaded). The bit defaults to 0 on power up.
Read Time. Setting the R bit to 1 captures the current time in holding registers so that
clock updates are not during the reading process. Set the R bit to 0 to enable the
holding register to resume clock updates. The bit defaults to 0 on power up.
Document Control #ML0024 Rev 2.0
Jan, 2008
25
STK17T88
Commercial and Industrial Ordering Information
STK17T88 R F 45 I TR
Packing Option
Blank=Tube
TR= Tape & Reel
Temperature Range
Blank= Commercial (0 to 70 C)
I= Industrial (-40 to +85 C)
Access Time
25 = 25ns
45 = 45ns
Lead Finish
F = 100% Sn (Matte Tin) RoHS Compliant
Package
R= Plastic 48-pin 300 mil SSOP
Ordering Codes
Part Number
STK17T88-RF25
STK17T88-RF45
STK17T88-RF25TR
STK17T88-RF45TR
STK17T88-RF25I
STK17T88-RF45I
STK17T88-RF25ITR
STK17T88-RF45ITR
Description
3.3V 32Kx8 AutoStore nvSRAM+RTC
3.3V 32Kx8 AutoStore nvSRAM+RTC
3.3V 32Kx8 AutoStore nvSRAM+RTC
3.3V 32Kx8 AutoStore nvSRAM+RTC
3.3V 32Kx8 AutoStore nvSRAM+RTC
3.3V 32Kx8 AutoStore nvSRAM+RTC
3.3V 32Kx8 AutoStore nvSRAM+RTC
3.3V 32Kx8 AutoStore nvSRAM+RTC
Document Control #ML0024 Rev 2.0
Jan, 2008
26
SSOP48-300
SSOP48-300
SSOP48-300
SSOP48-300
SSOP48-300
SSOP48-300
SSOP48-300
SSOP48-300
Access Times
25 ns access time
45 ns access time
25 ns access time
45 ns access time
25 ns access time
45 ns access time
25 ns access time
45 ns access time
Temperature
Commercial
Commercial
Commercial
Commercial
Industrial
Industrial
Industrial
Industrial
STK17T88
Package Drawing
48 Pin SSOP
400 Pin 300 mil SSOP
TOP VIEW
(
0.620 15.75
0.630 16.00
N
0.400
0.410
) BOTTOM VIEW
)
( 10.16
10.41
7.42
)
( 7.59
0.292
0.299
.045
.055
0.292
0.299
7.42
)
( 7.59
(11.43
13.97)
1
Pin 1 indicator
.045 DIA.
(11.43)
2
3
.035
.045
.020
(5.1)
8.89
)
(11.43
SIDE VIEW
0.008
0.0135
0.025
(0.635)
(
0.203
0.343
)
(
)
( 2.41
2.79)
DIM = INCHES
DIM = mm
(
0.088
0.092
( 2.24
2.34 )
SEATING
PLANE
0.008
0.016
SEE DETAIL
A
( 0.20
0.41)
MIN
END VIEW
MAX
MIN
MAX
( 0.25
0.41 )
45°
0.095
0.110
0.620 15.75
0.630 16.00
0.010
0.016
END VIEW
0.010
(0.25)
)
GAUGE PLANE
SEATING PLANE
DETAIL A
Document Control #ML0024 Rev 2.0
Jan, 2008
27
PARTING
LINE
0.024
0.040
( 0.61
1.02 )
STK17T88
Document Revision History
Rev
Date
Change
0.0
February 2003
Publish new data sheet
0.1
March 2003
Remove 525 mil SOIC, add 48 pin SSOP and 40 pin DIP packages. Modified block diagram in
AutoStore description section.
1.0
December 2004
Parameter
Vcap Min
tVCCRISE
ICC1 Max Com.
ICC1 Max Com.
ICC1 Max Com.
ICC1 Max Ind.
ICC1 Max Ind.
ICC1 Max Ind.
ICC1 Max
ICC1 Max
tHRECALL
tSTORE
tRECALL
tGLQV
Old Value
10 μF
NA
35 mA
40 mA
50 mA
35 mA
45 mA
55 mA
1.5 mA
0.5 mA
5 ms
10 ms
20 μs
10 μs
New Value
17 μF
150 μs
50 mA
55 mA
65 mA
55 mA
60 mA
70 mA
3.0 m
3 mA
20 ms
12.5 ms
40 μs
12 μs
Notes
New Spec
@ 45 ns access
@ 35 ns access
@ 25 ns access
@ 45 ns access
@ 35 ns access
@ 25 ns access
Com. & Ind.
Com. & Ind.
@ 25 ns access
1.1
January 2005
Changed “N” package reference to “R” package.
1.2
April 2005
Changed RTC register unused bits “X” to require zero “0” value when writing values.
1.3
October 2005
Parameter
ICC3 Max Com.
ICC3 Max Ind.
ISB Max Com.
ISB Max Ind.
tRECALL
tSTORE
Max STORE Cycles
tOSCS
tOSCS
C1
C2
Old
Value
5 mA
5 mA
2 mA
2 mA
40 μa
12.5 ms
16
1x10
1 min
10 sec
2.2 pF
47 pF
New
Value
10 mA
10 mA
3 mA
3 mA
60 μs
15 ms
5
5x10
10 sec
5 sec
0 pF
56 pF
Notes
Soft Recall
Industrial Grade Only
Contact Simtex for details
@ MIN Temperature
@ 25C from Power UP
RTC Output Cap
RTC Input Cap
Removed plastic dip 32 pin package offering. Package type “W.”
1.4
December 2005
Parameter
tRECALL
tSS
NVC
DATAR
Old Value
60 μs
Undefined
1 Million
100 Years at
Unspecified
Temperature
New Value
100 μs
70 μs
500K
20 Years at Max
Temperature
Discontinued 35 ns speed grade option.
Document Control #ML0024 Rev 2.0
Jan, 2008
28
Notes
Soft Recall
New Spec
Nonvolatile STORE operations
Data Retention New
Specification
STK17T88
Rev
Date
1.5
March 2006
1.6
July 2006
Change
Removed Leaded lead finish.
Parameter
tHRE CALL
NVC
DATAR
VSWITCH Min
Old
Value
20 ms
500K
20 Years
@ 85 C
2.55 V
New Value
Notes
40 ms
200K
Power-up RECALL duration
New Nonvolatile Store Cycle
Spec
New Data Retention Spec
20 Years @
55 C
No Min. Spec
1.7
March 2007
Iout for [email protected] Volts
tEHAX, tGHAX specification of 1 ns added
tELAX, tGLAX specification deleted
tDELAY Max specification of 70 us added
tHLBL specification deleted
tSS spec of 70 uS changed from min to max.
ABE Bit Removed From Interrupt Register
Interrupt Register Initializes to 00h
Flag Bits (WDF, AF, PF) Initialize to Zero
W-bit in Flag Register Enables Writes to RTC, Alarm, Calibration, Interrupt, and Flag Registers.
Add Tape & Reel Ordering Option
Add Product Ordering Code Listing
Add Package Drawings
Reformat Entire Document
2.0
January 2008
Page 3: added thermal characteristics.
Page 5: revised recommended value verbiage.
Page 6: in the SRAM Read Cycles #1 and #2 table, revised parameter description for tELQX and
tEHQZ and changed Symbol #2 to tELEH for Read Cycle Time; updated SRAM Read Cycle #2 timing
diagram and changed title to add G controlled.
Page 9: revised the notes below the Software-Controlled Store/Recall Cycle diagram.
Page 11: in the Mode Selection table, changed column to A14-A0.
Page 12: added Stefan's revised text (italics show revision): "Refer to the DC CHARACTERISTICS
table for the size of the capacitor."
Page 13: under Hardware Store (HSB) Operation, revised first paragraph to read “The HSB pin has
a very resistive pullup...”
Page 14: added best practices section.
Revised RTC register map for registers 0x1FFF8 (D7) and 0x1FFF6 (D7, D6, D5, D3, and D2).
Page 26: added access times column to the Ordering Codes.
SIMTEK STK17T88 Datasheet, January 2008
Copyright 2008, Simtek Corporation. All rights reserved.
This datasheet may only be printed for the expressed use of Simtek Customers. No part of the datasheet may be reproduced in any other form
or means without the express written permission from Simtek Corporation. The information contained in this publication is believed to be accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein constitutes a
license, grant or transfer of any rights to any Simtek patent, copyright, trademark, or other proprietary right.
Document Control #ML0024 Rev 2.0
Jan, 2008
29