CYPRESS CY14B101K

CY14B101K
1 Mbit (128K x 8) nvSRAM With Real Time Clock
Features
Functional Description
■
Data integrity of Cypress nvSRAM combined with full featured
Real Time Clock (RTC)
■
Watchdog timer
■
Clock alarm with programmable interrupts
■
Capacitor or battery backup for RTC
The Cypress CY14B101K combines a 1 Mbit nonvolatile static
RAM with a full featured real time clock in a monolithic integrated
circuit. The embedded nonvolatile elements incorporate
QuantumTrap™ technology producing the world’s most reliable
nonvolatile memory. The SRAM is read and written an infinite
number of times, while independent, nonvolatile data resides in
the nonvolatile elements.
■
25 ns, 35 ns, and 45 ns access times
■
Hands off automatic STORE on power down with only a small
capacitor
■
STORE to QuantumTrap™ initiated by software, device pin, or
on power down
■
RECALL to SRAM initiated by software or on power up
■
Infinite READ, WRITE, and RECALL cycles
■
High reliability
❐ Endurance to 200,000 cycles
❐ Data retention: 20 years at 55°C
■
10 mA typical ICC at 200 ns cycle time
■
Single 3V operation +20%, –10%
■
Commercial and industrial temperature
■
SSOP package (ROHS compliant)
The Real Time Clock function provides an accurate clock with
leap year tracking and a programmable high accuracy oscillator.
The alarm function is programmable for one time alarm or
periodic seconds, minutes, hours, or days. There is also a
programmable watchdog timer for process control.
Logic Block Diagram
VCC
QuantumTrap
1024 x 1024
A5
STATIC RAM
ARRAY
1024 X 1024
DQ 4
DQ 5
DQ 6
VRTCcap
STORE/
RECALL
CONTROL
HSB
A15 - A 0
COLUMN IO
COLUMN DEC
INPUT BUFFERS
DQ 2
DQ 3
RECALL
VRTCbat
SOFTWARE
DETECT
DQ 0
DQ 1
POWER
CONTROL
STORE
ROW DECODER
A6
A7
A8
A9
A 12
A 13
A 14
A 15
A 16
VCAP
RTC
x1
x2
MUX
A16 - A 0
INT
A 0 A 1 A 2 A 3 A 4 A 10 A 11
DQ 7
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-06401 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised Nov 06, 2007
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CY14B101K
Pinouts
Figure 1. Pin Diagram - 48 SSOP
V CAP
1
48
V CC
A 16
2
47
A 14
A 15
3
46
HSB
4
45
5
44
WE
A 13
A 12
A7
A6
6
43
A5
7
42
A9
INT
8
41
NC
A8
A4
9
NC
10
NC
11
NC
V SS
12
NC
14
V RTCbat
15
34
DQ0
16
33
DQ 6
A3
17
32
A2
18
31
OE
A 10
13
48-SSOP
40
A 11
39
NC
38
NC
Top View
37
NC
36
(Not To Scale)
V SS
35
NC
V RTCcap
A1
19
30
A0
CE
20
29
DQ7
DQ1
21
28
DQ5
DQ2
x1
22
27
DQ4
23
26
DQ3
x2
24
25
V CC
Pin Definitions
Pin Name
IO Type
A0 – A16
Input
Description
Address inputs used to select one of the 131,072 bytes of the nvSRAM.
DQ0 – DQ7 Input Output Bidirectional Data IO Lines. Used as input or output lines depending on operation
NC
No Connect No Connects. This pin is not connected to the die
WE
Input
Write Enable Input, Active LOW. When selected LOW, enables data on the IO pins to be written
to the address location latched by the falling edge of CE.
CE
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output Enable, Active LOW. The active low OE input enables the data output buffers during READ
cycles. Deasserting OE high causes the IO pins to tri-state.
X1
Output
X2
Input
Crystal Connection, drives crystal on start up.
Crystal Connection for 32.768 kHz crystal.
VRTCcap
Power Supply Capacitor Supplied Backup RTC Supply Voltage. (Left unconnected if VRTCbat is used)
VRTCbat
Power Supply Battery Supplied Backup RTC Supply Voltage. (Left unconnected if VRTCcap is used)
INT
Output
Interrupt Output. Program to respond to the clock alarm, the watchdog timer, and the power monitor.
Programmable to either active HIGH (push or pull) or LOW (open drain).
VSS
Ground
Ground for the Device. Must be connected to ground of the system.
VCC
Power Supply Power Supply Inputs to the Device.
HSB
Input Output Hardware Store Busy. When LOW this output indicates a Hardware Store is in progress. When
pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up
resistor keeps this pin HIGH if not connected (connection optional).
VCAP
Power Supply AutoStoreTM Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
Document Number: 001-06401 Rev. *G
Page 2 of 24
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CY14B101K
Device Operation
V CC
0.1UF
V CC
10k Ohm
V CAP
V CAP
The CY14B101K nvSRAM is made up of two functional components paired in the same physical cell, a SRAM memory cell, and
a nonvolatile QuantumTrap cell. The SRAM memory cell
operates as a standard fast static RAM. Data transfers from the
SRAM to the nonvolatile cell (the STORE operation) or from the
nonvolatile cell to SRAM (the RECALL operation). This unique
architecture enables all cells to store and recall in parallel. During
the STORE and RECALL operations, SRAM READ and WRITE
operations are inhibited. The CY14B101K supports infinite reads
and writes similar to a typical SRAM. In addition, it provides
infinite RECALL operations from the nonvolatile cells and up to
200,000 STORE operations.
Figure 2. AutoStore Mode
WE
SRAM READ
The CY14B101K performs a READ cycle whenever CE and OE
are LOW, when WE and HSB are HIGH. The address specified
on pins A0-16 determines which of the 131,072 data bytes are
accessed. When the READ is initiated by an address transition,
the outputs are valid after a delay of tAA (READ cycle 1). If the
READ is initiated by CE or OE, the outputs are valid at tACE or at
tDOE, whichever is later (READ cycle 2). The data outputs
repeatedly respond to address changes within the tAA access
time without the need for transitions on any control input pins. It
remains valid until another address change or until CE or OE is
brought HIGH, or WE or HSB is brought LOW.
SRAM WRITE
A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable before entering
the WRITE cycle and must remain stable until either CE or WE
go HIGH at the end of the cycle. The data on the common IO pins
DQ0–7 is written into the memory if the data is valid tSD before
the end of a WE controlled WRITE or before the end of an CE
controlled WRITE. Keep OE HIGH during the entire WRITE cycle
to avoid data bus contention on common IO lines. If OE is left
LOW, internal circuitry turns off the output buffers tHZWE after WE
goes LOW.
AutoStore Operation
The CY14B101K stores data to nvSRAM using one of three
storage operations:
1. Hardware Store activated by HSB
2. Software Store activated by an address sequence
3. AutoStore on device power down
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B101K.
During normal operations, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to the section “DC
Electrical Characteristics” on page 14 for the size of VCAP. The
voltage on the VCAP pin is driven to 5V by a charge pump internal
Document Number: 001-06401 Rev. *G
to the chip. A pull up is placed on WE to hold it inactive during
power up.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored unless at least one
WRITE operation takes place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a WRITE operation took place. Monitor the
HSB signal by the system to detect if an AutoStore cycle is in
progress.
Hardware STORE (HSB) Operation
The CY14B101K provides the HSB pin for controlling and
acknowledging the STORE operations. Use the HSB pin to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B101K conditionally initiates a STORE operation
after tDELAY. An actual STORE cycle only begins if a WRITE to
the SRAM has taken place since the last STORE or RECALL
cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition while the STORE
(initiated by any means) is in progress.
SRAM READ and WRITE operations that are in progress when
HSB is driven LOW by any means are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
the CY14B101K continues SRAM operations for tDELAY. During
tDELAY, multiple SRAM READ operations take place. If a WRITE
is in progress when HSB is pulled LOW, it is allowed a time,
tDELAY, to complete. However, any SRAM WRITE cycles
requested after HSB goes LOW are inhibited until HSB returns
HIGH.
During any STORE operation, regardless of how it is initiated,
the CY14B101K continues to drive the HSB pin LOW, releasing
it only when the STORE is complete. After completing the
STORE operation, the CY14B101K remains disabled until the
HSB pin returns HIGH. Leave the HSB unconnected if it is not
used.
Page 3 of 24
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CY14B101K
Hardware RECALL (Power Up)
During power up or after any low power condition
(VCC < VSWITCH), an internal RECALL request is latched. When
VCC once again exceeds the sense voltage of VSWITCH, a
RECALL cycle automatically initiates and takes tHRECALL to
complete.
Software STORE
Using a software address sequence, transfer the data from the
SRAM to the nonvolatile memory. The CY14B101K software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed followed by a program of the nonvolatile
elements. Once a STORE cycle is initiated, further input and
output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If there are intervening
READ OR WRITE accesses, the sequence is aborted and no
STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence are performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE cycle
The software sequence is clocked with CE controlled READs or
OE controlled READs. Once the sixth address in the sequence
is entered, the STORE cycle commences and the chip is
disabled. It is important that READ cycles and not WRITE cycles
are used in the sequence. It is not necessary that OE is LOW for
the sequence to be valid. After the tSTORE cycle time is fulfilled,
the SRAM is activated again for READ and WRITE operation.
Software RECALL
Transfer the data from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations are
performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared and then the nonvolatile information is transferred into
the SRAM cells. After the tRECALL cycle time, the SRAM is once
again ready for READ and WRITE operations. The RECALL
operation does not alter the data in the nonvolatile elements.
Preventing AutoStore
Disable the AutoStore function by initiating an AutoStore Disable
sequence. A sequence of READ operations is performed in a
manner similar to the software STORE initiation. To initiate the
AutoStore Disable sequence, the following sequence of CE
controlled READ operations are performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8B45 AutoStore Disable
Re-enable the AutoStore by initiating an AutoStore Enable
sequence. A sequence of READ operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore Enable sequence, the following sequence of CE
controlled READ operations are performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) is issued to save the
AutoStore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
Data Protection
The CY14B101K protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when VCC is less than VSWITCH. If the CY14B101K is in a WRITE
mode (both CE and WE LOW) at power up, after a RECALL or
after a STORE, the WRITE is inhibited until a negative transition
on CE or WE is detected. This protects against inadvertent writes
during power up or brownout conditions.
Noise Considerations
The CY14B101K is a high speed memory and so must have a
high frequency bypass capacitor of approximately 0.1 µF
connected between VCC and VSS, using leads and traces that
are as short as possible. As with all high speed CMOS ICs,
careful routing of power, ground, and signals reduce circuit
noise.
.
Document Number: 001-06401 Rev. *G
Page 4 of 24
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CY14B101K
Table 1. Mode Selection
CE
WE
OE
A15 – A0
Mode
IO
Power
H
X
X
X
Not Selected
Output High Z
Standby
L
H
L
X
READ SRAM
Output Data
Active
L
L
X
X
WRITE SRAM
Input Data
Active
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
READ SRAM
READ SRAM
READ SRAM
READ SRAM
READ SRAM
AutoStore
Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[1, 2, 3]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
READ SRAM
READ SRAM
READ SRAM
READ SRAM
Read SRAM
AutoStore
Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[1, 2, 3]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Store
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active ICC2[1, 2, 3]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active[1, 2, 3]
Notes
1. The six consecutive address locations are in the order listed. WE is HIGH during all six cycles to enable a nonvolatile cycle.
2. While there are 17 address lines on the CY14B101K, only the lower 16 lines are used to control software modes.
3. O state depends on the state of OE. The IO table shown is based on OE Low.
Document Number: 001-06401 Rev. *G
Page 5 of 24
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CY14B101K
Low Average Active Power
Clock Operations
CMOS technology provides the CY14B101K the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns.
The clock registers maintain time up to 9,999 years in one
second increments. The user sets the time to any calendar time
and the clock automatically keeps track of days of the week,
month, leap years, and century transitions. There are eight
registers dedicated to the clock functions that are used to set
time with a WRITE cycle and to READ time during a READ cycle.
These registers contain the Time of Day in BCD format. Bits
defined as ‘0’ are currently not used and are reserved for future
use by Cypress.
Figure 3. Current vs. Cycle Time
Reading the Clock
While the double buffered RTC register structure reduces the
chance of reading incorrect data from the clock, halt internal
updates to the CY14B101K clock registers before reading clock
data to prevent the reading of data in transition. Stopping the
internal register updates does not affect clock accuracy. The
update process is stopped by writing a ‘1’ to the READ bit ‘R’ (in
the flags register at 0x1FFF0) and does not restart until a ‘0’ is
written to the READ bit. The RTC registers then READ when the
internal clock continues to run. Within 20 ms after a ‘0’ is written
to the READ bit, all CY14B101K registers are simultaneously
updated.
Setting the Clock
Figure 3 shows the relationship between ICC and READ/WRITE
Cycle Time. The worst case current consumption is shown for
commercial temperature range, VCC = 3.6V, and chip enable at
maximum frequency. Only standby current is drawn when the
chip is disabled.
The overall average current drawn by the CY14B101K depends
on the following items:
Setting the WRITE bit ‘W’ (in the flags register at 0x1FFF0) to a
‘1’ halts updates to the CY14B101K registers. The correct day,
date, and time are then written into the registers in 24 hour BCD
format. The time written is referred to as the ‘Base Time’. This
value is stored in nonvolatile registers and used in calculation of
the current time. Resetting the WRITE bit to ‘0’ transfers those
values to the actual clock counters, after which the clock
resumes normal operation.
■
The duty cycle of chip enable
Backup Power
■
The overall cycle rate for accesses
■
The ratio of READs to WRITEs
■
The operating temperature
■
The VCC level
The RTC in the CY14B101K is intended for permanently
powered operations. Either the VRTCcap or VRTCbat pin is
connected depending on whether a capacitor or battery is
chosen for the application. When the primary power, VCC, fails
and drops below VSWITCH, the device switches to the backup
power supply.
■
IO loading
Real Time Clock Operation
nvTIME Operation
The CY14B101K offers internal registers that contain clock,
alarm, watchdog, interrupt, and control functions. Internal double
buffering of the clock and the clock or timer information registers
prevents accessing transitional internal clock data during a
READ or WRITE operation. Double buffering also circumvents
disrupting normal timing counts or clock accuracy of the internal
clock while accessing clock data. Clock and Alarm Registers
store data in BCD format.
Document Number: 001-06401 Rev. *G
The clock oscillator uses very little current to maximize the
backup time available from the backup source. Regardless of
clock operation with the primary source removed, the data stored
in nvSRAM is secure, as it is stored in the nonvolatile elements
when power was lost.
During backup operation, the CY14B101K consumes a
maximum of 300 nA at 2V. According to the application, the user
chooses the capacitor or battery values.
Backup time values, based on maximum current specifications,
are shown in the following table. Nominal times are approximately three times longer.
Table 2. RTC Backup Time
Capacitor Value
Backup Time
0.1F
72 hours
0.47F
14 days
1.0F
30 days
Page 6 of 24
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CY14B101K
Using a capacitor has the obvious advantage of recharging the
backup source each time the system is powered up. If a battery
is used, use a 3V lithium and the CY14B101K only source
current from the battery when the primary power is removed.
However, the battery does not recharge at any time by the
CY14B101K. The battery capacity is chosen for total anticipated
cumulative downtime required over the life of the system.
Stopping and Starting the Oscillator
The OSCEN bit in the calibration register at 0x1FFF8 controls
the starting and stopping of the oscillator. This bit is nonvolatile
and is shipped to customers in the “enabled” (set to ‘0’) state. To
preserve battery life when the system is in storage, OSCEN is
set to a ‘1’. This turns off the oscillator circuit extending the
battery life. If the OSCEN bit goes from disabled to enabled, it
takes approximately 5 seconds (10 seconds max) for the
oscillator to start.
The CY14B101K has the ability to detect oscillator failure. This
is recorded in the OSCF (Oscillator Failed bit) of the Flags
register at address 0x1FFF0. When the device is powered on
(VCC goes above VSWITCH) the OSCEN bit is checked for
“enabled” status. If the OSCEN bit is enabled and the oscillator
is not active, the OSCF bit is set. The user must check for this
condition and then WRITE a ‘0’ to clear the flag. In addition to
setting the OSCF flag bit, the time registers are reset to the “Base
Time” (see the section “Setting the Clock” on page 6): the value
that is last written to the time keeping registers. The Control or
Calibration register and the OSCEN bit are not affected by the
oscillator failed condition.
If the voltage on the backup supply (either VRTCcap or VRTCbat)
falls below their minimum level, the oscillator may fail. This may
lead to the oscillator failed condition that is detected when
system power is restored.
The value of OSCF is reset to ‘0’ when the time registers are
written for the first time. This initializes the state of this bit that is
set when the system is first powered on.
Calibrating the Clock
The RTC is driven by a quartz controlled oscillator with a nominal
frequency of 32.768 kHz. Clock accuracy depends on the quality
of the crystal usually specified to 35 ppm limits at 25°C. This error
equates to +1.53 minutes in accordance with the month. The
CY14B101K employs a calibration circuit that improves the
accuracy to +1/–2 ppm at 25°C. The calibration circuit adds or
subtracts counts from the oscillator divider circuit.
The number of pulses that are suppressed (subtracted, negative
calibration) or split (added, positive calibration) depends upon
the value loaded into the five calibration bits found in calibration
register at 0x1FFF8. Adding counts speeds the clock up and
subtracting counts slows the clock down. The calibration bits
occupy the five lower order bits in the Control register 8. Set
these bits to represent any value between 0 and 31 in binary
form. Bit D5 is a sign bit, where a ‘1’ indicates positive calibration
and a ‘0’ indicates negative calibration. Calibration occurs within
a 64 minute cycle. The first 62 minutes in the cycle may, once in
accordance with minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles.
If a binary ‘1’ is loaded into the register, only the first two minutes
of the 64 minute cycle are modified. If a binary 6 is loaded, the
Document Number: 001-06401 Rev. *G
first 12 are affected, and so on. Therefore, each calibration step
has the effect of adding 512 or subtracting 256 oscillator cycles
for every 125, 829,120 actual oscillator cycles, that is, 4.068 or
–2.034 ppm of adjustment in accordance with calibration step in
the calibration register.
To determine how to set the calibration one may set the CAL bit
in the flags register at 0x1FFF0 to ‘1’ that causes the INT pin to
toggle at a nominal 512 Hz. Any deviation measured from the
512 Hz indicates the degree and direction of the required
correction. For example, a reading of 512.010124 Hz indicates
a +20 ppm error, requiring to load a –10 (001010) into the
Calibration register. Note that setting or changing the calibration
register does not affect the frequency test output frequency.
Alarm
The alarm function compares user programmed values to the
corresponding time-of-day values. When a match occurs, the
alarm event occurs. The alarm drives an internal flag, AF, and
may drive the INT pin if required.
There are four alarm match fields. They are date, hours, minutes,
and seconds. Each of these fields also has a match bit that is
used to determine if the field is used in the alarm match logic.
Setting the match bit to ‘0’ indicates that the corresponding field
is used in the match process.
Depending on the match bits, the alarm occurs as specifically as
one particular second on one day of the month or as frequently
as once in accordance with second continuously. The MSb of
each alarm register is a match bit. Selecting none of the match
bits (all 1s) indicates that no match is required. The alarm occurs
every second. Setting the match select bit for seconds to ‘0’
causes the logic to match the seconds alarm value to the current
time of day. Since a match occurs for only one value in
accordance with minute, the alarm occurs once in accordance
with minute. Likewise, setting the seconds and minutes match
bits causes an exact match of these values. Thus, an alarm
occurs once in accordance with hour. Setting seconds, minutes,
and hours causes a match once in accordance with day. Lastly,
selecting all match values causes an exact time and date match.
Selecting other bit combinations does not produce meaningful
results. However, the alarm circuit must follow the functions
described.
There are two ways a user can detect an alarm event. They are
by reading the AF flag or monitoring the INT pin. The AF flag in
the Flags register at 0x1FFF0 indicates that a date and time
match has occurred. The AF bit is set to ‘1’ when a match occurs.
Reading the Flags or Control register clears the Alarm flag bit
(and all others). A hardware interrupt pin is also used to detect
an alarm event.
Watchdog Timer
The Watchdog Timer is a free running down counter that uses
the 32 Hz clock (31.25 ms) derived from the crystal oscillator.
The oscillator is running for the watchdog to function. It begins
counting down from the value loaded in the Watchdog Timer
register.
The counter consists of a loadable register and a free running
counter. On power up, the watchdog timeout value in register
0x1FFF7 is loaded into the counter load register. Counting
begins on power up and restarts from the loadable value any time
the watchdog strobe (WDS) bit is set to ‘1’. The counter is
Page 7 of 24
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CY14B101K
compared to the terminal value of ‘0’. If the counter reaches this
value, it causes an internal flag and an optional interrupt output.
You can prevent the timeout interrupt by setting WDS bit to ‘1’
before the counter reaching ‘0’. This reloads the counter with the
watchdog timeout value and restarts. As long as the user sets
the WDS bit before the counter reaches the terminal value, the
interrupt and flag never occur.
Write new timeout values by setting the watchdog WRITE bit to
‘0’. When the WDW is ‘0’ (from the previous operation), new
writes to the watchdog timeout value bits D5–D0 enable to
modify the timeout value. When WDW is a ‘1’, writes to bits D5
– D0 are ignored. The WDW function enables a user to set the
WDS bit without concern that the watchdog timer value is
modified. A logical diagram of the watchdog timer is shown in
Figure 4. Note that setting the watchdog timeout value to ‘0’ is
otherwise meaningless and disables the watchdog function.
The output of the watchdog timer is the flag bit WDF that is set if
the watchdog is allowed to timeout. The flag is set upon a
watchdog timeout and cleared when the Flags/Control register is
Read by the user. If the watchdog timeout occurs, the user can
also enable an optional interrupt source to drive the INT pin.
Clock
Divider
32,768 KHz
1 Hz
32 Hz
Counter
Zero
Compare
WDF
Load
Register
WDS
D
Q
WDW
Q
write to
Watchdog
Register
Watchdog
Register
Power Monitor
The CY14B101K provides a power management scheme with
power fail interrupt capability. It also controls the internal switch
to backup power for the clock and protects the memory from low
VCC access. The power monitor is based on an internal band gap
reference circuit that compares the VCC voltage to various
thresholds.
As described in the “AutoStore Operation” on page 3, when
VSWITCH is reached as VCC decays from power loss, a data store
operation is initiated from SRAM to the nonvolatile elements,
securing the last SRAM data state. Power is also switched from
VCC to the backup supply (battery or capacitor) to operate the
RTC oscillator.
When operating from the backup source, no data is read or
written and the clock functions are not available to the user. The
clock continues to operate in the background. Updated clock
data is available to the user after VCC is restored to the device
Document Number: 001-06401 Rev. *G
Interrupts
The CY14B101K provides three potential interrupt sources.
They include the watchdog timer, the power monitor, and the
clock or calendar alarm. Individually enable each and assign to
drive the INT pin. In addition, each has an associated flag bit that
the host processor uses to determine the cause of the interrupt.
Some of the sources have additional control bits that determine
functional behavior. In addition, the pin driver has three bits that
specify its behavior when an interrupt occurs.
The three interrupts each have a source and an enable. Both the
source and the enable are active (true HIGH) to generate an
interrupt output. Only one source is necessary to drive the pin.
The user identifies the source by reading the Flags/Control
register, that contains the flags associated with each source. All
flags are cleared to ‘0‘ when the register is READ. The flags are
cleared only after a complete read cycle (WE HIGH). The power
monitor has two programmable settings that is explained in the
section “Power Monitor” on page 8.
Once an interrupt source is active, the pin driver determines the
behavior of the output. It has two programmable settings as
shown in the following section. Pin driver control bits are located
in the Interrupts register.
Figure 4. Watchdog Timer Block Diagram
Oscillator
and the RECALL delay (see the section “AutoStore/Power Up
RECALL” on page 16).
According to the programming selections, the pin is driven in the
backup mode for an alarm interrupt. In addition, the pin is an
active LOW (open drain) or an active HIGH (push pull) driver. If
programmed for operation during backup mode, it is only active
LOW. Lastly, the pin provides a one shot function so that the
active condition is a pulse or a level condition. In one shot mode,
the pulse width is internally fixed at approximately 200 ms. This
mode is intended to reset a host microcontroller. In level mode,
the pin goes to its active polarity until the Flags/Control register
is read by the user. This mode is used as an interrupt to a host
microcontroller. The Interrupt register is initialized to 00h. The
control bits are summarized as follows:
Watchdog Interrupt Enable – WIE. When set to ‘1’, the
watchdog timer drives the INT pin and an internal flag when a
watchdog timeout occurs. When WIE is set to ‘0’, the watchdog
timer affects only the internal flag.
Alarm Interrupt Enable – AIE. When set to ‘1’, the alarm match
drives the INT pin and an internal flag. When set to ‘0’, the alarm
match only affects the internal flag.
Power Fail Interrupt Enable – PFE. When set to ‘1’, the power
fail monitor drives the pin and an internal flag. When set to ‘0’,
the power fail monitor affects only the internal flag.
High/Low – H/L. When set to a ‘1’, the INT pin is active HIGH
and the driver mode is push pull. The INT pin drives high only
when VCC > VSWITCH. When set to a ‘0’, the INT pin is active
LOW and the drive mode is open drain. Active LOW (open drain)
is operational even in battery backup mode.
Pulse/Level – P/L. When set to a ‘1’ and an interrupt occurs, the
INT pin is driven for approximately 200 ms. When P/L is set to a
‘0’, the INT pin is driven high or low (determined by H/L) until the
Flags/Control register is READ.
Page 8 of 24
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CY14B101K
When an enabled interrupt source activates the INT pin, an
external host can READ the Flags or Control registers to
determine the cause. Remember that all flags are cleared when
the register is READ. If the INT pin is programmed for Level
mode, then the condition clears and the INT pin returns to its
inactive state. If the pin is programmed for Pulse mode, then
reading the flag also clears the flag and the pin. The pulse does
not complete its specified duration if the Flags or Control
registers are READ. If the INT pin is used as a host reset, then
the Flags or Control registers must not be READ during a reset.
During a power on reset with no battery, the Interrupt register is
automatically loaded with the value 24h. This enables power fail
interrupt with an active LOW pulse.
Flags Register – The Flags register has three flag bits: WDF,
AF, and PF. These flag bits are initialized to 00h. These flags are
set by the watchdog timeout, alarm match, or power fail monitor,
respectively. The processor either polls this register or enables
to inform interrupts when a flag is set. The flags are automatically
reset once the register is READ.
Figure 5. RTC Recommended Component Configuration
Recommended Values
Y1 = 32.768 KHz
RF = 10 MΩ
C1 = 0
C2 = 56 pF
Figure 6. Interrupt Block Diagram
WDF
Watchdog
Timer
WIE
PF
Power
Monitor
PFE
P/L
VCC
Pin
Driver
INT
VINT
H/L
VSS
AF
Clock
Alarm
AIE
Legend
WDF - Watchdog Timer Flag
WIE - Watchdog Interrupt Enable
PF - Power F ail Flag
PFE - Power Fail Enable
AF - Alarm Flag
AIE - Alarm Interrupt Enable
P/L - Pulse Level
H/L - High/Low
Document Number: 001-06401 Rev. *G
Page 9 of 24
[+] Feedback
CY14B101K
Table 3. RTC Register Map
Register
BCD Format Data
D7
D6
0x1FFFE
0
0
0x1FFFD
0
0
0x1FFFC
0
0
0x1FFFB
0
0
0x1FFFA
0
0x1FFFF
D5
D4
D3
D2
D1
10s Years
0
0
Years: 00 – 99
Months: 01 – 12
Day Of Month
Day of Month: 01 – 31
0
0
Day of week
10s Hours
0x1FFF9
0x1FFF8 OSCEN
Years
Months
10s
Months
10s Day of Month
Function/Range
D0
Day of week: 01 – 07
Hours
Hours: 00 – 23
10s Minutes
Minutes
Minutes: 00 – 59
10s Seconds
Seconds
Seconds: 00 – 59
0
Cal Sign
Calibration Values [4]
Calibration
Watchdog [4]
0x1FFF7
WDS
WDW
0x1FFF6
WIE
AIE
0x1FFF5
M
0
10s Alarm Date
Alarm Day
Alarm, Day of Month: 01 – 31
0x1FFF4
M
0
10s Alarm Hours
Alarm Hours
Alarm, Hours: 00 – 23
0x1FFF3
M
10 Alarm Minutes
Alarm Minutes
Alarm, Minutes: 00 – 59
0x1FFF2
M
10 Alarm Minutes
Alarm, Seconds
Alarm, Seconds: 00 – 59
Centuries
Centuries: 00 – 99
0x1FFF1
0x1FFF0
WDT
PFE
0
H/L
P/L
10s Centuries
WDF
AF
PF
OSCF
0
CAL
0
Interrupts [4]
0
W
Flags [4]
R
Table 4. Register Map Detail
Time Keeping – Years
D7
D6
0x1FFFF
D5
D4
D3
D2
10s Years
D1
D0
Years
Contains the lower two BCD digits of the year. Lower nibble contains the value for years and upper nibble contains
the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0 – 99.
Time Keeping – Months
0x1FFFE
D7
D6
D5
D4
0
0
0
10s Month
D3
D2
D1
D0
Months
Contains the BCD digits of the month. Lower nibble contains the lower digit and operates from 0 to 9 and upper
nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1 – 12.
Time Keeping – Date
0x1FFFD
D7
D6
0
0
D5
D4
D3
10s Day of Month
D2
D1
D0
Day of Month
Contains the BCD digits for the date of the month. Lower nibble contains the lower digit and operates from 0 to 9
and upper nibble contains the upper digit and operates from 0 to 3. The range for the register is 1 – 31. Leap years
are automatically adjusted for.
Time Keeping – Day
0x1FFFC
D7
D6
D5
D4
D3
0
0
0
0
0
D2
D1
D0
Day of Week
Lower nibble contains a value that correlates to day of the week. Day of the week is a ring counter that counts from
1 to 7 then returns to 1. The user must assign meaning to the day value, as the day is not integrated with the date.
Note
4. This register contains a binary, not BCD, value.
Document Number: 001-06401 Rev. *G
Page 10 of 24
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CY14B101K
Table 4. Register Map Detail (continued)
Time Keeping – Hours
0x1FFFB
D7
D6
12/24
0
D5
D4
D3
D2
10s Hours
D1
D0
Hours
Contains the BCD value of hours in 24 hour format. Lower nibble contains the lower digit and operates from 0 to 9
and upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0 – 23.
Time Keeping – Minutes
D7
0x1FFFA
D6
0
D5
D4
D3
D2
10s Minutes
D1
D0
Minutes
Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9 and upper nibble
contains the upper minutes digit and operates from 0 to 5. The range for the register is 0 – 59.
Time Keeping – Seconds
D7
0x1FFF9
D6
0
D5
D4
D3
D2
10s Seconds
D1
D0
Seconds
Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9 and upper nibble
contains the upper digit and operates from 0 to 5. The range for the register is 0 – 59.
Calibration/Control
0X1FFF8
OSCEN
D7
D6
D5
OSCEN
0
Calibration
Sign
D4
D3
D2
D1
D0
Calibration
Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs. Disabling the oscillator
saves battery/capacitor power during storage. On a no battery power up, this bit is set to 0.
Calibration Determines if the calibration adjustment is applied as an addition to or as a subtraction from the time base.
Sign
Calibration These five bits control the calibration of the clock.
WatchDog Timer
0x1FFF7
D7
D6
WDS
WDW
D5
D4
D3
D2
D1
D0
WDT
WDS
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no affect. The
bit is cleared automatically once the watchdog timer is reset. The WDS bit is WRITE only. Reading it always returns
a 0.
WDW
Watchdog Write Enable. Setting this bit to 1 masks the watchdog timeout value (WDT5–WDT0) so it is not written.
This enables the user to strobe the watchdog without disturbing the timeout value. Setting this bit to 0 allows bits 5
– 0 to be written on the next WRITE to the watchdog register. The new value is loaded on the next internal watchdog
clock after the WRITE cycle is complete. This function is explained in more detail in the “Watchdog Timer” on page 7.
WDT
Watchdog Timeout Selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents
a multiplier of the 32 Hz count (31.25 ms). The minimum range or timeout value is 31.25 ms (a setting of 1) and the
maximum timeout is 2 seconds (setting of 3 Fh). Setting the watchdog timer register to 0 disables the timer. These
bits are written only if the WDW bit is cleared to 0 on a previous cycle.
Document Number: 001-06401 Rev. *G
Page 11 of 24
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CY14B101K
Table 4. Register Map Detail (continued)
Interrupt Status/Control
0x1FFF6
D7
D6
D5
D4
D3
D2
D1
D0
WIE
AIE
PFIE
0
H/L
P/L
0
0
WIE
Watchdog Interrupt Enable. When set to 1 and a watchdog timeout occurs, the watchdog timer drives the INT pin
and the WDF flag. When set to 0, the watchdog timeout affects only the WDF flag.
AIE
Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin and the AF flag. When set to 0, the alarm
match only affects the AF flag.
PFIE
Power Fail Enable. When set to 1, the alarm match drives the INT pin and the AF flag. When set to 0, the power fail
monitor affects only the PF flag.
0
Reserved for future use.
H/L
High/Low. When set to a 1, the INT pin is driven active high. When set to 0, the INT pin is open drain, active LOW.
P/L
Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L) by an interrupt source for approximately
200 ms. When set to a 0, the INT pin is driven to an active level (as set by H/L) until the Flags/Control register is READ.
Alarm – Day
0x1FFF5
D7
D6
M
0
D5
D4
D3
D2
10s Alarm Date
D1
D0
Alarm Date
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.
M
Match. Setting this bit to 0 causes the date value to use the alarm match. Setting this bit to 1 causes the match circuit
to ignore the date value.
Alarm – Hours
0x1FFF4
D7
D6
M
0
D5
D4
D3
D2
10s Alarm Hours
D1
D0
Alarm Hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
M
Match. Setting this bit to 0 causes the hours value to use the alarm match. Setting this bit to 1 causes the match
circuit to ignore the hour value.
Alarm – Minutes
0x1FFF3
D7
D6
M
0
D5
D4
D3
10s Alarm Minutes
D2
D1
D0
Alarm Minutes
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.
M
Match. Setting this bit to 0 causes the minutes value to use the alarm match. Setting this bit to 1 causes the match
circuit to ignore the minute value.
Alarm – Seconds
0x1FFF2
D7
D6
M
0
D5
D4
D3
10s Alarm Seconds
D2
D1
D0
Alarm Seconds
Contains the alarm value for the seconds and the mask bit to select or deselect the second value.
M
Match. Setting this bit to 0 causes the second value to use the alarm match. Setting this bit to 1 causes the match
circuit to ignore the second value.
Time Keeping – Centuries
0x1FFF1
D7
D6
0
0
Document Number: 001-06401 Rev. *G
D5
D4
10s Centuries
D3
D2
D1
D0
Centuries
Page 12 of 24
[+] Feedback
CY14B101K
Table 4. Register Map Detail (continued)
Flags
0x1FFF0
D7
D6
D5
D4
D3
D2
D1
D0
WDF
AF
PF
OSCF
0
CAL
W
R
WDF
Watchdog Timer Flag. This READ only bit is set to 1 when the watchdog timer is allowed to reach 0 without being
reset by the user. It is cleared to 0 when the Flags/Control register is READ.
AF
Alarm Flag. This READ only bit is set to 1 when the time and date match the values stored in the alarm registers
with the match bits = 0. It is cleared when the Flags/Control register is READ.
PF
Power Fail Flag. This READ only bit is set to 1 when power falls below the power fail threshold VSWITCH. It is cleared
to 0 when the Flags/Control register is READ.
OSCF
Oscillator Fail Flag. Set to 1 on power up only if the oscillator is not running in the first 5 ms of power on operation.
This indicates that time counts are no longer valid. The user must reset this bit to 0 to clear this condition. The chip
does not clear this flag. This bit survives power cycles.
CAL
Calibration Mode. When set to 1, a 512 Hz square wave is output on the INT pin. When set to 0, the INT pin resumes
normal operation. This bit defaults to 0 (disabled) on power up.
W
Write Time. Setting the W bit to 1 freeze updates of the timekeeping registers. The user can then WRITE them with
updated values. Setting the W bit to 0 causes the transfer of contents of the time registers to the timekeeping
counters. The W bit enables writes to RTC, Alarm, Calibration, Interrupt, and Flag registers.[5]
R
READ Time. Setting the R bit to 1 copies a static image of the time keeping registers and places them in a holding
register. The user can then READ without concerns over changing values causing system errors. The R bit going
from 0 to 1 causes the time keeping capture, so the bit must be returned to 0 before reading again.
Notes
5. W bit must be set to write to any of the RTC registers except the Flag register (0X1FFF1 to 0X1FFFF)
Document Number: 001-06401 Rev. *G
Page 13 of 24
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CY14B101K
Maximum Ratings
Package Power Dissipation
Capability (TA = 25°C) ................................................... 1.0W
Exceeding maximum ratings may impair the useful life of device.
These user guidelines are not tested.
Surface Mount Pb Soldering
Temperature (3 Seconds) .......................................... +260°C
Storage Temperature ................................. –65°C to +150°C
Output Short Circuit Current [6] .................................... 15 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Supply Voltage on VCC Relative to GND ..........–0.5V to 4.1V
Latch Up Current ................................................... > 200 mA
Voltage Applied to Outputs
in High Z State ....................................... –0.5V to VCC + 0.5V
Operating Range
Input Voltage...........................................–0.5V to Vcc + 0.5V
Transient Voltage (<20 ns) on
Any Pin to Ground Potential .................. –2.0V to VCC + 2.0V
Range
Ambient Temperature
VCC
0°C to +70°C
2.7V to 3.6V
–40°C to +85°C
2.7V to 3.6V
Commercial
Industrial
DC Electrical Characteristics
Over the Operating Range (VCC = 2.7V to 3.6V) [7, 8, 9]
Parameter
ICC1
Description
Average VCC Current
Test Conditions
Min
Commercial
tRC = 25 ns
tRC = 35 ns
tRC = 45 ns
Dependent on output loading and cycle Industrial
rate. Values obtained without output
loads.
IOUT = 0 mA.
Max
Unit
65
55
50
mA
mA
mA
55
(tRC = 45 ns)
mA
mA
mA
6
mA
ICC2
Average VCC Current
during STORE
ICC3
Average VCC Current at WE > (VCC – 0.2). All other inputs cycling.
tAVAV = 200 ns, 3V, 25°C Dependent on output loading and cycle rate.
Typical
Values obtained without output loads.
10
mA
ICC4
Average VCAP Current
during AutoStore Cycle
All Inputs Do Not Care, VCC = Max
Average current for duration tSTORE
3
mA
ISB
VCC Standby Current
WE > (VCC – 0.2). All others VIN < 0.2V or
> (VCC–0.2V). Standby current level after nonvolatile
cycle is complete.
Inputs are static. f = 0 MHz
3
mA
IIX
Input Leakage Current
VCC = Max, VSS < VIN < VCC
–1
+1
μA
IOZ
Off State Output Leakage VCC = Max, VSS < VIN < VCC, CE or OE > VIH
Current
–1
+1
μA
VIH
Input HIGH Voltage[10]
2.0
VCC + 0.3
V
VIL
Input LOW Voltage
VSS – 0.5
0.8
V
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IOUT = 4 mA
VCAP
Storage Capacitor
Between VCAP pin and VSS, 5V rated
All Inputs Do Not Care, VCC = Max
Average current for duration tSTORE
IOUT = –2 mA
2.4
17
V
0.4
V
120
μF
Notes
6. Outputs shorted for no more than one second. No more than one output is shorted at a time.
7. Typical conditions for the active current shown at the beginning of the data sheet are average values at 25°C (room temperature) and VCC = 3V. Not 100% tested.
8. The HSB pin has IOUT = –10 μA for VOH of 2.4 V, this parameter is characterized but not tested.
9. The INT pin is open drain and does not source or sink current when interrupt register bit D3 is low.
10. VIH changes by 100 mV when VCC > 3.5V.
Document Number: 001-06401 Rev. *G
Page 14 of 24
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CY14B101K
Capacitance
These parameters are guaranteed but not tested.
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 0 to 3.0 V
Max
Unit
7
pF
7
pF
Thermal Resistance
These parameters are guaranteed but not tested.
Parameter
ΘJA
ΘJC
Description
Thermal Resistance
(junction to ambient)
Thermal Resistance
(junction to case)
Test Conditions
48-SSOP
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
TBD
°C/W
TBD
°C/W
AC Test Loads
R1 577Ω
R1 577Ω
For Tri-state Specs
3.0V
3.0V
OUTPUT
OUTPUT
30 pF
R2
789Ω
5 pF
R2
789Ω
AC Test Conditions
Input Pulse Levels ..................................................0 V to 3 V
Input Rise and Fall Times (10% - 90%) ........................ <5 ns
Input and Output Timing Reference Levels ................... 1.5 V
Document Number: 001-06401 Rev. *G
Page 15 of 24
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CY14B101K
AC Switching Characteristics
Parameter
25 ns Part
Description
Cypress
Alt.
Parameter Parameter
Min
Max
35 ns Part
Min
Max
45 ns Part
Min
Unit
Max
SRAM READ Cycle
tACE
tACS
Chip Enable Access Time
tRC [12]
tRC
Read Cycle Time
tAA [13]
tAA
Address Access Time
25
35
45
ns
tDOE
tOE
Output Enable to Data Valid
12
15
20
ns
tOHA [13]
tOH
Output Hold After Address Change
3
3
3
ns
tLZCE[14]
tLZ
Chip Enable to Output Active
3
3
3
ns
tHZCE
[14]
tHZ
Chip Disable to Output Inactive
tLZOE[14]
tOLZ
Output Enable to Output Active
tHZOE [14]
tOHZ
Output Disable to Output Inactive
tPU [11]
tPA
Chip Enable to Power Active
[11]
tPS
Chip Disable to Power Standby
tPD
25
25
35
35
10
0
13
0
10
0
45
ns
15
ns
0
13
0
25
ns
45
ns
15
ns
0
35
ns
45
ns
SRAM WRITE Cycle
tWC
tWC
Write Cycle Time
25
35
45
ns
tPWE
tWP
Write Pulse Width
20
25
30
ns
tSCE
tCW
Chip Enable To End of Write
20
25
30
ns
tSD
tDW
Data Setup to End of Write
10
12
15
ns
tHD
tDH
Data Hold After End of Write
0
0
0
ns
tAW
tAW
Address Setup to End of Write
20
25
30
ns
tSA
tAS
Address Setup to Start of Write
0
0
0
ns
tHA
tWR
Address Hold After End of Write
0
0
0
ns
tHZWE [14, 15] tWZ
Write Enable to Output Disable
tLZWE [14]
Output Active after End of Write
tOW
10
3
13
3
15
ns
3
ns
AutoStore/Power Up RECALL
Parameter
Description
tHRECALL [16]
Power Up RECALL Duration
tSTORE [17, 18]
STORE Cycle Duration
VSWITCH
Low Voltage Trigger Level
tVCCRISE
VCC Rise Time
CY14B101K
Min
Max
20
ms
12.5
ms
2.65
150
Unit
V
μs
Notes
11. These parameters are guaranteed but not tested.
12. WE must be HIGH during SRAM READ cycles.
13. Device is continuously selected with CE and OE both low.
14. Measured ±200 mV from steady state output voltage.
15. If WE is low when CE goes low, the outputs remain in the high impedance state.
16. tHRECALL starts from the time VCC rises above VSWITCH.
17. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE takes place.
18. Industrial grade devices require 15 ms max.
Document Number: 001-06401 Rev. *G
Page 16 of 24
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CY14B101K
Software Controlled STORE/RECALL Cycles
In the following table, the software sequence is clocked with CE controlled or OE controlled READs. The six consecutive addresses
must be READ in the order listed in the “Mode Selection” on page 5. WE must be HIGH during all six consecutive cycles. A 600Ω
resistor must be connected to HSB to use the software command.
Parameter
25 ns Part
Description
Min
Max
35 ns Part
Min
Max
45 ns Part
Min
Unit
Max
tRC
STORE/RECALL Initiation Cycle Time
25
35
45
ns
tAS
Address Setup Time
0
0
0
ns
tCW
Clock Pulse Width
20
25
30
ns
tGHAX
Address Hold Time
1
1
1
ns
tRECALL
RECALL Duration
100
100
100
μs
tSS [22, 23]
Soft Sequence Processing Time
70
70
70
μs
Hardware STORE Cycle
Parameter
CY14B101K
Description
Min
Max
70
tDELAY [24]
Time Allowed to Complete SRAM Cycle
1
tHLHX
Hardware STORE Pulse Width
15
Unit
μs
ns
RTC Characteristics
Parameters
Description
IBAK [25]
RTC Backup Current
VRTCbat [26]
RTC Battery Pin Voltage
VRTCcap [27]
RTC Capacitor Pin Voltage
tOCS
RTC Oscillator Time to Start
Test Conditions
Min
Commercial
Industrial
Commercial
1.8
Max
Units
300
nA
350
nA
3.3
V
Industrial
1.8
3.3
V
Commercial
1.2
2.7
V
Industrial
1.2
2.7
V
Commercial
10
sec
at 25°C Temperature from Power Up Commercial
or Enable
5
sec
at Min Temperature from Power Up
or Enable
Industrial
10
sec
at 25°C Temperature from Power Up Industrial
or Enable
5
sec
at Min Temperature from Power Up
or Enable
Notes
19. The software sequence is clocked with CE controlled or OE controlled READs.
20. The six consecutive addresses must be READ in the order listed in the “Mode Selection” on page 5. WE must be HIGH during all six consecutive cycles.
21. A 600Ω resistor must be connected to HSB to use the software command.
22. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register the command.
23. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
24. READ and WRITE cycles in progress before HSB are given this amount of time to complete.
25. From either VRTCcap or VRTCbat.
26. Typical = 3.0V during normal operation.
27. Typical = 2.4V during normal operation.
Document Number: 001-06401 Rev. *G
Page 17 of 24
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CY14B101K
Switching Waveforms
Figure 7 shows the SRAM Read Cycle 1(address controlled).[12, 13, 28]
Figure 7. SRAM Read Cycle 1
tRC
ADDRESS
t AA
t OHA
DQ (DATA OUT)
DATA VALID
Figure 8 shows the SRAM Read Cycle 2 (CE and OE controlled).[12, 28]
Figure 8. SRAM Read Cycle 2
tRC
ADDRESS
tLZCE
CE
tACE
tPD
tHZCE
OE
tLZOE
DQ (DATA OUT)
t PU
ICC
tHZOE
tDOE
DATA VALID
ACTIVE
STANDBY
Note
28. HSB must remain HIGH during READ and WRITE cycles.
Document Number: 001-06401 Rev. *G
Page 18 of 24
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CY14B101K
Figure 9 shows the SRAM Write Cycle 1 (WE controlled). [28, 29]
Figure 9. SRAM WRITE Cycle 1
tWC
ADDRESS
tHA
tSCE
CE
tAW
tSA
tPWE
WE
tSD
tHD
DATA VALID
DATA IN
tHZWE
DATA OUT
tLZWE
HIGH IMPEDANCE
PREVIOUS DATA
Figure 10 shows the SRAM Write Cycle 2 (CE controlled). [28, 29]
Figure 10. SRAM WRITE Cycle 2
tWC
ADDRESS
CE
WE
tHA
tSCE
tSA
tAW
tPWE
tSD
DATA IN
DATA OUT
tHD
DATA VALID
HIGH IMPEDANCE
Note
29. CE or WE must be > VIH during address transitions.
Document Number: 001-06401 Rev. *G
Page 19 of 24
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CY14B101K
Figure 11. AutoStore/Power Up RECALL
No STORE occurs
without atleast one
SRAM write
STORE occurs only
if a SRAM write
has happened
VCC
VSWITCH
tVCCRISE
AutoStore
tSTORE
tSTORE
POWER-UP RECALL
tHRECALL
tHRECALL
Read & Write Inhibited
In the following figure, The six consecutive addresses must be READ in the order listed in the “Mode Selection” on page 5. WE
must be HIGH during all six consecutive cycles.
Figure 12. CE Controlled Software STORE/RECALL Cycle
tRC
tSCE
tGHAX
ADDRESS # 6
tGLAX
OE
a
a
a
a a a
a
a
tSA
CE
a
a
a a
ADDRESS # 1
ADDRESS
tRC
DQ (DATA)
DATA VALID
Document Number: 001-06401 Rev. *G
a
a
t STORE / t RECALL
DATA VALID
HIGH IMPEDANCE
Page 20 of 24
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CY14B101K
In the following figure, The six consecutive addresses must be READ in the order listed in the “Mode Selection” on page 5. WE
must be HIGH during all six consecutive cycles.
Figure 13. OE Controlled Software STORE/RECALL Cycle
tRC
ADDRESS # 1
ADDRESS
CE
tSA
ADDRESS # 6
tSCE
OE
t STORE / t RECALL
DQ (DATA)
a
a
tGHAX
tGLAX
DATA VALID
a
a
a
a
a
a
a
a
a
a
a a
tRC
HIGH IMPEDANCE
DATA VALID
Figure 14. Hardware STORE Cycle
a
a
tHLHX
HSB (IN)
tSTORE
a
a
tHLBL
HSB (OUT)
HIGH IMPEDANCE
HIGH IMPEDANCE
a
a
t DELAY
DATA VALID
DQ (DATA OUT)
DATA VALID
In the following figure, this is the amount of time it takes to take action on a soft sequence command. Vcc power must remain
HIGH to effectively register the command. Commands such as STORE and RECALL lock out IO until operation is complete which
further increases this time. See the specific command.
Figure 15. Soft Sequence Processing
ADDRESS # 1
ADDRESS # 6
34
t SS
Soft Sequence Command
ADDRESS # 1
a
a
ADDRESS
a
a
Soft Sequence Command
34
t SS
ADDRESS # 6
VCC
Document Number: 001-06401 Rev. *G
Page 21 of 24
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CY14B101K
Part Numbering Nomenclature
CY 14 B 101 K - SP 25 X C T
Option:
T - Tape and Reel
Blank - Std.
Temperature:
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
Pb-Free
Package:
SP - 48 SSOP
Voltage:
B - 3.0V
Speed:
25 - 25 ns
35 - 35 ns
45 - 45 ns
Data Bus:
K - x8 + RTC
Density:
101 - 1 Mb
NVSRAM
14 - AutoStore + Software Store + Hardware Store
Cypress
Document Number: 001-06401 Rev. *G
Page 22 of 24
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CY14B101K
Ordering Information
All mentioned parts are Pb-free. Shaded areas contain advance information. Contact your local Cypress sales representative for
availability of these parts.
Speed
(ns)
25
25
35
35
45
45
Ordering Code
Package
Diagram
Package Type
CY14B101K-SP25XCT
51-85061
48-pin SSOP
CY14B101K-SP25XC
51-85061
48-pin SSOP
CY14B101K-SP25XIT
51-85061
48-pin SSOP
CY14B101K-SP25XI
51-85061
48-pin SSOP
CY14B101K-SP35XCT
51-85061
48-pin SSOP
CY14B101K-SP35XC
51-85061
48-pin SSOP
CY14B101K-SP35XIT
51-85061
48-pin SSOP
CY14B101K-SP35XI
51-85061
48-pin SSOP
CY14B101K-SP45XCT
51-85061
48-pin SSOP
CY14B101K-SP45XC
51-85061
48-pin SSOP
CY14B101K-SP45XIT
51-85061
48-pin SSOP
CY14B101K-SP45XI
51-85061
48-pin SSOP
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Package Diagram
Figure 16. 48-Pin Shrunk Small Outline Package, 51-85061
51-85061-*C
Document Number: 001-06401 Rev. *G
Page 23 of 24
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CY14B101K
Document History Page
Document Title: CY14B101K 1 Mbit (128K x 8) nvSRAM With Real Time Clock
Document Number: 001-06401
REV.
**
ECN NO.
425138
Issue
Date
See ECN
Orig. of Change
TUP
Description of Change
New data sheet
*A
437321
See ECN
TUP
Show data sheet on External Web
*B
471966
See ECN
TUP
Changed ICC3 from 5 mA to 10 mA
Changed ISB from 2 mA to 3 mA
Changed VIH(min) from 2.2V to 2.0V
Changed tRECALL from 40 ms to 100 ms
Changed Endurance from 1 million Cycles to 500K Cycles
Changed Data Retention from 100 years to 20 years
Added Soft Sequence Processing Time Waveform
Updated Part Numbering Nomenclature and Ordering Information
Added RTC Characteristics Table
Added RTC Recommended Component Configuration
*C
503272
See ECN
PCI
Changed from Advance to Preliminary
Changed the term “Unlimited” to “Infinite”
Changed Endurance from 500K Cycles to 200K Cycles
Added temperature spec. to Data Retention - 20 years at 55×C
Removed Icc1 values from the DC table for 25 ns and 35 ns Industrial
Grade
Changed Icc2 value from 3 mA to 6 mA in the DC Table
Added a footnote on VIH
Added footnote 18 related to using the software command
Changed VSWITCH(min) from 2.55V to 2.45V
Updated Part Nomenclature Table and Ordering Information Table
*D
597002
See ECN
TUP
Removed VSWITCH(min) specification from the AutoStore/Power Up
RECALL Table
Changed tGLAX specification from 20 ns to 1 ns
Added tDELAY(max) specification of 70 ms in the Hardware STORE Cycle
Table
Removed tHLBL specification
Changed tSS specification form 70 ms (min) to 70 ms (max)
Changed VCAP(max) from 57 mF to 120 mF
*E
688776
See ECN
VKN
Added footnote 7 related to HSB
Added footnote 8 related to INT pin
Changed tGLAX to tGHAX
Removed ABE bit from interrupt register
*F
1349963
See ECN
UHA/SFV
Changed from Preliminary to Final
Added Note 5 regarding the W bit in the Flag register
Updated Ordering Information Table
*G
1739984
See ECN
vsutmp8/AESA
Added Pinout diagram and Pin definition Table
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-06401 Rev. *G
Revised Nov 06, 2007
Page 24 of 24
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. AutoStore and QuantumTrap are
registered trademarks of Simtek Corporation. All products and company names mentioned in this document are the trademarks of their respective holders.
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