CYPRESS CY25200

CY25200
Programmable Spread Spectrum
Clock Generator for EMI Reduction
Features
Benefits
• Wide operating output (SSCLK) frequency range
• Suitable for most PC peripherals, networking, and consumer applications.
— 3–200 MHz
• Provides wide range of spread percentages for maximum
EMI reduction, to meet regulatory agency Electro Magnetic
Compliance (EMC) requirements. Reduces development
and manufacturing costs and time-to-market.
• Programmable spread spectrum with nominal 31.5-kHz
modulation frequency.
• Center spread: ±0.25% to ±2.5%
• Down spread: –0.5% to –5.0%
• Eliminates the need for expensive and difficult to use higher
order crystals.
• Input frequency range:
• Internal PLL generates up to 200 MHz outputs, and can
generate custom frequencies from an external crystal or a
driven source.
— External crystal: 8–30 MHz fundamental crystals
— External reference: 8–166 MHz Clock
• Integrated phase-locked loop (PLL)
• Enables fine-tuning of output clock frequency by adjusting
CLoad of the crystal. Eliminates the need for external CLoad
capacitors.
• Programmable crystal load capacitor tuning array
• Low cycle-to-cycle Jitter
• Application compatibility in standard and low-power systems.
• 3.3V operation with 2.5V output clock drive option
• Spread spectrum On/Off function
• Power-down or Output Enable function
• Provides ability to enable or disable spread spectrum with
an external pin.
• Output frequency select option
• Enables low-power state or output clocks to High-Z state.
Logic Block Diagram
7
Divider
Bank 1
XIN/CLKIN 1
OSC.
Q
CXOUT
8 SSCLK2
Output
Select
Matrix
Φ
VCO
XOUT 16
P
CXIN
SSCLK1
9
SSCLK3
12 SSCLK4
Divider
Bank 2
PLL
14 SSCLK5/REFOUT/CP2
15 SSCLK6/REFOUT/CP3
2
Pin Configuration
VDD
Cypress Semiconductor Corporation
Document #: 38-07633 Rev. *A
3
AVDD
•
5
11
13
AVSS
VSS
VDDL
6
VSSL
4
10
CP0
CP1
XIN
VDD
1
16
XOUT
2
15
AVDD
3
14
SSCLK6/REFOUT/CP3
SSCLK5/REFOUT/CP2
CP0
4
13
VSS
AVSS
5
12
SSCLK4
VSSL
6
11
VDDL
SSCLK1
7
10
SSCLK2
8
9
CP1
SSCLK3
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 22, 2004
CY25200
General Description
The CY25200 is a Spread Spectrum Clock Generator (SSCG)
IC used for the purpose of reducing Electro Magnetic Interference (EMI) found in today’s high-speed digital electronic
systems.
The device uses a Cypress proprietary Phase-Locked Loop
(PLL) and Spread Spectrum Clock (SSC) technology to
synthesize and modulate the frequency of the input clock. By
frequency modulating the clock, the measured EMI at the
fundamental and harmonic frequencies are greatly reduced.
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory agency requirements (EMC)
and improve time to market without degrading system performance.
The CY25200 uses a factory-programmable configuration
memory array to synthesize output frequency, spread %,
crystal load capacitor, clock control pins, PD# and OE options.
The spread % is factory programmed to either center spread
or down spread with various spread percentages. The range
for center spread is from ±0.25% to ±2.50%. The range for
down spread is from –0.5% to –5.0%. Contact the factory for
smaller or larger spread % amounts if required.
The input to the CY25200 can be either a crystal or a clock
signal. The input frequency range for crystals is 8–30 MHz,
and for clock signals is 8–166 MHz.
The CY25200 has six clock outputs, SSCLK1 to SSCLK6. The
frequency modulated SSCLK outputs can be programmed
from 3–200 MHz.
The CY25200 products are available in a 16-pin TSSOP
package with a commercial operating temperature range of 0
to 70°C.
CY25200 Pin Summary
Name
XIN
XOUT
VDD
AVDD
VSS
AVSS
VDDL
VSSL
SSCLK1
SSCLK2
SSCLK3
SSCLK4
SSCLK5/REFOUT/CP2
Pin Number
1
16
2
3
13
5
11
6
7
8
9
12
14
Description
Crystal Input or Reference Clock Input.
Crystal Output. Leave this pin floating if external clock is used.
3.3V Power supply for digital logic and SSCLK5/6 clock drives.
3.3V analog–PLL power supply
Ground
Analog ground
2.5V or 3.3V power supply for SSCLK1/2/3/4 clock drives
VDDL power supply ground
Programmable Spread Spectrum Clock Output at VDDL Level (2.5V or 3.3V)
Programmable Spread Spectrum Clock Output at VDDL Level (2.5V or 3.3V)
Programmable Spread Spectrum Clock Output at VDDL Level (2.5V or 3.3V)
Programmable Spread Spectrum Clock Output at VDDL Level (2.5V or 3.3V)
Programmable Spread Spectrum Clock or Buffered Reference Output at VDD
Level (3.3V) or Control pin, CP2
SSCLK6/REFOUT/CP3
15
CP0[1]
CP1[1]
4
10
Programmable Spread Spectrum Clock or Buffered Reference Output at VDD
Level (3.3V) or Control pin, CP3
Control Pin 0
Control Pin 1
Note:
1. Pins can be programmed to be any of the following control signals: OE: Output Enable, OE = 1 all the SSCLK outputs are enabled, PD#: Powerdown, PD#
= 0, all the SSCLK outputs are three-stated and the part enters a low-power state, SSON: Spread Spectrum Control (SSON = 0, No Spread and SSON = 1,
Spread Signal), CLKSEL: SSCLK Output Frequency Select. Please see page 3 for control pins programming option.
Document #: 38-07633 Rev. *A
Page 2 of 11
CY25200
Table 1. Fixed Function Pins
Pin
Function
Pin Name
Input
Frequency
CXIN and
CXOUT
Spread
Percent
Frequency
Modulation
SSCLK4
XIN and
XOUT
XIN and
XOUT
SSCLK[1:6]
SSCLK[1:6]
Output Clock Functions and Frequency
SSCLK1
SSCLK2
SSCLK3
Pin#
7
8
9
12
1 and 16
1 and 16
Units
MHz
MHz
MHz
MHz
MHz
pF
7,8,9,12,14,15 7,8,9,12,14,15
%
kHz
Program Value
CLKSEL = 0
ENTER
DATA
ENTER
DATA
ENTER
DATA
ENTER
DATA
Program Value
CLKSEL = 1
ENTER
DATA
ENTER
DATA
ENTER
DATA
ENTER
DATA
ENTER
DATA
ENTER
DATA
ENTER
DATA
31.5
Table 2. Multi-function Pins
Pin
Function
Output Clock /REFOUT /OE/SSON/CLKSEL
OE/PD#/SSON/CLKSEL
Pin Name
SSCLK5/REFOUT/CP2
SSCLK6/REFOUT/CP3
CP0
CP1
Pin#
14
15
4
10
N/A
N/A
ENTER DATA
ENTER DATA
Units
MHz
MHz
Program Value
CLKSEL = 0
ENTER DATA
ENTER DATA
Program Value
CLKSEL = 1
ENTER DATA
ENTER DATA
Programming Description
Customers planning to use the CY25200 need to provide the
programming information described as “ENTER DATA” in
Table 1 and Table 2, then should contact local Cypress Sales.
Additional information on the CY25200 can be obtained from
the Cypress web site at www.cypress.com.
Product Functions
Control Pins (CP0, CP1, CP2 and CP3)
There are four control signals available through programming
of pins 4, 10, 14 and 15.
CP0 (pin 4) and CP1 (pin10) are specifically designed to
function
as
control
pins.
However
pins
14
(SSCLK5/REFOUT/CP2) and 15 (SSCLK6/REFOUT/CP3)
are multi-functional and can be programmed to be a control
signal or an output clock (SSCLK or REFOUT). All of the
control pins, CP0, CP1, CP2 and CP3 are programmable and
can be programmed to have only one of the following
functions:
• Output Enable (OE), if OE = 1, all the SSCLK or REFOUT
outputs are enabled
• SSON, Spread spectrum control, 1 = spread on and 0 =
spread off
• CLKSEL, SSCLK output frequency select
• PD#, Active Low, PD# = 0, all the outputs are three-stated
and the part enters a low-power state
• The last control signal is the Power down (PD#) that can be
implemented only through programming CP0 or CP1 (CP2
and CP3 can not be programmed as PD#). Here is an example with 3 control pins,
• CLKIN = 33MHz
• SSCLK1/2/3/4 = 100MHz with ±1% Spread
• SSCLK 5 = REFOUT(33MHz)
• CP0 (Pin 4) = PD#
• CP1 (Pin 10) = OE
• CP3 (pin 15) = SSON
The pinout for the above example is shown in Figure 1.
33.0MHz
VDD
1
16
NC
2
15
SSON
AVDD
3
14
REFOUT(33.0MHz)
PD#
4
13
VSS
AVSS
5
12
100MHz
VSSL
6
11
VDDL
100MHz
7
10
OE
100MHz
8
9
100MHz
Figure 1.
Document #: 38-07633 Rev. *A
Page 3 of 11
CY25200
The CLKSEL control pin enables the user to change the output
frequency from one frequency (e.g., frequency A) to another
frequency (e.g., frequency B). These must be related
frequencies that can be derived off of a common VCO
frequency, e.g., 33.333 MHz and 66.666 MHz can both be
derived from a VCO = 400 MHz and dividing it down by 12 and
6 respectively. Table 3 shows an example of how this can be
implemented. The VCO frequency range is 100–400MHz. The
CY25200 has two separate dividers, Divider 1 and Divider 2,
these two can be loaded to have any number between 2 and
130 providing two different but related frequencies as
explained above.
For example, if a fundamental 16-MHz crystal with CL of 16 pF
is used and CP is 2 pF, CXIN and CXOUT can be calculated as:
CXIN = CXOUT = (2 x 16) – 2 = 30 pF.
If using a driven reference clock, set CXIN and CXOUT to the
minimum value 12 pF.
Output Frequency (SSCLK1 through SSCLK6 Outputs)
All of the SSCLK outputs are produced by synthesizing the
input reference frequency using a PLL and modulating the
VCO frequency. SSCLK[1:4] can be programmed to be only
output clocks (SSCLK). SSCLK5 and SSCLK6 can also be
programmed to function the same as SSCLK[1:4] or a buffered
copy of the input reference (REFOUT) or they can be
programmed to be a control pin as discussed in the control
pins section. To utilize the 2.5V output drive option on
SSCLK[1:4], VDDL must be connected to a 2.5V power supply
(SSCLK[1:4] outputs are powered by VDDL). When using the
2.5V output drive option, the maximum output frequency on
SSCLK[1:4] is 166MHz.
In the above example SSCLK5 (pin 14) and SSCLK6(pin 15)
are used as output clocks, however they could have been
used as control signals. See Figure 2 for the pinout.
Input Frequency (XIN, pin 1 and XOUT, pin 16)
The input to the CY25200 can be a crystal or a clock. The input
frequency range for crystals is 8 to 30 MHz, and for clock signal is 8 to 166 MHz.
Spread Percentage (SSCLK1 through SSCLK6 Outputs)
CXIN and CXOUT (pin 1 and pin 16)
The SSCLK frequency can be programmed at any percentage
value from ±0.25% to ±2.5% for Center Spread and from
–0.5% to –5.0% Down Spread.
The load capacitors at pin 1 (CXIN) and pin 16 (CXOUT) can be
programmed from 12 pF to 60 pF with 0.5-pF increments. The
programmed value of these on-chip crystal load capacitors are
the same (XIN = XOUT = 12 to 60 pF).
Frequency Modulation
The required values of CXIN and CXOUT for matching crystal
load (CL) can be calculated using the following formula:
The frequency modulation is programmed at 31.5 kHz for all
SSCLK frequencies from 3 to 200 MHz. Contact the factory if
a higher modulation frequency is required.
CXIN = CXOUT = 2CL – CP
Where CL is the crystal load capacitor as specified by the crystal manufacturer and CP is the parasitic PCB capacitance.
Table 3. Using Clock Select, CLKSEL Control Pin
Input Freq.
(MHz)
CLKSEL
(Pin 4)
SSCLK1
(Pin 7)
SSCLK2
(Pin 8)
SSCLK3
(Pin 9)
SSCLK4
(Pin 12)
REFOUT
(Pin 14)
REFOUT
(Pin 15)
14.318
CLKSEL = 0
33.33
33.33
33.33
33.33
14.318
14.318
CLKSEL = 1
66.66
66.66
66.66
66.66
14.318
14.318
14.318MHz
VDD
1
16
XOUT
2
15
REFOUT(14.318MHz)
AVDD
3
14
REFOUT(14.318MHz)
CLKSEL
4
13
VSS
AVSS
5
12
33.33/66.66MHz
VSSL
6
11
VDDL
33.33/66.66MHz
7
10
SSON
33.33/66.66MHz
8
9
33.33/66.66MHz
Figure 2. Table 3 Configuration Pinout
Document #: 38-07633 Rev. *A
Page 4 of 11
CY25200
Switching Waveforms
Duty Cycle Timing (DC = t1A/t1B)
t1A
OUTPUT
t1B
Output Rise/Fall Time (SSCLK and REFCLK)
VDD
OUTPUT
0V
Tr
Tf
Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3)
Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4)
Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
Power-down Timing and Power-up Timing
POWERDOWN
VDD
0V
VIH
VIL
tPU
High Impedance
SSCLK
(Asynchronous)
tSTP
Output Enable/Disable Timing
OUTPUT
ENABLE
VDD
0V
VIH
VIL
TOE2
High Impedance
SSCLK
(Asynchronous)
TOE1
Document #: 38-07633 Rev. *A
Page 5 of 11
CY25200
Informational Graphs [2]
172.5
161.5
169.5
169
168.5
168
167.5
167
166.5
166
165.5
165
164.5
164
163.5
163
160.5
162.5
171.5
Spread Spectrum Profile: Fnom=166MHz,
Fmod=30kHz, Spread%= -4%
170.5
169.5
168.5
167.5
166.5
Fnominal
165.5
164.5
163.5
162.5
159.5
0
20
68.5
40
60
80
100
120
Time (us)
140
160
180
Fnominal
0
200
Spread Spectrum Profile: Fnom=66MHz,
Fmod=30kHz, Spread%= -4%
68
Spread Spectrum Profile: Fnom=166MHz,
Fmod=30kHz, Spread%= +/-1%
20
67.5
40
60
80
100 120
Time (us)
140
160
180
200
Spread Spectrum Profile: Fnom=66MHz,
Fmod=30kHz, Spread%= +/-1%
67
67.5
67
66.5
66.5
Fnominal
66
Fnominal
66
65.5
65.5
65
64.5
65
64
64.5
63.5
0
20
40
60
80
100
120
Time (us)
140
160
180
200
0
20
40
60
80
100 120
Time (us)
140
160
180
200
Note:
2. The “Informational Graphs” are meant to convey the typical performance levels. No performance specifications is implied or guaranteed. Refer to the tables on
pages 4 and 5 for device specifications.
Document #: 38-07633 Rev. *A
Page 6 of 11
CY25200
Absolute Maximum Rating
Junction Temperature ................................ –40°C to +125°C
Supply Voltage (VDD) .......................................–0.5 to +7.0V
DC Input Voltage...................................... –0.5V to VDD + 0.5
Storage Temperature (Non-condensing)..... –55°C to +125°C
Data Retention @ Tj = 125°C............................... > 10 Years
Package Power Dissipation...................................... 350 mW
Static Discharge Voltage.......................................... > 2000V
(per MIL-STD-883, Method 3015)
Recommended Crystal Specifications
Parameter
Description
Comments
Min. Typ. Max. Unit
FNOM
Nominal Crystal Frequency
Parallel resonance, fundamental mode, AT cut
8
30
MHz
CLNOM
Nominal Load Capacitance
Internal load caps
6
30
pF
R1
Equivalent Series Resistance (ESR)
Fundamental mode
25
Ω
R3/R1
Ratio of Third Overtone Mode ESR to Ratio used because typical R1 values are much
Fundamental Mode ESR
less than the maximum spec
DL
Crystal Drive Level
2
mW
3
No external series resistor assumed
0.5
Recommended Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Unit
VDD
Operating Voltage
3.135
3.3
3.465
V
VDDLHI
Operating Voltage
3.135
3.3
3.465
V
VDDLLO
Operating Voltage
2.375
2.5
2.625
V
TAC
Ambient Commercial Temp
0
–
70
°C
CLOAD
Max. Load Capacitance VDD/VDDL = 3.3V
–
–
15
pF
CLOAD
Max. Load Capacitance VDDL = 2.5V
–
–
15
pF
FSSCLK-HighVoltage
SSCLK1/2/3/4/5/6 when VDD = AVDD = VDDL =
3.3 V
3
–
200
MHz
FSSCLK-LowVoltage
SSCLK5/6 when VDD = 3.3.V and VDDL = 2.5V
3
–
166
MHz
REFOUT
REFOUT when VDD = AVDD = 3.3.V and VDDL =
3.3V or 2.5V
8
–
166
MHz
fREF1
Clock Input
8
–
166
MHz
fREF2
Crystal Input
tPU
Power-up time for all VDDs to reach minimum
specified voltage (power ramps must be
monotonic)
8
–
30
MHz
0.05
–
500
ms
DC Electrical Specifications
Parameter[4]
Name
Description
Min.
Typ.
Max.
Unit
IOH3.3
Output High Current
VOH = VDD – 0.5V, VDD/VDDL = 3.3V
10
12
–
mA
IOL3.3
Output Low Current
VOL = 0.5V, VDD/VDDL = 3.3V
10
12
–
mA
IOH2.5
Output High Current
VOH = VDDL – 0.5V, VDDL = 2.5V
8
16
–
mA
IOL2.5
Output Low Current
VOL = 0.5V, VDDL = 2.5V
8
16
–
mA
VIH
Input High Voltage
CMOS levels, 70% of VDD
0.7
–
1.0
VDD
VIL
Input Low Voltage
CMOS levels, 30% of VDD
0
–
0.3
VDD
IVDD[5]
Supply Current
AVDD/VDD Current
–
–
33
mA
IVDDL2.5[5]
Supply Current
VDDL Current (VDDL = 2.625V)
–
–
20
mA
IVDDL3.3[5]
Supply Current
VDDL Current (VDDL = 3.465V)
–
–
26
mA
IDDS
Power-Down Current
VDD = VDDL = AVDD = 3.465V
–
–
50
uA
IOHZ
IOLZ
Output Leakage
VDD = VDDL = AVDD = 3.465V
–
–
10
uA
Notes:
3. Rated for 10 years.
4. Not 100% tested, guaranteed by design.
5. IVDD currents specified for SSCLK1/2/3/4/5/6 = 33.33 MHz with CLKIN = 14.318 MHz and 15 pF on all the output clocks.
Document #: 38-07633 Rev. *A
Page 7 of 11
CY25200
AC Electrical Specifications
Parameter
DC
Description
Condition
Min.
Typ.
Max. Unit
Output Duty Cycle
SSCLK, Measured at VDD/2
45
50
55
%
Output Duty Cycle
REFCLK, Measured at VDD/2
Duty Cycle of CLKIN = 50%.
40
50
60
%
Rising/Falling Edge Slew Rate SSCLK1/2/3/4 < 100 MHz, VDD = VDDL = 3.3V
0.6
–
2.0
V/ns
SR2
Rising/Falling Edge Slew Rate SSCLK1/2/3/4 ≥ 100 MHz, VDD = VDDL = 3.3V
0.8
–
3.5
V/ns
SR3
Rising/Falling Edge Slew Rate SSCLK1/2/3/4 < 100 MHz, VDD = VDDL = 2.5V
0.5
–
2.2
V/ns
SR4
Rising/Falling Edge Slew Rate SSCLK1/2/3/4 ≥ 100 MHz, VDD = VDDL = 2.5V
0.6
–
3.0
V/ns
SR5
Rising/Falling Edge Slew Rate SSCLK5/6 < 100 MHz, VDD = VDDL = 3.3V
0.6
–
1.9
V/ns
SR6
Rising/Falling Edge Slew Rate SSCLK5/6 ≥ 100 MHz, VDD = VDDL = 3.3V
TCCJ1
Cycle-to-Cycle Jitter
SSCLK1/2/3/4
SR1
TCCJ2
TCCJ3
TCCJ4
Cycle-to-Cycle Jitter
SSCLK5/6=REFOUT
Cycle-to-Cycle Jitter
SSCLK1/2/3/4
Cycle-to-Cycle Jitter
SSCLK5/6=REFOUT
1.0
–
2.9
V/ns
CLKIN = SSCLK1/2/3/4 = 166MHz, ±2% spread and
SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
110
ps
CLKIN = SSCLK1/2/3/4 = 66.66 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
170
ps
CLKIN = SSCLK1/2/3/4 = 33.33 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
140
ps
CLKIN = SSCLK1/2/3/4 = 14.318MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
290
CLKIN = SSCLK1/2/3/4 = 166 MHz, ±2% spread and
SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
100
ps
CLKIN = SSCLK1/2/3/4 = 66.66 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
120
ps
CLKIN = SSCLK1/2/3/4 = 33.33 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
180
ps
CLKIN = SSCLK1/2/3/4 = 14.318 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
180
CLKIN = SSCLK1/2/3/4 = 166 MHz, ±2% spread and
SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V
–
–
110
ps
CLKIN = SSCLK1/2/3/4 = 66.66MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V
–
–
170
ps
CLKIN = SSCLK1/2/3/4 = 33.33 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V
–
–
190
ps
CLKIN = SSCLK1/2/3/4 = 14.318 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V
–
–
330
CLKIN = SSCLK1/2/3/4 = 166 MHz, ±2% spread and
SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V
–
–
90
ps
CLKIN = SSCLK1/2/3/4 = 66.66 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V
–
–
110
ps
CLKIN = SSCLK1/2/3/4 = 33.33 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V
–
–
160
ps
CLKIN = SSCLK1/2/3/4 = 14.318MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V
–
–
150
tSTP
Power-down Time
(pin3 = PD#)
Time from falling edge on PD# to stopped outputs
(Asynchronous)
–
150
300
ns
TOE1
Output Disable Time
(pin3 = OE)
Time from falling edge on OE to stopped outputs
(Asynchronous)
–
150
300
ns
TOE2
Output Enable Time
(pin3 = OE)
Time from rising edge on OE to outputs at a valid
frequency (Asynchronous)
–
150
300
ns
FMOD
Spread Spectrum Modulation SSCLK1/2/3/4/5/6
Frequency
30.0
31.5
33.0
kHz
Document #: 38-07633 Rev. *A
Page 8 of 11
CY25200
AC Electrical Specifications (continued)
Min.
Typ.
tPU1
Parameter
Power-up Time,
Crystal is used
Description
Time from rising edge on PD# to outputs at valid
frequency (Asynchronous)
Condition
–
3
Max. Unit
5
ms
tPU2
Power-up Time,
Reference clock is used
Time from rising edge on PD# to outputs at valid
frequency (Asynchronous)
–
2
3
ms
Ordering Information
Ordering Code[6]
Package Type
Temperature Operating Range
CY25200ZXC_XXXW
16-lead TSSOP (Lead Free)
Commercial, 0 to 70°C
CY25200ZXC_XXXWT
16-lead TSSOP- Tape and Reel (Lead Free)
Commercial, 0 to 70°C
16-lead TSSOP Package Characteristics
Parameter
Name
Value
Unit
θJA
theta JA
115
°C/W
Notes:
6. “XXX” denotes the assigned product dash number. “W” denotes the different revisions of the product.
Document #: 38-07633 Rev. *A
Page 9 of 11
CY25200
Package Drawing and Dimension
16-lead TSSOP 4.40 MM Body Z16.173
PIN 1 ID
DIMENSIONS IN MM[INCHES] MIN.
1
MAX.
REFERENCE JEDEC MO-153
6.25[0.246]
6.50[0.256]
PACKAGE WEIGHT 0.05gms
4.30[0.169]
4.50[0.177]
16
0.65[0.025]
BSC.
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
0.25[0.010]
BSC
GAUGE
PLANE
0°-8°
0.076[0.003]
0.85[0.033]
0.95[0.037]
4.90[0.193]
5.10[0.200]
0.05[0.002]
0.15[0.006]
SEATING
PLANE
0.50[0.020]
0.70[0.027]
0.09[[0.003]
0.20[0.008]
51-85091-*A
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07633 Rev. *A
Page 10 of 11
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY25200
Document History Page
Document Title: CY25200 Programmable Spread Spectrum Clock Generator for EMI Reduction
Document Number: 38-07633
REV.
ECN NO.
Issue Date
Orig. of Change
**
204243
See ECN
RGL
New Data Sheet
*A
220043
See ECN
RGL
Minor Change: Corrected letter assignment in the
ordering info for Lead Free.
Document #: 38-07633 Rev. *A
Description of Change
Page 11 of 11