CY25200 Programmable Spread Spectrum Clock Generator for EMI Reduction Features Benefits ■ Wide operating output (SSCLK) frequency range ❐ 3–200 MHz ■ Suitable for most PC peripherals, networking, and consumer applications. ■ Programmable spread spectrum with nominal 31.5 kHz modulation frequency ■ ■ Center spread: ±0.25% to ±2.5% Provides wide range of spread percentages for maximum EMI reduction to meet regulatory agency Electro Magnetic Compliance (EMC) requirements. Reduces development and manufacturing costs and time to market. ■ Down spread: –0.5% to –5.0% ■ ■ Input frequency range ❐ External crystal: 8–30 MHz fundamental crystals ❐ External reference: 8–166 MHz clock Eliminates the need for expensive and difficult to use higher order crystals. ■ Internal PLL generates up to 200 MHz outputs; also generates custom frequencies from an external crystal or a driven source. ■ Integrated phase-locked loop (PLL) ■ ■ Programmable crystal load capacitor tuning array Enables fine tuning of output clock frequency by adjusting CLoad of the crystal. Eliminates the need for external CLoad capacitors. ■ Low cycle-to-cycle jitter ■ Application compatibility in standard and low power systems. ■ 3.3V operation with 2.5V output clock drive option ■ ■ Spread spectrum On and Off function Provides ability to enable or disable spread spectrum with an external pin. ■ Power down or Output Enable function ■ Enables low power state or output clocks to High-Z state. ■ Output frequency select option ■ Enables quick generation of sample prototype quantities. ■ Field-programmable ■ Package: 16 pin TSSOP Logic Block Diagram 7 Divider Bank 1 XIN/CLKIN 1 OSC. Q CXOUT 8 SSCLK2 Output Select Matrix Φ VCO XOUT 16 SSCLK1 9 SSCLK3 12 SSCLK4 P CXIN Divider Bank 2 PLL 14 SSCLK5/REFOUT/CP2 15 SSCLK6/REFOUT/CP3 2 VDD Cypress Semiconductor Corporation Document #: 38-07633 Rev. *D • 3 AVDD 5 AVSS 13 VSS 11 VDDL 198 Champion Court 6 VSSL • 4 10 CP0 CP1 San Jose, CA 95134-1709 • 408-943-2600 Revised December 11, 2007 [+] Feedback CY25200 Pin Configuration Figure 1. Pin Diagram General Description The CY25200 is a Spread Spectrum Clock Generator (SSCG) IC used to reduce Electro Magnetic Interference (EMI) found in today’s high speed digital electronic systems. The device uses a Cypress proprietary Phase-Locked Loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the input clock. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies are greatly reduced. This reduction in radiated energy significantly reduces the cost of complying with regulatory agency requirements (EMC) and improves time to market, without degrading system performance. The CY25200 uses a factory and field-programmable configuration memory array to synthesize output frequency, spread %, crystal load capacitor, clock control pins, PD#, and OE options. The spread % is factory and field-programmed to either center spread or down spread with various spread percentages. The range for center spread is from ±0.25% to ±2.50%. The range for down spread is from –0.5% to –5.0%. Contact the factory for smaller or larger spread % amounts, if required. The input to the CY25200 is either a crystal or a clock signal. The input frequency range for crystals is 8–30 MHz and for clock signals is 8–166 MHz. The CY25200 has six clock outputs, SSCLK1 to SSCLK6. The frequency modulated SSCLK outputs are programmed from 3–200 MHz. The CY25200 products are available in a 16-pin TSSOP package with a commercial operating temperature range of 0 to 70°C. Table 1. Pin Summary Name Pin Number Description XIN 1 Crystal Input or Reference Clock Input XOUT 16 Crystal Output. Leave this pin floating if external clock is used VDD 2 3.3V power supply for digital logic and SSCLK5 and 6 clock drives AVDD 3 3.3V analog–PLL power supply VSS 13 Ground AVSS 5 Analog ground VDDL 11 2.5V or 3.3V power supply for SSCLK1/2/3/4 clock drives VSSL 6 VDDL power supply ground SSCLK1 7 Programmable spread spectrum clock output at VDDL level (2.5V or 3.3V) SSCLK2 8 Programmable spread spectrum clock output at VDDL level (2.5V or 3.3V) SSCLK3 9 Programmable spread spectrum clock output at VDDL level (2.5V or 3.3V) SSCLK4 12 Programmable spread spectrum clock output at VDDL level (2.5V or 3.3V) SSCLK5/REFOUT/CP2 14 Programmable spread spectrum clock or buffered reference output at VDD level (3.3V) or control pin, CP2 SSCLK6/REFOUT/CP3 15 Programmable spread spectrum clock or buffered reference output at VDD level (3.3V) or control pin, CP3 CP0[1] 4 Control pin 0 CP1[1] 10 Control pin 1 Note 1. Pins are programmed to be any of the following control signals: OE: Output Enable, OE = 1, all the SSCLK outputs are enabled; PD#: Power down, PD# = 0, all the SSCLK outputs are three-stated and the part enters a low power state; SSON: Spread Spectrum Control (SSON = 0, No Spread and SSON = 1, Spread Signal), CLKSEL: SSCLK Output Frequency Select. Please see Control Pins (CP0, CP1, CP2 and CP3) for control pins programming options. Document #: 38-07633 Rev. *D Page 2 of 12 [+] Feedback CY25200 Table 2. Fixed Function Pins Pin Function Output Clock Functions and Frequency Input Frequency CXIN and CXOUT Spread Percent Frequency Modulation SSCLK[1:6] SSCLK[1:6] Pin Name SSCLK1 SSCLK2 SSCLK3 SSCLK4 XIN and XOUT XIN and XOUT Pin# 7 8 9 12 1 and 16 1 and 16 MHz pF % kHz ENTER DATA ENTER DATA ENTER DATA 31.5 Units MHz MHz MHz MHz Program Value CLKSEL = 0 ENTER DATA ENTER DATA ENTER DATA ENTER DATA Program Value CLKSEL = 1 ENTER DATA ENTER DATA ENTER DATA ENTER DATA 7,8,9,12,14,15 7,8,9,12,14,15 Table 3. Multi-Function Pins Pin Function Output Clock/REFOUT/OE/SSON/CLKSEL OE/PD#/SSON/CLKSEL Pin Name SSCLK5/REFOUT/CP2 SSCLK6/REFOUT/CP3 CP0 CP1 Pin# 14 15 4 10 N/A N/A ENTER DATA ENTER DATA Units MHz MHz Program Value CLKSEL = 0 ENTER DATA ENTER DATA Program Value CLKSEL = 1 ENTER DATA ENTER DATA Programming Description Field-Programmable CY25200 The CY25200 is programmed at the package level, that is, in a programmer socket. The CY25200 is Flash technology based, so the parts are reprogrammed up to 100 times. This allows for fast and easy design changes and product updates, and eliminates any issues with old and out of date inventory. Samples and small prototype quantities are programmed on the CY3672 programmer with the CY3695 socket adapter. CyberClocks™ Online Software CyberClocks™ Online Software is a web based software application that allows the user to custom configure the CY25200. All the parameters in given as “Enter Data” are programmed into the CY25200. CyberClocks Online outputs an industry standard JEDEC file used for programming the CY25200. CyberClocks Online is available at www.cyberclocksonline.com website through user registration. To register, fill out the registration form Document #: 38-07633 Rev. *D and make sure to check the “non-standard devices” box. For more information on the registration process refer to the CY3672 data sheet. For information regarding Spread Spectrum software programming solutions, please contact your local Cypress Sales or Field Application Engineer (FAE), representative for details. Factory-Programmable CY25200 Factory programming is available for volume manufacturing by Cypress. All requests must be submitted to the local Cypress Field Application Engineer (FAE) or sales representative. The sample request form provided by the representative must be completed. When the request is processed, you receive a new part number, samples, and data sheet with the programmed values. This part number is used for additional sample requests and production orders. Additional information on the CY25200 are available on the Cypress website at www.cypress.com. Page 3 of 12 [+] Feedback CY25200 Product Functions Control Pins (CP0, CP1, CP2 and CP3) There are four control signals available through programming of pins 4, 10, 14, and 15. CP0 (pin 4) and CP1 (pin10) are specifically designed to function as control pins. However pins 14 (SSCLK5/REFOUT/CP2) and 15 (SSCLK6/REFOUT/CP3) are multi-functional and are programmed to be a control signal or an output clock (SSCLK or REFOUT). All of the control pins, CP0, CP1, CP2, and CP3 are programmable and are programmed to have only one of the following functions: ■ Output Enable (OE)—if OE = 1, all the SSCLK or REFOUT outputs are enabled. shows an example of how this is implemented. The VCO frequency range is 100–400MHz. The CY25200 has two separate dividers, Divider 1 and Divider 2. These two are loaded to have any number between 2 and 130 providing two different but related frequencies as explained above. In the above example SSCLK5 (pin 14) and SSCLK6 (pin 15) are used as output clocks. However, they can also be used as control signals. See Figure 3 for the pinout. Input Frequency (XIN, pin 1 and XOUT, pin 16) The input to the CY25200 is a crystal or a clock. The input frequency range for crystals is 8 to 30 MHz, and for clock signal is 8 to 166 MHz. CXIN and CXOUT (pin 1 and pin 16) ■ SSON, Spread spectrum control—1 = spread on and 0 = spread off. ■ CLKSEL—SSCLK output frequency select The load capacitors at pin 1 (CXIN) and pin 16 (CXOUT) are programmed from 12 pF to 60 pF with 0.5 pF increments. The programmed value of these on-chip crystal load capacitors are the same (XIN = XOUT = 12 to 60 pF). ■ PD#, Active Low—if PD# = 0, all the outputs are three-stated and the part enters a low power state. The required values of CXIN and CXOUT for matching crystal load (CL) is calculated using the following formula: The last control signal is the power down (PD#) that is implemented only through programming CP0 or CP1 (CP2 and CP3 cannot be programmed as PD#). Here is an example with three control pins: CXIN = CXOUT = 2CL – CP Where CL is the crystal load capacitor as specified by the crystal manufacturer and CP is the parasitic PCB capacitance. ■ CLKIN = 33 MHz For example, if a fundamental 16 MHz crystal with CL of 16 pF is used and CP is 2 pF, CXIN and CXOUT is calculated as: ■ SSCLK1/2/3/4 = 100 MHz with ±1% spread CXIN = CXOUT = (2 x 16) – 2 = 30 pF. ■ SSCLK 5 = REFOUT(33 MHz) ■ CP0 (Pin 4) = PD# If using a driven reference clock, set CXIN and CXOUT to the minimum value 12 pF. ■ CP1 (Pin 10) = OE ■ CP3 (pin 15) = SSON Output Frequency (SSCLK1 through SSCLK6 Outputs) The pinout for the above example is shown in Figure 2. Figure 2. Pin Diagram 33.0MHz VDD 1 16 NC 2 15 SSON AVDD 3 14 REFOUT(33.0MHz) PD# 4 13 VSS AVSS 5 12 100MHz VSSL 6 11 VDDL 100MHz 7 10 OE 100MHz 8 9 100MHz The CLKSEL control pin enables the user to change the output frequency from one frequency to another (for example, frequency A to frequency B). These must be related frequencies that are derived off of a common VCO frequency. For instance, 33.333 MHz and 66.666 MHz are both derived from a VCO of 400 MHz and dividing it down by 12 and 6 respectively. Table 4 Document #: 38-07633 Rev. *D All of the SSCLK outputs are produced by synthesizing the input reference frequency using a PLL and modulating the VCO frequency. SSCLK[1:4] is programmed to be only output clocks (SSCLK). SSCLK5 and SSCLK6 are also programmed to function the same as SSCLK[1:4] or a buffered copy of the input reference (REFOUT) or they are programmed to be a control pin as discussed in the control pins section. To use the 2.5V output drive option on SSCLK[1:4], VDDL must be connected to a 2.5V power supply (SSCLK[1:4] outputs are powered by VDDL). When using the 2.5V output drive option, the maximum output frequency on SSCLK[1:4] is 166 MHz. Spread Percentage (SSCLK1 through SSCLK6 Outputs) The SSCLK frequency is programmed at any percentage value from ±0.25% to ±2.5% for center spread and from –0.5% to –5.0% down spread. Frequency Modulation The frequency modulation is programmed at 31.5 kHz for all SSCLK frequencies from 3 to 200 MHz. Contact the factory if a higher modulation frequency is required. Page 4 of 12 [+] Feedback CY25200 Table 4. Using Clock Select, CLKSEL Control Pin Input Frequency (MHz) CLKSEL (Pin 4) SSCLK1 (Pin 7) SSCLK2 (Pin 8) SSCLK3 (Pin 9) SSCLK4 (Pin 12) REFOUT (Pin 14) REFOUT (Pin 15) 14.318 CLKSEL = 0 33.33 33.33 33.33 33.33 14.318 14.318 CLKSEL = 1 66.66 66.66 66.66 66.66 14.318 14.318 Figure 3. Using Clock Select, CLKSEL Control Pin Configuration Pinout Document #: 38-07633 Rev. *D 14.318MHz VDD 1 16 XOUT 2 15 REFOUT(14.318MHz) AVDD 3 14 REFOUT(14.318MHz) CLKSEL 4 13 VSS AVSS 5 12 33.33/66.66MHz VSSL 6 11 VDDL 33.33/66.66MHz 7 10 SSON 33.33/66.66MHz 8 9 33.33/66.66MHz Page 5 of 12 [+] Feedback CY25200 Switching Waveforms Figure 4. Duty Cycle Timing (DC = t1A/t1B) Figure 5. Output Rise and Fall Time (SSCLK and REFCLK) VDD OUTPUT 0V Tr Tf Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3) Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4) Refer to AC Electrical Characteristics table for SR (Slew Rate) values. Figure 6. Power Down and Power Up Timing POWER DOWN VDD 0V VIH VIL tPU High Impedance SSCLK (Asynchronous) tSTP Figure 7. Output Enable and Disable Timing OUTPUT ENABLE VDD 0V VIH VIL TOE2 High Impedance SSCLK (Asynchronous ) TOE1 a Document #: 38-07633 Rev. *D Page 6 of 12 [+] Feedback CY25200 Informational Graphs The informational graphs are meant to convey the typical performance levels. No performance specifications is implied or guaranteed. Refer to the tables on 3 and 5 for device specifications. 172.5 68.5 171.5 Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= -4% 170.5 169.5 Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= -4% 68 67.5 67 66.5 168.5 167.5 166.5 Fnominal 66 Fnominal 165.5 164.5 163.5 162.5 65.5 65 64.5 64 63.5 161.5 160.5 0 159.5 0 20 169.5 169 168.5 168 167.5 167 166.5 166 165.5 165 164.5 164 163.5 163 40 60 80 100 120 Time (us) 140 160 180 20 40 60 80 100 120 Time (us) 140 160 180 200 200 67.5 Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= +/-1% Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= +/-1% 67 66.5 Fnominal 66 Fnominal 65.5 65 64.5 162.5 0 0 20 40 60 80 100 120 Time (us) Document #: 38-07633 Rev. *D 140 160 180 20 40 60 80 100 120 Time (us) 140 160 180 200 200 Page 7 of 12 [+] Feedback CY25200 Absolute Maximum Rating Junction Temperature ................................ –40°C to +125°C Supply Voltage (VDD) .......................................–0.5 to +7.0V DC Input Voltage...................................... –0.5V to VDD + 0.5 Storage Temperature (non-condensing) ..... –55°C to +125°C Data Retention at Tj = 125°C ................................> 10 years Package Power Dissipation...................................... 350 mW Static Discharge Voltage.......................................... > 2000V (per MIL-STD-883, Method 3015) Recommended Crystal Specifications Parameter Description Comments Min Typ. Max Unit FNOM Nominal Crystal Frequency Parallel resonance, fundamental mode, AT cut 8 CLNOM R1 Nominal Load Capacitance Internal load caps 6 Equivalent Series Resistance (ESR) Fundamental mode R3/R1 Ratio of Third Overtone Mode ESR to Ratio used because typical R1 values are much Fundamental Mode ESR less than the maximum specification DL Crystal Drive Level 30 MHz 30 pF 25 Ω 2 mW 3 No external series resistor assumed 0.5 Recommended Operating Conditions Parameter Description Min Typ. Max Unit VDD Operating Voltage 3.135 3.3 3.465 V VDDLHI Operating Voltage 3.135 3.3 3.465 V VDDLLO Operating Voltage 2.375 2.5 2.625 V TAC Ambient Commercial Temp 0 – 70 °C CLOAD Maximum Load Capacitance VDD/VDDL = 3.3V – – 15 pF CLOAD Maximum Load Capacitance VDDL = 2.5V – – 15 pF FSSCLK-HighVoltage SSCLK1/2/3/4/5/6 when VDD = AVDD = VDDL = 3.3 V 3 – 200 MHz FSSCLK-LowVoltage SSCLK1/2/3/4 when VDD = AVDD = 3.3.V and VDDL = 2.5V 3 – 166 MHz REFOUT REFOUT when VDD = AVDD = 3.3.V and VDDL = 3.3V or 2.5V 8 – 166 MHz fREF1 Clock Input 8 – 166 MHz fREF2 Crystal Input tPU Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Document #: 38-07633 Rev. *D 8 – 30 MHz 0.05 – 500 ms Page 8 of 12 [+] Feedback CY25200 DC Electrical Specifications Parameter[3] Name Description Min Typ. Max Unit IOH3.3 Output High Current VOH = VDD – 0.5V, VDD/VDDL = 3.3V 10 12 – mA IOL3.3 Output Low Current VOL = 0.5V, VDD/VDDL = 3.3V 10 12 – mA IOH2.5 Output High Current VOH = VDDL – 0.5V, VDDL = 2.5V 8 16 – mA IOL2.5 Output Low Current VOL = 0.5V, VDDL = 2.5V 8 16 – mA VIH Input High Voltage CMOS levels, 70% of VDD 0.7 – 1.0 VDD VIL Input Low Voltage CMOS levels, 30% of VDD 0 – 0.3 VDD IVDD[4] Supply Current AVDD/VDD Current – – 33 mA IVDDL2.5[4] Supply Current VDDL Current (VDDL = 2.625V) – – 20 mA IVDDL3.3[4] Supply Current VDDL Current (VDDL = 3.465V) – – 26 mA IDDS Power Down Current VDD = VDDL = AVDD = 3.465V – – 50 uA IOHZ IOLZ Output Leakage VDD = VDDL = AVDD = 3.465V – – 10 uA Notes 2. Rated for 10 years. 3. Not 100% tested, guaranteed by design. 4. IVDD currents specified for SSCLK1/2/3/4/5/6 = 33.33 MHz with CLKIN = 14.318 MHz and 15 pF on all the output clocks. Document #: 38-07633 Rev. *D Page 9 of 12 [+] Feedback CY25200 AC Electrical Specifications Parameter DC Description Condition Min Typ. Max Unit Output Duty Cycle SSCLK, Measured at VDD/2 45 50 55 % Output Duty Cycle REFCLK, Measured at VDD/2 Duty Cycle of CLKIN = 50%. 40 50 60 % SR1 Rising/Falling Edge Slew Rate SSCLK1/2/3/4 < 100 MHz, VDD = VDDL = 3.3V 0.6 – 2.0 V/ns SR2 Rising/Falling Edge Slew Rate SSCLK1/2/3/4 ≥ 100 MHz, VDD = VDDL = 3.3V 0.8 – 3.5 V/ns SR3 Rising/Falling Edge Slew Rate SSCLK1/2/3/4 < 100 MHz, VDD = VDDL = 2.5V 0.5 – 2.2 V/ns SR4 Rising/Falling Edge Slew Rate SSCLK1/2/3/4 ≥ 100 MHz, VDD = VDDL = 2.5V 0.6 – 3.0 V/ns SR5 Rising/Falling Edge Slew Rate SSCLK5/6 < 100 MHz, VDD = VDDL = 3.3V 0.6 – 1.9 V/ns SR6 Rising/Falling Edge Slew Rate SSCLK5/6 ≥ 100 MHz, VDD = VDDL = 3.3V 1.0 – 2.9 V/ns TCCJ1 Cycle-to-Cycle Jitter SSCLK1/2/3/4 CLKIN = SSCLK1/2/3/4 = 166MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V – – 110 ps CLKIN = SSCLK1/2/3/4 = 66.66 MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V – – 170 ps CLKIN = SSCLK1/2/3/4 = 33.33 MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V – – 140 ps CLKIN = SSCLK1/2/3/4 = 14.318MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V – – 290 CLKIN = SSCLK1/2/3/4 = 166 MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V – – 100 ps CLKIN = SSCLK1/2/3/4 = 66.66 MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V – – 120 ps CLKIN = SSCLK1/2/3/4 = 33.33 MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V – – 180 ps CLKIN = SSCLK1/2/3/4 = 14.318 MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V – – 180 CLKIN = SSCLK1/2/3/4 = 166 MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V – – 110 ps CLKIN = SSCLK1/2/3/4 = 66.66MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V – – 170 ps CLKIN = SSCLK1/2/3/4 = 33.33 MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V – – 190 ps CLKIN = SSCLK1/2/3/4 = 14.318 MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V – – 330 TCCJ2 TCCJ3 Cycle-to-Cycle Jitter SSCLK5/6=REFOUT Cycle-to-Cycle Jitter SSCLK1/2/3/4 tSTP Power Down Time (pin3 = PD#) Time from falling edge on PD# to stopped outputs (Asynchronous) – 150 300 ns TOE1 Output Disable Time (pin3 = OE) Time from falling edge on OE to stopped outputs (Asynchronous) – 150 300 ns TOE2 Output Enable Time (pin3 = OE) Time from rising edge on OE to outputs at a valid frequency (Asynchronous) – 150 300 ns FMOD Spread Spectrum Modulation SSCLK1/2/3/4/5/6 Frequency 30.0 31.5 33.0 kHz tPU1 Power Up Time, Crystal is used Time from rising edge on PD# to outputs at valid frequency (Asynchronous) – 3 5 ms tPU2 Power Up Time, Reference clock is used Time from rising edge on PD# to outputs at valid frequency (Asynchronous) – 2 3 ms tSKEW[5] Clock Skew Output to output skew between related clock outputs. Measured at VDD/2. – – 250 ps Document #: 38-07633 Rev. *D Page 10 of 12 [+] Feedback CY25200 Ordering Information Ordering Code[6] CY25200ZXC_XXXW Package Type Programming Temperature Operating Range 16-lead TSSOP (Pb Free) CY25200ZXC_XXXWT 16-lead TSSOP – Tape and Reel (Pb Free) Factory Commercial, 0 to 70°C Factory Commercial, 0 to 70°C CY25200FZXC 16-lead TSSOP (Pb Free) Field Commercial, 0 to 70°C CY25200FZXCT 16-lead TSSOP – Tape and Reel (Pb Free) Field Commercial, 0 to 70°C CY3672 FTG Development Kit N/A N/A CY3672-PRG FTG Programmer N/A N/A CY3695 CY22050F/CY22150F/CY25200F Socket Adapter N/A N/A Table 5. 16-lead TSSOP Package Characteristics Parameter θJA Name Value theta JA Unit 115 °C/W Package Drawing and Dimensions Figure 8. 16-lead TSSOP 4.40 MM Body Z16.173 PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. 1 MAX. REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] PACKAGE WEIGHT 0.05gms 4.30[0.169] 4.50[0.177] 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091-*A Notes 5. Skew and phase alignment is guaranteed within all SSCLK outputs and within both REFOUT outputs. SSCLK and REFOUT outputs are not phase aligned to each other. 6. “XXX” denotes the assigned product dash number. “W” denotes the different revisions of the product. Document #: 38-07633 Rev. *D Page 11 of 12 [+] Feedback CY25200 Document History Page Document Title: CY25200 Programmable Spread Spectrum Clock Generator for EMI Reduction Document Number: 38-07633 REV. ECN NO. Issue Date Orig. of Change ** 204243 See ECN RGL Description of Change New data sheet *A 220043 See ECN RGL Minor Change: Corrected letter assignment in the ordering info for Pb Free. *B 267832 See ECN RGL Added Field Programmable Devices and Functionality *C 291094 See ECN RGL Added tSKEW spec. and footnote *D 1821908 See ECN DPF/AESA Corrected FSSCLK-Low Voltage specification on page 7 for SSCLK5/6 to SSCLK1/2/3/4, as SSCLK5/6 output does not operate at low voltage. Deleted Tccj4 on page 8 for the same reason as above © Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07633 Rev. *D Revised December 11, 2007 Page 12 of 12 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback