CY29350 2.5V or 3.3V, 200-MHz, 9-Output Clock Driver Features • • • • • • • • • • • • • • Functional Description Output frequency range: 25 MHz to 200 MHz Input frequency range: 6.25 MHz to 31.25 MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs ±2.5% max Output duty cycle variation Nine Clock outputs: Drive up to 18 clock lines Two reference clock inputs: Xtal or LVCMOS 150-ps max output-output skew Phase-locked loop (PLL) bypass mode Spread Aware™ Output enable/disable Pin-compatible with MPC9350 Industrial temperature range: –40°C to +85°C 32-pin 1.0mm TQFP package The CY29350 is a low-voltage high-performance 200-MHz PLL-based clock driver designed for high speed clock distribution applications. The CY29350 features Xtal and LVCMOS reference clock inputs and provides nine outputs partitioned in four banks of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4 while the other banks divide by 4 or 8 per SEL(A:D) settings, see . These dividers allow output to input ratios of 16:1, 8:1, 4:1, and 2:1. Each LVCMOS compatible output can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:18. The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 25 MHz to 200 MHz. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see Table 1. When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. Pin Configuration Block Diagram PLL_EN TCLK VSS QA VDDQB QB VSS 29 28 27 26 25 15 16 VDDQD QD2 QD0 14 ÷4 / ÷8 QD3 QC1 SELC 13 QC0 C Y 29350 VSS ÷4 / ÷8 24 23 22 21 20 19 18 17 12 FB_SEL SELB 1 2 3 4 5 6 7 8 QD4 ÷16 / ÷32 AVDD FB _S E L S E LA S E LB SE LC SE LD A V SS XO U T 30 QB 11 ÷4 / ÷8 REF_SEL QA VDD LPF ÷2 / ÷4 9 VCO 200 500MHz 10 Phase Detector XIN OSC OE# XIN XOUT 31 REF_SEL TCLK 32 SELA PLL_EN QC0 VD D Q C QC1 VS S QD0 VD D Q D QD1 VS S QD1 SELD QD2 QD3 QD4 OE# Cypress Semiconductor Corporation Document #: 38-07474 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised July 26, 2004 CY29350 Pin Definitions[1] Pin Name I/O Type Description 8 XOUT O Analog Oscillator Output. Connect to a crystal. 9 XIN I Analog Oscillator Input. Connect to a crystal. 30 TCLK I, PD LVCMOS LVCMOS/LVTTL reference clock input 28 QA O LVCMOS Clock output bank A 26 QB O LVCMOS Clock output bank B 22, 24 QC(1:0) O LVCMOS Clock output bank C 12, 14, 16, 18, 20 QD(4:0) O LVCMOS Clock output bank D 2 FB_SEL I, PD LVCMOS Internal Feedback Select Input. See Table 1. 10 OE# I, PD LVCMOS Output enable/disable input. See Table 2. 31 PLL_EN I, PU LVCMOS PLL enable/disable input. See Table 2. 32 REF_SEL I, PD LVCMOS Reference select input. See Table 2. 3, 4, 5, 6 SEL(A:D) I, PD LVCMOS Frequency select input, Bank (A:D). See Table 2. 27 VDDQB Supply VDD 2.5V or 3.3V Power supply for bank B output clock[2,3] 23 VDDQC Supply VDD 2.5V or 3.3V Power supply for bank C output clocks[2,3] 15, 19 VDDQD Supply VDD 2.5V or 3.3V Power supply for bank D output clocks[2,3] 1 AVDD Supply VDD 2.5V or 3.3V Power supply for PLL[2,3] 11 VDD Supply VDD 2.5V or 3.3V Power supply for core, inputs, and bank A output clock[2,3] 7 AVSS Supply Ground Analog ground 13, 17, 21, 25, 29 VSS Supply Ground Common ground Table 1. Frequency Table VCO Input Frequency Range (AVDD = 3.3V) Input Frequency Range (AVDD = 2.5V) FB_SEL Feedback Divider 0 ÷32 Input Clock * 32 6.25 MHz to 15.625 MHz 6.25 MHz to 11.875 MHz 1 ÷16 Input Clock * 16 12.5 MHz to 31.25 MHz 12.5 MHz to 23.75 MHz Table 2. Function Table Control Default 0 1 REF_SEL 0 Xtal TCLK PLL_EN 1 Bypass mode, PLL disabled. The input clock connects to the output dividers PLL enabled. The VCO output connects to the output dividers OE# 0 Outputs enabled Outputs disabled (three-state) FB_SEL 0 SELA 0 Feedback divider ÷ 32 ÷ 2 (Bank A) Feedback divider ÷ 16 ÷ 4 (Bank A ) SELB 0 ÷ 4 (Bank B) ÷ 8 (Bank B) SELC 0 ÷ 4 (Bank C) ÷ 8 (Bank C) SELD 0 ÷ 4 (Bank D) ÷ 8 (Bank D) Notes: 1. PU = Internal pull-up, PD = Internal pull-down. 2. A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their high frequency filtering characteristics will be cancelled by the lead inductance of the traces. 3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output power supply pins. Document #: 38-07474 Rev. *A Page 2 of 7 CY29350 Absolute Maximum Conditions Parameter VDD VDD VIN VOUT VTT LU RPS TS TA TJ ØJC ØJA ESDH FIT Description DC Supply Voltage DC Operating Voltage DC Input Voltage DC Output Voltage Output termination Voltage Latch Up Immunity Power Supply Ripple Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Failure in Time Condition Min. –0.3 2.375 –0.3 –0.3 Functional Relative to VSS Relative to VSS Functional Ripple Frequency < 100 kHz Non-functional Functional Functional Functional Functional Max. 5.5 3.465 VDD + 0.3 VDD + 0.3 VDD ÷ 2 200 150 +150 +85 +150 42 105 –65 –40 2000 Manufacturing test 10 Unit V V V V V mA mVp-p °C °C °C °C/W °C/W Volts ppm DC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C) Parameter VIL VIH VOL VOH IIL IIH IDDA IDDQ IDD Description Input Voltage, Low Input Voltage, High Output Voltage, Low[4] Output Voltage, High[4] Input Current, Low[5] Input Current, High[5] PLL Supply Current Quiescent Supply Current Dynamic Supply Current CIN ZOUT Input Pin Capacitance Output Impedance Condition LVCMOS LVCMOS IOL = 15mA IOH = –15mA VIL = VSS VIL = VDD AVDD only All VDD pins except AVDD Outputs loaded @ 100 MHz Outputs loaded @ 200 MHz Min. – 1.7 – 1.8 – – – – – – – 14 Typ. – – – – – – 5 – 180 210 4 18 Max. 0.7 VDD+0.3 0.6 – –100 100 10 7 – – – 22 Unit V V V V µA µA mA mA mA Min. – 2.0 – – 2.4 –– – – – – – – 12 Typ. – – – – – – – 5 – 270 300 4 15 Max. 0.8 VDD+0.3 0.55 0.30 – –100 100 10 7 – – – 18 Unit V V V pF Ω DC Electrical Specifications (VDD= 3.3V ± 5%, TA = –40°C to +85°C) Parameter VIL VIH VOL Description Input Voltage, Low Input Voltage, High Output Voltage, Low[4] VOH IIL IIH IDDA IDDQ IDD Output Voltage, High[4] Input Current, Low[5] Input Current, High[5] PLL Supply Current Quiescent Supply Current Dynamic Supply Current CIN ZOUT Input Pin Capacitance Output Impedance Condition LVCMOS LVCMOS IOL = 24 mA IOL = 12 mA IOH = –24 mA VIL = VSS VIL = VDD AVDD only All VDD pins except AVDD Outputs loaded @ 100 MHz Outputs loaded @ 200 MHz V µA µA mA mA mA pF Ω Notes: 4. Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50Ω series terminated transmission lines. 5. Inputs have pull-up or pull-down resistors that affect the input current. Document #: 38-07474 Rev. *A Page 3 of 7 CY29350 AC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C) [6] Parameter Description fVCO VCO Frequency fin Input Frequency Condition Min. Typ. Max. Unit 200 – 380 MHz ÷16 Feedback 12.5 – 23.75 MHz ÷32 Feedback 6.25 – 11.87 0 – 200 Bypass mode (PLL_EN = 0) fXTAL Crystal Oscillator Frequency 10 – 23.75 MHz frefDC Input Duty Cycle 25 – 75 % tr , tf TCLK Input Rise/FallTime 0.7V to 1.7V – – 1.0 ns fMAX Maximum Output Frequency ÷2 Output 100 – 190 MHz ÷4 Output 50 – 95 ÷8 Output 25 – 47.5 DC Output Duty Cycle fMAX < 100 MHz 47.5 – 52.5 fMAX > 100 MHz 45 – 55 0.6V to 1.8V 0.1 – 1.0 ns – – 150 ps % tr , tf Output Rise/Fall times tsk(O) Output-to-Output Skew tPLZ, HZ Output Disable Time – – 10 ns tPZL, ZH Output Enable Time – – 10 ns BW PLL Closed Loop Bandwidth (-3dB) ÷16 Feedback – 0.7 - 0.9 – MHz ÷32 Feedback – 0.6 - 0.8 – Same frequency – – 150 Multiple frequencies – – 250 tJIT(CC) tJIT(PER) tLOCK Cycle-to-Cycle Jitter Period Jitter ps Same frequency – – 100 Multiple frequencies – – 175 – – 1 ms Min. Typ. Max. Unit Maximum PLL Lock Time ps AC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C) [6] Parameter Description fVCO VCO Frequency fin Input Frequency Condition 200 – 500 MHz ÷16 Feedback 12.5 – 31.25 MHz ÷32 Feedback 6.25 – 15.625 0 – 200 10 – 25 Bypass mode (PLL_EN = 0) fXTAL Crystal Oscillator Frequency frefDC Input Duty Cycle tr , tf TCLK Input Rise/FallTime 0.8V to 2.0V fMAX Maximum Output Frequency ÷2 Output MHz 25 – 75 % – – 1.0 ns 100 – 200 MHz ÷4 Output 50 – 125 ÷8 Output 25 – 62.5 47.5 – 52.5 DC Output Duty Cycle fMAX < 100 MHz fMAX > 100 MHz 45 – 55 tr , tf Output Rise/Fall times 0.8V to 2.4V 0.1 – 1.0 tsk(O) Output-to-Output Skew Banks at same voltage – – 150 ps tsk(B) Bank-to-Bank Skew Banks at different voltages – – 350 ps tPLZ, HZ Output Disable Time – – 10 ns tPZL, ZH Output Enable Time – – 10 ns % ns Note: 6. AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested. Document #: 38-07474 Rev. *A Page 4 of 7 CY29350 AC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C)(continued)[6] Parameter Description Condition Min. Typ. Max. Unit – 0.7 – 0.9 – MHz ÷32 Feedback – 0.6 – 0.8 – Same frequency – – 150 BW PLL Closed Loop Bandwidth (–3dB) ÷16 Feedback tJIT(CC) Cycle-to-Cycle Jitter Multiple frequencies – – 250 tJIT(PER) Period Jitter Same frequency – – 100 Multiple frequencies – – 150 tLOCK Maximum PLL Lock Time – – 1 Zo = 50 ohm Pulse Generator Z = 50 ohm ps ps ms Zo = 50 ohm R T = 50 ohm R T = 50 ohm VTT VTT Figure 1. AC Test Reference for VDD = 3.3V / 2.5V VDD VDD/2 tP GND T0 DC = tP / T0 x 100% Figure 2. Output Duty Cycle (DC) VDD VDD/2 GND VDD VDD/2 tSK(O) GND Figure 3. Output-to-Output Skew , tsk(O) Table 3. Suggested Oscillator Crystal Parameters Characteristic Symbol Conditions Frequency Tolerance TC Frequency Temperature Stability TS (TA –10 +60C) Aging TA First three years @ 25C CL Crystal’s rated load Load Capacitance Effective Series Resistance RESR Min Typ Max Units – – ±100 PPM – – ±00 PPM – – 5 PPM/yr – 20 – pF – 40 80 Ω Ordering Information Part Number Package Type Product Flow CY29350AI 32-pin TQFP Industrial, –40°C to +85°C CY29350AIT 32-pin TQFP – Tape and Reel Industrial, –40°C to 85°C Document #: 38-07474 Rev. *A Page 5 of 7 CY29350 Package Drawing and Dimension 32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32 51-85063-*B Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07474 Rev. *A Page 6 of 7 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY29350 Document History Page Document Title:CY29350 2.5V or 3.3V, 200-MHz, 9-Output Clock Driver Document Number: 38-07474 Issue Date Orig. of Change 128104 07/07/03 RGL New Data Sheet 245393 See ECN RGL Re-worded Select Function Descriptions in table 2. Rev. ECN No. ** *A Document #: 38-07474 Rev. *A Description of Change Page 7 of 7