CY2V9950 2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer Features 2.5V or 3.3V operation Split output bank power supplies Output frequency range: 6 MHz to 200 MHz Output-output skew < 150 ps Cycle-cycle jitter < 100 ps Selectable positive or negative edge synchronization Selectable phase-locked loop (PLL) frequency range 8 LVTTL outputs driving 50Ω terminated lines LVCMOS/LVTTL Over-voltage tolerant reference input 2x, 4x multiply and (1/2)x, (1/4)x divide ratios Spread-Spectrum-compatible Pin-compatible with IDT5V9950 and IDT5T9950 Industrial temperature range: –40°C to +85°C 32-pin TQFP package The user can program the output banks through 3F[0:1] and 4F[0:1]pins. Any one of the outputs can be connected to feedback input to achieve different reference frequency multiplication and divide ratios and zero input-output delay. The device also features split output bank power supplies which enable the user to run two banks (1Qn and 2Qn) at a power supply level different from that of the other two banks (3Qn and 4Qn). Additionally, the PE pin controls the synchronization of the output signals to either the rising or the falling edge of the reference clock. Pin Configuration Block Diagram PLL 3F1 2Q 1 2F0 2F1 21 20 VDDQ1 1Q0 4Q1 4Q0 VSS 6 7 19 18 1Q1 8 17 VSS /K CY2V9950 sOE# VSS VSS 9 10 11 12 13 14 15 16 3Q 0 3 3Q 1 4Q 0 3 3 TEST 4 5 VDDQ 3 4F1:0 REF PE VDDQ4 2Q1 2Q0 2Q 0 2F1:0 1F0 VDD 1Q 1 1F1 23 22 FB 1F1:0 24 4F0 4F1 1 2 3 VDDQ3 1Q 0 3 VSS 32 31 30 29 28 27 26 25 FB 3F1:0 VDD 3 FS 3 FS VDDQ 1 3Q0 PE 3F0 TEST R EF The CY2V9950 is a low-voltage, low-power, eight-output, 200-MHz clock driver. It features functions necessary to optimize the timing of high performance computer and communication systems. 3Q1 • • • • • • • • • • • • • • Functional Description /M 4Q 1 VDDQ 4 sO E# Cypress Semiconductor Corporation Document #: 38-07436 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised August 11, 2004 CY2V9950 Pin Definitions Pin 29 13 27 Name REF FB TEST 22 sOE# I/O[1] Type I LVTTL/LVCMOS I LVTTL 3-Level I 2-Level I, PD 4 PE 24, 23, 26, 25, 1, 32, 3, 2 31 19, 20, 15, 16,10,11, 6, 7 21 nF[1:0] VDDQ1[2] 12 VDDQ3[2] 5 VDDQ4[2] 14,30 VDD[2] 8, 9, 17, 18, 28 VSS I, PU I FS nQ[1:0] I O PWR PWR PWR PWR PWR LVTTL 3-Level Description Reference Clock Input. Feedback Input. When MID or HIGH, disables PLL (except for conditions of note 3). REF goes to all outputs. Set LOW for normal operation. Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE = H or M) – 2Q0 and 2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE# is high, the nF[1:0] pins act as output disable controls for individual banks when nF[1:0] = LL. Set sOE# LOW for normal operation. Selects Positive or Negative Edge Control and High or Low output drive strength. When LOW / HIGH the outputs are synchronized with the negative/positive edge of the reference clock. Please see Table 5. Select frequency of the outputs. Please see Tables 1 and 2. 3-Level LVTTL Selects VCO operating frequency range. Please see Table 4. Four banks of two outputs. Please see Tables 1 and 2 for frequency settings. Power Power supply for Bank 1 and Bank 2 output buffers. Please see Table 6 for supply level constraints Power supply for Bank 3 output buffers. Please see Table 6 for supply level constraints Power supply for Bank 4 output buffers. Please see Table 6 for supply level constraints Power supply for internal circuitry. Please see Table 6 for supply level constraints Ground. Power Power Power Power Device Configuration The outputs of the CY2V9950 can be configured to run at frequencies ranging from 6 to 200 MHz. Banks 3 and 4 output dividers are controlled by 3F[1:0] and 4F[1:0] as indicated in Table 1 and 2 respectively. Table 1. Output Divider Settings – Bank 3 3F[1:0] LL[4] HH Other K – Bank3 Output Divider 2 4 1 Table 2. Output Divider Settings – Bank 4 4F[1:0] LL[4] HH Other M – Bank4 Output Divider 2 Inverted[5] 1 The divider settings, output frequencies, and possible configurations of connecting FB to ANY output are summarized in Table 3. Table 3. Output Frequency Settings Configuration Output Frequency 1Q, 2Q [6] 3Q 1Qn, 2Qn FREF (1/K) x FREF (1/M) x FREF 3Qn K x FREF FREF (K/M) x FREF 4Qn M x FREF (M/K) x FREF FREF FB to 4Q The 3-level FS control pin setting determines the nominal operating frequency range of the divide-by-one outputs of the device. The CY2V9950 PLL operating frequency range that corresponds to each FS level is given in Table 4. Notes: 1. ‘PD’ indicates an internal pull-down and ‘PU’ indicates an internal pull-up. ‘3’ indicates a three-level input buffer. 2. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces. 3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. The 1F[0:1] and 2F[0:1] pins should be either tied to mid-level or left floating (on-chip resistors will bias to mid-level) during normal operation. 4. LL disables outputs if TEST = MID and sOE# = HIGH. 5. When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE = HIGH, sOE# disables them LOW when PE = LOW. 6. These outputs are undivided copies of the VCO clock. Therefore, the formulas in this column can be used to calculate the VCO operating frequency at a given reference frequency (FREF) and divider and feedback configurations. The user must select a configuration and a reference frequency that will generate a VCO frequency that is within the range specified by FS pin. Refer to Table 4. Document #: 38-07436 Rev. *A Page 2 of 9 CY2V9950 Table 4. Frequency Range Select Table 6. Power Supply Constraints FS PLL Frequency Range VDD VDDQ1[7] VDDQ3[7] VDDQ4[7] L 24 to 50 MHz 3.3V 3.3V or 2.5V 3.3V or 2.5V 3.3V or 2.5V M 48 to 100 MHz 2.5V 2.5V 2.5V 2.5V H 96 to 200 MHz Governing Agencies The PE pin determines whether the outputs synchronize to the rising edge or the falling edge of the reference signal, as indicated in Table 5. The following agencies provide specifications that apply to the CY2V9950. The agency name and relevant specification is listed below. Table 5. PE Settings PE Synchronization L Negative H Positive Agency Name JEDEC Specification JESD 51 (Theta JA) JESD 65 (Skew, Jitter) IEEE The CY2V9950 features split power supply buses for Banks 1 and 2, Bank 3 and Bank 4, which enables the user to obtain both 3.3V and 2.5V output signals from one device. The core power supply (VDD) must be set a level which is equal or higher than that on any one of the output power supplies. UL-194_V0 MIL 1596.3 (Jiter Specs) 94 (Moisture Grading) 883E Method 1012.1 (Therma Theta JC) Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD Operating Voltage Functional @ 2.5V ± 5% 2.25 2.75 V VDD Operating Voltage Functional @ 3.3V ± 10% 2.97 3.63 V VIN(MIN) Input Voltage Relative to VSS VSS – 0.3 – V VIN(MAX) Input Voltage Relative to VDD – VDD + 0.3 V TS Temperature, Storage Non Functional –65 +150 °C TA Temperature, Operating Ambient Functional –40 +85 °C TJ Temperature, Junction Functional – 155 °C ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V ØJC Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 42 °C/W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) 105 °C/W UL-94 Flammability Rating @1/8 in. MSL Moisture Sensitivity Level FIT Failure in Time V–0 1 Manufacturing Testing 10 ppm DC Electrical Specifications @ 2.5V Parameter Description Conditions VDD 2.5 Operating Voltage 2.5V ± 5% VIL Input LOW Voltage REF, FB, PE, and sOE# Inputs VIH Input HIGH Voltage VIHH[8] VIMM[8] Input HIGH Voltage VILL[8] Input LOW Voltage IIL Input Leakage Current Input MID Voltage 3-Level Inputs (TEST, FS, nF[1:0]) (These pins are normally wired to VDD,GND or unconnected) VIN = VDD/GND,VDD = Max (REF, PE, and FB inputs) Min. Max. Unit 2.375 2.625 V – 0.7 V 1.7 – V VDD – –0.4 – V VDD/2–0.2 VDD/2 + 0.2 V – 0.4 V –5 5 µA Notes: 7. VDDQ1/3/4 must not be set at a level higher than that of VDD. They can be set at different levels from each other, e.g., VDD = 3.3V, VDDQ1 = 3.3V, VDDQ3 = 2.5V and VDDQ4 = 2.5V. 8. These Inputs are normally wired to VDD, GND or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. Document #: 38-07436 Rev. *A Page 3 of 9 CY2V9950 DC Electrical Specifications @ 2.5V (continued) I3 3-Level Input DC Current HIGH, VIN = VDD MID, VIN = VDD/2 LOW, VIN = VSS 3-Level Inputs (TEST, FS, nF[1:0]) IPU Input Pull-up Current VIN = VSS, VDD = Max IPD Input Pull-down Current VIN = VDD, VDD = Max, (sOE#) VOL Output LOW Voltage IOL = 12 mA (nQ[0:1]) VOH Output HIGH Voltage IOH = –12 mA (nQ[0:1]) IDDQ Quiescent Supply Current VDD = Max, TEST = MID, REF = LOW, sOE# = LOW, Outputs not loaded IDD Dynamic Supply Current @100 MHz CIN Input Pin Capacitance – 200 µA –50 50 µA –200 – µA –25 – µA – 100 µA – 0.4 V 2.0 – V – 2 mA 150 mA 4 pF DC Electrical Specifications @ 3.3V Parameter Description Condition VDD 3.3 Operating Voltage 3.3V ± 10% VIL Input LOW Voltage REF, FB, PE, and sOE# Inputs VIH Input HIGH Voltage VIHH[8] Input HIGH Voltage VIMM[8] Input MID Voltage VILL[8] Input LOW Voltage IIL Input Leakage Current VIN = VDD/GND,VDD = Max (REF, PE, and FB inputs) I3 3-Level Input DC Current HIGH, VIN = VDD 3-Level Inputs (TEST, FS, nF[1:0]) (These pins are normally wired to VDD,GND or unconected) MID, VIN = VDD/2 LOW, VIN = VSS 3-Level Inputs (TEST, FS, nF[1:0]) VIN = VSS, VDD = Max Min. Max. Unit 2.97 3.63 V – 0.8 V 2.0 – V VDD – –0.6 – V VDD/2 – 0.3 VDD/2 + 0.3 V – 0.6 V –5 5 µA – 200 µA –50 50 µA –200 – µA –100 – µA IPU Input Pull-Up Current IPD Input Pull-Down Current VIN = VDD, VDD = Max, (sOE#) – 100 µA VOL Output LOW Voltage IOL = 12 mA, (nQ[0:1]) – 0.4 V VOH Output HIGH Voltage IOH = –12 mA, (nQ[0:1]) 2.4 – V IDDQ Quiescent Supply Current VDD = Max, TEST = MID, REF = LOW, sOE# = LOW, outputs not loaded – 2 mA IDD Dynamic Supply Current @100 MHz CIN Input Pin Capacitance 230 mA 4 pF AC Input Specifications Parameter Description Condition Min. Max. Unit TR,TF Input Rise/Fall Time 0.8V – 2.0V – 10 ns/V TPWC Input Clock Pulse HIGH or LOW 2 – ns TDCIN Input Duty Cycle % FREF Reference Input Frequency Document #: 38-07436 Rev. *A 10 90 FS = LOW 6 50 FS = MID 12 100 FS = HIGH 24 200 MHz Page 4 of 9 CY2V9950 Switching Characteristics Parameter Description Min. Max. Unit 6 200 MHz VCO Lock Range 200 400 MHz VCO Loop Bandwidth 0.25 3.5 MHz Skew between the earliest and the latest output transitions within the same bank – 150 ps Skew between the earliest and the latest output transitions among all outputs – 200 ps tSKEW1 Skew between the earliest and the latest output transitions among all same class outputs – 200 ps tSKEW2 Skew between the nominal output rising edge to the inverted output falling edge – 500 ps tSKEW3 Skew between non-inverted outputs running at different frequencies – 500 ps tSKEW4 Skew between nominal to inverted outputs running at different frequencies – 500 ps tSKEW5 Skew between nominal outputs at different power supply levels – 650 ps Skew between the outputs of any two devices under identical settings and conditions (VDDQ, VDD, temp, air flow, frequency, etc.) – 750 ps –250 +250 ps FOR Output frequency range VCOLR VCOLBW tSKEWPR Matched-Pair Skew[9] tSKEW0 Output-Output Skew[9] Condition tPART Part-Part Skew tPD0 Ref to FB Propagation Delay[10] tODCV Output Duty Cycle Measured at VDD/2 45 55 % tPWH Output High Time Deviation from 50% Measured at 2.0V for VDD = 3.3V and at 1.7V for VDD = 2.5V. – 1.5 ns tPWL Output Low Time Deviation from 50% Measured at 0.8V for VDD = 3.3V and at 0.7V for VDD = 2.5V. – 2.0 ns tR/tF Output Rise/Fall Time Measured at 0.8V – 2.0V for VDD = 3.3V and 0.7V – 1.7V for VDD = 2.5V 0.15 1.5 ns tLOCK PLL lock time[11,12] – 0.5 ms tCCJ Cycle-Cycle Jitter Divide by 1 output frequency, FS = L, FB = divide by 1, 2, 4 – 100 ps Divide by 1 output frequency, FS = M/H, FB = divide by 1, 2, 4 – 150 ps Notes: 9. Test Load = 20 pF, terminated to VCC/2. All outputs are equally loaded. 10. tPD is measured at 1.5V for VDD = 3.3V and at 1.25V for VDD = 2.5V with REF rise/fall times of 0.5ns between 0.8V–2.0V. 11. tLOCK is the time that is required before outputs synchronize to REF. This specification is valid with stable power supplies which are within normal operating limits. 12. Lock detector circuit may be unreliable for input frequencies lower than 4MHz, or for input signals which contain significant jitter. Document #: 38-07436 Rev. *A Page 5 of 9 CY2V9950 AC Timing Definitions tREF tPWL tPWH REF tPD t0DCV t0DCV FB tCCJ1-12 Q tSKEWPR tSKEW0,1 tSKEWPR tSKEW0,1 OTHER Q tSKEW1 tSKEW1 INVERTED Q tSKEW3 tSKEW3 tSKEW3 REF DIVIDED BY 2 tSKEW1,3,4 tSKEW1,3,4 REF DIVIDED BY 4 Document #: 38-07436 Rev. *A Page 6 of 9 CY2V9950 AC Test Loads and Waveforms VDDQ Output 150Ω 20pF Output 20pF 150Ω For Lock Output For All Other Outputs Figure 1. tORISE tORISE tOFALL tPWH 2.0V tOFALL tPWH 1.7V VTH =1.25V VTH =1.5V tPWL 0.8V tPWL 0.7V 2.5V LVTTL OUTPUT WAVEFORM 3.3V LVTTL OUTPUT WAVEFORM Figure 2. LVTTL Output Test Waveforms ≤ 1ns ≤ 1ns ≤ 1ns ≤ 1ns 2.5V 3.0V 1.7V 2.0V VTH =1.25V VTH =1.5V 0.7V 0V 0.8V 0V 2.5V LVTTL INPUT TEST WAVEFORM 3.3V LVTTL INPUT TEST WAVEFORM Figure 3. LVTTL Input Test Waveforms Ordering Information Part Number Package Type Product Flow CY2V9950AC 32 TQFP Commercial, 0° to 70°C CY2V9950ACT 32 TQFP – Tape and Reel Commercial, 0° to 70°C CY2V9950AI 32 TQFP Industrial, –40° to 85°C CY2V9950AIT 32 TQFP – Tape and Reel Industrial, –40° to 85°C Document #: 38-07436 Rev. *A Page 7 of 9 CY2V9950 Package Drawing and Dimensions 32-lead Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32 51-85063-B All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07436 Rev. *A Page 8 of 9 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY2V9950 Document History Page Document Title:CY2V9950 2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer Document Number: 38-07436 Issue Date Orig. of Change REV. ECN No. ** 122628 01/10/03 RGL *A 252355 See ECN RGL/GGK Document #: 38-07436 Rev. *A Description of Change New Data Sheet Fixed Note 3 definition. Page 9 of 9