NCP1586 Low Voltage Synchronous Buck Controller The NCP1586 is a low cost PWM controller designed to operate from a 5 V or 12 V supply. This device is capable of producing an output voltage as low as 0.8 V. This 8−pin device provides an optimal level of integration to reduce size and cost of the power supply. The NCP1586 provides a 1 A gate driver design and an internally set 275 kHz oscillator. In addition to the 1 A gate drive capability, other efficiency enhancing features of the gate driver include adaptive non−overlap circuitry. The NCP1586 also incorporates an externally compensated error amplifier and a capacitor programmable soft−start function. Protection features include programmable short circuit protection and under voltage lockout (UVLO). The NCP1586 comes in an 8−pin SOIC package. http://onsemi.com MARKING DIAGRAM 8 SOIC−8 D SUFFIX CASE 751 8 1 1 1586 = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Device Features • • • • • • • • • • • • Input Voltage Range from 4.5 to 13.2 V 275 kHz Internal Oscillator Boost Pin Operates to 26.5 V Voltage Mode PWM Control 0.8 V ±1.0 % Internal Reference Voltage Adjustable Output Voltage Capacitor Programmable Soft−start Internal 1 A Gate Drivers 80% Max Duty Cycle Input Under Voltage Lockout Programmable Current Limit This is a Pb−Free Device PIN CONNECTIONS BST 1 March, 2007 − Rev. 0 7 COMP/DIS GND 3 6 FB BG 4 5 VCC (Top View) ORDERING INFORMATION Graphics Cards Desktop Computers Servers / Networking DSP & FPGA Power Supply DC−DC Regulator Modules © Semiconductor Components Industries, LLC, 2007 8 PHASE TG 2 Applications • • • • • 1586 ALYW G Device NCP1586DR2G Package Shipping † SOIC−8 (Pb−Free) 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1 Publication Order Number: NCP1586/D NCP1586 12 V 3.3 V VCC BST FB COMP/DIS TG VOUT PHASE BG GND Figure 1. Typical Application Diagram POR UVLO 5 VCC 1 BST 2 TG 8 PHASE VOCTH FAULT FB 6 − + GM + − 0.8 V (VREF) LATCH FAULT R PWM OUT Q S + − Clock 2V + − Ramp COMP/DIS 7 + − SCP OSC VCC 4 BG Rset OSC FAULT Figure 2. Detailed Block Diagram http://onsemi.com 2 3 GND NCP1586 PIN FUNCTION DESCRIPTION Pin No. Symbol Description 1 BST Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired input voltage to this pin (cathode connected to BST pin). Connect a capacitor (CBST) between this pin and the PHASE pin. Typical values for CBST range from 0.1 mF to 1 mF. Ensure that CBST is placed near the IC. 2 TG Top gate MOSFET driver pin. Connect this pin to the gate of the top N−Channel MOSFET. 3 GND 4 BG Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N−Channel MOSFET. 5 VCC Supply rail for the internal circuitry. Operating supply range is 4.5 V to 13.2 V. Decouple with a 1 mF capacitor to GND. Ensure that this decoupling capacitor is placed near the IC. 6 FB This pin is the inverting input to the error amplifier. Use this pin in conjunction with the COMP pin to compensate the voltage−control feedback loop. Connect this pin to the output resistor divider (if used) or directly to Vout. 7 COMP/DIS Compensation Pin. This is the output of the error amplifier (EA) and the non−inverting input of the PWM comparator. Use this pin in conjunction with the FB pin to compensate the voltage−control feedback loop. The compensation capacitor also acts as a soft−start capacitor. Pull this pin low for disable. 8 PHASE Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the top MOSFET. IC ground reference. All control circuits are referenced to this pin. ABSOLUTE MAXIMUM RATINGS Pin Name Symbol VMAX VMIN Main Supply Voltage Input VCC 15 V −0.3 V Bootstrap Supply Voltage Input BST 30 V wrt/GND 15 V wrt/PHASE −0.3 V PHASE 25 V −0.7 V −5.0 V for < 50 ns High−Side Driver Output (Top Gate) TG 30 V wrt/GND 15 V wrt/PHASE −0.3 V wrt/PHASE Low−Side Driver Output (Bottom Gate) BG 15 V −0.3 V −2.0 V for < 200 ns Feedback FB 5.5 V −0.3 V COMP/DIS 5.5 V −0.3 V Switching Node (Bootstrap Supply Return) COMP/DISABLE MAXIMUM RATINGS Symbol Value Unit Thermal Resistance, Junction−to−Ambient Rating RqJA 165 °C/W Thermal Resistance, Junction−to−Case RqJC 45 °C/W NCP1586 Operating Junction Temperature Range TJ 0 to 125 °C NCP1586 Operating Ambient Temperature Range TA 0 to 70 °C Storage Temperature Range Tstg −55 to +150 °C 260 °C 1 − Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb−Free Moisture Sensitivity Level MSL Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 3 NCP1586 ELECTRICAL CHARACTERISTICS (0_C < TA < 70_C; 4.5 V < VCC < 13.2 V, 4.5 V < BST < 26.5 V, CTG = CBG = 1.0 nF (REF:NTD30N02), for min/max values unless otherwise noted.) Characteristic Conditions Min Typ Max Unit Input Voltage Range − 4.5 − 13.2 V Boost Voltage Range − 4.5 − 26.5 V Quiescent Supply Current VFB = 1.0 V, No Switching VCC = 13.2 V 0.1 − 0.9 mA Boost Quiescent Current VFB = 1.0 V, No Switching, VCC = 13.2 V 2.0 3.0 4.0 mA Supply Current Under Voltage Lockout UVLO Threshold VCC Rising Edge 3.9 4.0 4.1 V UVLO Hysteresis − 365 415 465 mV VFB Feedback Voltage, Control Loop in Regulation TA = 0 to 70°C 0.792 0.8 0.808 V Oscillator Frequency TA = 0 to 70°C 250 275 300 kHz 0.8 1.1 1.4 V Switching Regulator Ramp−Amplitude Voltage Minimum Duty Cycle 0 − − % Maximum Duty Cycle 70 75 80 % BG Minimum On Time − 500 − ns Error Amplifier (GM) Transconductance 3.0 − 4.4 mmho Open Loop DC Gain 55 70 − DB 80 80 120 120 − − mA −2.0 0 2.0 mV − 0.1 1.0 mA Output Source Current Output Sink Current VFB < 0.8 V VFB > 0.8 V Input Offset Voltage Input Bias Current Soft−Start SS Source Current VFB < 0.8 V 8.0 − 14 mA Switch Over Threshold VFB = 0.8 V − 100 − % of Vref − 1.0 − A − 1.0 − A − 1.0 − A − 1.0 − A Gate Drivers Upper Gate Source Upper Gate Sink Lower Gate Source VCC = 12 V, VTG = VBG = 2.0 V Lower Gate Sink TG Falling to BG Rising Delay VCC = 12 V, TG < 2.0 V, BG > 2.0 V − 40 90 ns BG Falling to TG Rising Delay VCC = 12 V, BG < 2.0 V, TG > 2.0 V − 40 60 ns 0.3 0.4 0.5 V − 10 − mA Enable Threshold Over−Current Protection OCSET Current Source Sourced from BG pin, before SS OC Switch−Over Threshold − 700 − mV Fixed OC Threshold − −375 − mV http://onsemi.com 4 NCP1586 TYPICAL CHARACTERIZATION CURVES (TA = 25°C unless otherwise noted) 4.0 278 ICC, SUPPLY CURRENT (mA) fSW, FREQUENCY (kHz) VCC = 12 V 277 276 VCC = 5.0 V 275 274 273 272 3.5 3.0 2.5 2.0 1.5 1.0 0 25 50 75 0 TJ, JUNCTION TEMPERATURE (°C) tSS, SOFT−START SOURCING CURRENT (mA) VREF, REFERENCE VOLTAGE (mV) 806 804 802 800 798 796 794 40 60 80 Figure 4. Quiescent Current (ICC) vs. Temperature 808 20 40 TJ, JUNCTION TEMPERATURE (°C) Figure 3. Oscillator Frequency (fSW) vs. Temperature 792 0 20 60 80 14 13 12 11 10 9 8 0 Figure 5. Reference Voltage (VREF) vs. Temperature 20 40 60 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 6. Soft−Start Sourcing Current (tSS) vs. Temperature http://onsemi.com 5 80 NCP1586 DETAILED OPERATING DESCRIPTION General 4.0V The NCP1586 is an 8−pin PWM controller intended for DC−DC conversion from 5.0 V & 12 V buses. The NCP1586 has a 1 A internal gate driver circuit designed to drive N−channel MOSFETs in a synchronous−rectifier buck topology. The output voltage of the converter can be precisely regulated down to 800 mV ±1.0% when the VFB pin is tied to VOUT. The switching frequency, is internally set to 275 kHz. A high gain operational transconductance error amplifier (OTA) is used. Vcc 1.1V Comp 0.8V Vfb 550mV BG Duty Cycle and Maximum Pulse Width Limits 50mV OCP Programming In steady state DC operation, the duty cycle will stabilize at an operating point defined by the ratio of the input to the output voltage. The NCP1586 can achieve an 80% duty cycle. There is a built in off−time which ensures that the bootstrap supply is charged every cycle. The NCP1586 can allow a 12 V to 0.8 V conversion at 275 kHz. TG Vout POR SS Normal UVLO Figure 7. Soft−Start Implementation Input Voltage Range (VCC and BST) The input voltage range for both VCC and BST is 4.5 V to 13.2 V with respect to GND and PHASE, respectively. Although BST is rated at 13.2 V with respect to PHASE, it can also tolerate 26.4 V with respect to GND. UVLO Undervoltage Lockout (UVLO) is provided to ensure that unexpected behavior does not occur when VCC is too low to support the internal rails and power the converter. For the NCP1586, the UVLO is set to ensure that the IC will start up when VCC reaches 4.0 V and shutdown when VCC drops below 3.7 V. This permits operation when converting from a 5.0 input voltage. External Enable/Disable When the Comp pin voltage falls or is pulled externally below the 400 mV threshold, it disables the PWM Logic and the gate drive outputs. In this disabled mode, the operational transconductance amplifier (EOTA) output source current is reduced and limited to the Soft−Start mode of 10 mA. Overcurrent Threshold Setting NCP1586 allows to easily program an Overcurrent Threshold ranging from 50 mV to 550 mV, simply by adding a resistor (RSET) between BG and GND. During a short period of time following VCC rising over UVLO threshold, an internal 10 mA current (IOCSET) is sourced from BG pin, determining a voltage drop across ROCSET. This voltage drop will be sampled and internally held by the device as Overcurrent Threshold. The OC setting procedure overall time length is about 6 ms. Connecting a ROCSET resistor between BG and GND, the programmed threshold will be: Normal Shutdown Behavior Normal shutdown occurs when the IC stops switching because the input supply reaches UVLO threshold. In this case, switching stops, the internal SS is discharged, and all GATE pins go low. The switch node enters a high impedance state and the output capacitors discharge through the load with no ringing on the output voltage. External Soft−Start The NCP1586 features an external soft−start function, which reduces inrush current and overshoot of the output voltage. Soft−start is achieved by using the internal current source of 10 mA (typ), which charges the external integrator capacitor of the transconductance amplifier. Figure 7 is a typical soft−start sequence. This sequence begins once VCC surpasses its UVLO threshold and OCP programming is complete. During soft−start, as the Comp Pin rises through 400 mV, the PWM Logic and gate drives are enabled. When the feedback voltage crosses 800 mV, the EOTA will be given control to switch to its higher regulation mode output current of 120 mA. I @ ROCSET IOCth + OCSET RDS(on) (eq. 1) RSET values range from 5 kW to 55 kW. In case ROCSET is not connected, the device switches the OCP threshold to a fixed 375 mV value: an internal safety clamp on BG is triggered as soon as BG voltage reaches 700 mV, enabling the 375 mV fixed threshold and ending OC setting phase. The current trip threshold tolerance is ±25 mV. The accuracy of the set point is best at the highest set point (550 mV). The accuracy will decrease as the set point decreases. http://onsemi.com 6 NCP1586 Current Limit Protection FAULT In case of a short circuit or overload, the low−side (LS) FET will conduct large currents. The controller will shut down the regulator in this situation for protection against overcurrent. The low−side RDS(on) sense is implemented at the end of each of the LS−FET turn−on duration to sense the over current trip point. While the LS driver is on, the Phase voltage is compared to the internally generated OCP trip voltage. If the phase voltage is lower than OCP trip voltage, an overcurrent condition occurs and a counter is initiated. When the counter completes, the PWM logic and both HS−FET and LS−FET are turned off. The controller will retry to see if the short circuit or overload condition is removed through the soft start cycle. The minimum turn−on time of the LS−FET is set to be 500 nS. 1 BST 2 TG 8 PHASE + − 2V + − VCC 4 BG Rset Drivers 3 FAULT The NCP1586 includes 1 A gate drivers to switch external N−channel MOSFETs. This allows the NCP1586 to address high−power as well as low−power conversion requirements. The gate drivers also include adaptive non−overlap circuitry. The non−overlap circuitry increase efficiency, which minimizes power dissipation, by minimizing the body diode conduction time. A detailed block diagram of the non−overlap and gate drive circuitry used in the chip is shown in Figure 8. GND Figure 8. Block Diagram Careful selection and layout of external components is required, to realize the full benefit of the onboard drivers. The capacitors between VCC and GND and between BST and SWN must be placed as close as possible to the IC. The current paths for the TG and BG connections must be optimized. A ground plane should be placed on the closest layer for return currents to GND in order to reduce loop area and inductance in the gate drive circuit. http://onsemi.com 7 NCP1586 PACKAGE DIMENSIONS SOIC−8 D SUFFIX CASE 751−07 ISSUE AH −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8 _ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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