NCP1582, NCP1582A, NCP1583 Low Voltage Synchronous Buck Controllers The NCP158x is a low cost PWM controller designed to operate from a 5 V or 12 V supply. This device is capable of producing an output voltage as low as 0.8 V. This 8−pin device provides an optimal level of integration to reduce size and cost of the power supply. Features include a 0.7 A gate driver and an internally set 350 kHz (NCP1582, NCP1582A) and a 300 kHz (NCP1583) oscillator. The NCP158x also incorporates an externally compensated transconductance error amplifier and a programmable soft−start function. Protection features include short circuit protection (SCP) and under voltage lockout (UVLO). The NCP158x comes in an 8−pin SOIC package. http://onsemi.com MARKING DIAGRAM 8 SOIC−8 D SUFFIX CASE 751 8 1 1 x A L Y W G Features • Input Voltage Range from 4.5 V to 13.2 V • 350 kHz (NCP1582, NCP1582A), 300 kHz (NCP1583) Internal • • • • • • • • • • Oscillator Boost Pin Operates to 30 V Voltage Mode PWM Control 0.8 V $1.5% Internal Reference Voltage Adjustable Output Voltage Programmable Soft−Start Internal 0.7 A Gate Drivers 80% Max Duty Cycle Input UVLO RDS(on) Current Sensing for Short Circuit Protection These are Pb−Free Devices = 2, 2A or 3 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Device PIN CONNECTIONS BST 1 NCP158x Series Oscillator Frequency SCP Trip Voltage NCP1582 350 kHz −350 mV NCP1582A 350 kHz −450 mV NCP1583 300 kHz −350 mV ORDERING INFORMATION BST TG VOUT PHASE GND 5 VCC (Top View) Package Shipping † NCP1582DR2G SOIC−8 (Pb−Free) 2500/Tape & Reel NCP1582ADR2G SOIC−8 (Pb−Free) 2500/Tape & Reel NCP1583DR2G SOIC−8 (Pb−Free) 2500/Tape & Reel Device COMP/DIS 6 FB BG 4 VIN FB 7 COMP/DIS GND 3 Graphics Cards Desktop Computers Servers/Networking DSP and FPGA Power Supply DC−DC Regulator Modules VCC 8 PHASE TG 2 Applications • • • • • 158x ALYW G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. BG Figure 1. Typical Application Diagram © Semiconductor Components Industries, LLC, 2006 July, 2006 − Rev. 2 1 Publication Order Number: NCP1582/D NCP1582, NCP1582A, NCP1583 12 V 3.3 V VCC BST FB COMP/DIS TG VOUT PHASE BG GND Figure 2. Typical VGA Card Application Diagram POR UVLO 5 VCC 1 BST 2 TG 8 PHASE 4 BG 3 GND SCP Trip Voltage FAULT FB 6 − + + − 0.8 V (VREF) LATCH + − SCP FAULT R PWM OUT Q S + − Clock 2V + − Ramp COMP/DIS 7 VCC 2V OSC OSC FAULT Figure 3. Detailed Block Diagram http://onsemi.com 2 NCP1582, NCP1582A, NCP1583 PIN FUNCTION DESCRIPTION Pin No. Symbol Description 1 BST Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired input voltage to this pin (cathode connected to BST pin). Connect a capacitor (CBST) between this pin and the PHASE pin. Typical values for CBST range from 0.1 mF to 1 mF. Ensure that CBST is placed near the IC. 2 TG Top gate MOSFET driver pin. Connect this pin to the gate of the top N−Channel MOSFET. 3 GND 4 BG Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N−Channel MOSFET. 5 VCC Supply rail for the internal circuitry. Operating supply range is 4.5 V to 15 V. Decouple with a 1 mF capacitor to GND. Ensure that this decoupling capacitor is placed near the IC. 6 FB This pin is the inverting input to the error amplifier. Use this pin in conjunction with the COMP pin to compensate the voltage−control feedback loop. Connect this pin to the output resistor divider (if used) or directly to Vout. 7 COMP/DIS Compensation Pin. This is the output of the error amplifier (EA) and the non−inverting input of the PWM comparator. Use this pin in conjunction with the FB pin to compensate the voltage−control feedback loop. The compensation capacitor also acts as a soft−start capacitor. Pull this pin low with an open drain transistor for disable. 8 PHASE Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the top MOSFET. IC ground reference. All control circuits are referenced to this pin. ABSOLUTE MAXIMUM RATINGS Symbol VMAX VMIN Main Supply Voltage Input Pin Name VCC 15 V −0.3 V Bootstrap Supply Voltage Input BST 30 V wrt/GND 15 V wrt/PHASE −0.3 V PHASE 24 V −0.7 V −5 V for < 50 ns High−Side Driver Output (Top Gate) TG 30 V wrt/GND 15 V wrt/PHASE −0.3 V wrt/PHASE Low−Side Driver Output (Bottom Gate) BG 15 V −0.3 V −2 V for < 200 ns Feedback FB 5.5 V −0.3 V COMP/DIS 5.5 V −0.3 V Symbol Value Unit Thermal Resistance, Junction−to−Ambient RqJA 165 °C/W Thermal Resistance, Junction−to−Case RqJC 45 °C/W Operating Junction Temperature Range TJ −40 to 150 °C Operating Ambient Temperature Range TA −40 to 85 °C Storage Temperature Range Tstg −55 to +150 °C 260 peak °C 1 − Switching Node (Bootstrap Supply Return) COMP/DISABLE MAXIMUM RATINGS Rating Lead Temperature Soldering (10 sec): Reflow (SMD styles only) (Note 1) Pb−Free Moisture Sensitivity Level MSL Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. 60−180 seconds minimum above 237°C. http://onsemi.com 3 NCP1582, NCP1582A, NCP1583 ELECTRICAL CHARACTERISTICS (0_C < TA < 70_C, −40_C < TJ < 125_C (Note 2), 4.5 V < VCC < 13.2 V, 4.5 V < BST < 26.5 V, CTG = CBG = 1.0 nF(REF:NTD30N02), for min/max values unless otherwise noted.) Characteristic Conditions Min Input Voltage Range ⎯ Boost Voltage Range ⎯ Quiescent Supply Current VFB = 1.0 V, No Switching VCC = 13.2 V − Boost Quiescent Current VFB = 1.0 V, No Switching UVLO Threshold UVLO Hysteresis Typ Max Unit 4.5 13.2 V 4.5 26.5 V 1.0 1.75 mA − 140 − mA VCC Rising Edge 3.85 4.2 V ⎯ − 0.5 V VFB Feedback Voltage, Control Loop in Regulation TA = 0 to 70°C −40 to 125°C 0.788 0.8 0.8 0.812 V Oscillator Frequency (NCP1582, NCP1582A) TA = 0 to 70°C −40 to 125°C 300 350 350 400 kHz Oscillator Frequency (NCP1583) TA = 0 to 70°C −40 to 125°C 275 300 300 325 kHz Ramp−Amplitude Voltage − 1.1 − V Minimum Duty Cycle − 0 − % 70 75 Supply Current Under Voltage Lockout Switching Regulator Maximum Duty Cycle Minimum Pulse Width Static Operating 100 Blanking Time BG Minimum On Time 80 % 150 ns 50 ns ~500 ns Error Amplifier (GM) Transconductance Open Loop DC Gain Output Source Current Output Sink Current VFB = 0.8 V VFB > 0.8 V Input Offset Voltage 55 70 80 80 120 120 −2.0 5.0 mmho − DB mA mA 0 2.0 mV Input Bias Current 0.1 1.0 mA Unity Gain Bandwidth 4.0 Mhz Soft−Start SS Source Current VFB < 0.8 V 5.0 Switch Over Threshold 10 15 mA 100 % of Vref Current Limit Trip Voltage (NCP1582, NCP1583) Vphase to ground −350 mV Trip Voltage (NCP1582A) Vphase to ground −450 mV 0.7 A 2.4 W 0.7 A Gate Drivers Upper Gate Source Upper Gate Sink Lower Gate Source Lower Gate Sink PHASE Falling to BG Rising Delay BG Falling to TG Rising Delay Vgs = 6.0 V − Vugate wrt Phase = 1.0 V Vgs = 6.0 V − Vlgate wrt GND = 1.0 V − VCC = 12 V, BG < 2.0 V, TG > 2.0 V − Enable Threshold W 2.2 VCC = 12 V, PHASE < 2.0 V, BG > 2.0 V 30 90 ns 30 60 ns 0.4 2. Specifications to −40°C are guaranteed via correlation using standard quality control (SQC), not tested in production. http://onsemi.com 4 V NCP1582, NCP1582A, NCP1583 TYPICAL OPERATING CHARACTERISTICS 4.3 ICC, SUPPLY CURRENT (mA) FSW, FREQUENCY (kHz) 380 370 VCC = 5.0 V 360 350 VCC = 12 V 340 330 320 310 −50 −25 0 25 50 75 100 4.2 4.1 4.0 3.9 3.8 3.7 −50 125 −25 812 4.4 808 4.3 804 50 75 100 125 800 796 792 788 100 125 RISING 4.2 4.1 4.0 3.9 3.8 FALLING 3.7 −25 0 25 50 75 100 3.6 −50 125 −25 TJ, JUNCTION TEMPERATURE (°C) 0 25 50 75 TJ, JUNCTION TEMPERATURE (°C) Figure 6. Reference Voltage (Vref) vs. Temperature Figure 7. UVLO vs. Temperature 500 12 I−LIMIT TRIP (mV) SOFT START SOURCING CURRENT (mA) 25 Figure 5. ICC vs. Temperature UVLO RISING/FALLING (V) Vref, REFERENCE VOLTAGE (mV) Figure 4. Oscillator Frequency (FSW) vs. Temperature 784 −50 0 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) 11 10 450 400 350 9.0 −50 −25 0 25 50 75 100 125 300 −50 TJ, JUNCTION TEMPERATURE (°C) −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) Figure 8. Soft Start Sourcing Current vs. Temperature Figure 9. I−Limit vs. Temperature http://onsemi.com 5 125 NCP1582, NCP1582A, NCP1583 DETAILED OPERATING DESCRIPTION General The NCP158x is an 8−pin PWM controller intended for DC−DC conversion from 5.0 V & 12 V buses. The NCP158x has a 0.7 A internal gate driver circuit designed to drive N−channel MOSFETs in a synchronous−rectifier buck topology. The output voltage of the converter can be precisely regulated down to 800 mV 1.5% when the VFB pin is tied to VOUT. The switching frequency is internally set. A high gain operational transconductance error amplifier (OTA) is used. 1.1 V 0.4 V 0.4 V Vcomp Enable Vfb SS 120 mA 10 mA 10 mA Duty Cycle and Maximum Pulse Width Limits Isource/ Sink In steady state DC operation, the duty cycle will stabilize at an operating point defined by the ratio of the input to the output voltage. The NCP158x can achieve an 80% duty cycle. There is a built in off−time which ensures that the bootstrap supply is charged every cycle. The NCP158x, which is capable of a 100 nsec pulse width (min.), can allow a 12 V to 0.8 V conversion at 350 kHz. −10 mA Start Up Normal Timing Diagram NCP1582: Enable Sequence Figure 10. Soft Start Implementation Input Voltage Range (VCC and BST) UVLO The input voltage range for both VCC and BST is 4.5 V to 13.2 V with respect to GND and PHASE, respectively. Although BST is rated at 13.2 V with respect to PHASE, it can also tolerate 26.5 V with respect to GND. Under Voltage Lockout (UVLO) is provided to ensure that unexpected behavior does not occur when VCC is too low to support the internal rails and power the converter. For the NCP158x, the UVLO is set to ensure that the IC will start up when VCC reaches 4.2 V and shutdown when VCC drops below 3.7 V. This permits operation when converting from a 5.0 input voltage. External Enable/Disable When the Comp pin voltage falls or is pulled externally below the 400 mv threshold, it disables the PWM Logic and the gate drive outputs. In this disabled mode, the operational transconductance error amplifier’s (EOTA) output source current is reduced and limited to the Soft Start current of 10 mA. Current Limit Protection In case of a short circuit or overload, the low−side (LS) FET will conduct large currents. The controller will shut down the regulator in this situation for protection against overcurrent. The low−side RDSon sense is implemented by comparing the voltage at the Phase node when BG starts going low to an internally generated fixed voltage. If the phase voltage is lower than SCP trip voltage, an overcurrent condition occurs and a counter is initiated. When the counter completes, the PWM logic and both HS−FET and LS−FET are turned off. The controller will retry to see if the short circuit or overload condition is removed through the soft start cycle. The minimum turn−on time of the LS−FET is set to be 500 ns. The trip thresholds have a −95 mV, +45 mV process and temperature variation. Normal Shutdown Behavior Normal shutdown occurs when the IC stops switching because the input supply reaches UVLO threshold. In this case, switching stops, the internal SS is discharged, and all GATE pins go low. The switch node enters a high impedance state and the output capacitors discharge through the load with no ringing on the output voltage. External Soft Start The NCP158x features an external soft start function, which reduces inrush current and overshoot of the output voltage. Soft start is achieved by using the internal current source of 10 mA. (typ), which charges the external integrator capacitor of the transconductance amplifier. Figure 10 is a typical soft start sequence. This sequence begins once VCC surpasses its UVLO threshold. During Soft Start, as the Comp Pin rises through 400 mV, the PWM Logic and gate drives are enabled. When the feedback voltage crosses 800 mV, the EOTA will be given control to switch to its higher regulation mode output current of 120 mA. In the event of an overcurrent during soft start, the overcurrent logic will override the soft start sequence and will shut down the PWM logic and both the high side and low side gates. Drivers The NCP158x includes 0.7 A gate drivers to switch external N−channel MOSFETs. This allows the NCP158x to address high−power as well as low−power conversion requirements. The gate drivers also include adaptive non−overlap circuitry. The non−overlap circuitry increase efficiency, which minimizes power dissipation, by minimizing the body diode conduction time. A detailed block diagram of the non−overlap and gate drive circuitry used in the chip is shown in Figure 11. http://onsemi.com 6 NCP1582, NCP1582A, NCP1583 BST UVLO FAULT TG PHASE + − 2V + − 2V VCC BG PWM OUT GND UVLO FAULT Figure 11. Block Diagram of Gate Driver and Non−Overlap Circuitry Careful selection and layout of external components is required, to realize the full benefit of the onboard drivers. The capacitors between VCC and GND and between BST and SWN must be placed as close as possible to the IC. The current paths for the TG and BG connections must be optimized. A ground plane should be placed on the closest layer for return currents to GND in order to reduce loop area and inductance in the gate drive circuit. http://onsemi.com 7 NCP1582, NCP1582A, NCP1583 APPLICATION SECTION Input Capacitor Selection The above calculation includes the delay from comp rising to when output voltage becomes valid. To calculate the time of output voltage rising to when it reaches regulation; DV is the difference between the comp voltage reaching regulation and 1.1 V. The input capacitor has to sustain the ripple current produced during the on time of the upper MOSFET, so it must have a low ESR to minimize the losses. The RMS value of this ripple is: IinRMS + IOUT Ǹ D (1 * D) , Output Capacitor Selection The output capacitor is a basic component for the fast response of the power supply. In fact, during load transient, for the first few microseconds it supplies the current to the load. The controller immediately recognizes the load transient and sets the duty cycle to maximum, but the current slope is limited by the inductor value. During a load step transient the output voltage initial drops due to the current variation inside the capacitor and the ESR. (neglecting the effect of the effective series inductance (ESL)): where D is the duty cycle, IinRMS is the input RMS current, & IOUT is the load current. The equation reaches its maximum value with D = 0.5. Losses in the input capacitors can be calculated with the following equation: PCIN + ESRCIN IinRMS 2, where PCIN is the power loose in the input capacitors & ESRCIN is the effective series resistance of the input capacitance. Due to large dI/dt through the input capacitors, electrolytic or ceramics should be used. If a tantalum must be used, it must be surge protected. Otherwise, capacitor failure could occur. DVOUT−ESR + DIOUT where VOUT−ESR is the voltage deviation of VOUT due to the effects of ESR and the ESRCOUT is the total effective series resistance of the output capacitors. A minimum capacitor value is required to sustain the current during the load transient without discharging it. The voltage drop due to output capacitor discharge is given by the following equation: Calculating Input Start−up Current To calculate the input start up current, the following equation can be used. Iinrush + COUT VOUT , tSS where Iinrush is the input current during start−up, COUT is the total output capacitance, VOUT is the desired output voltage, and tSS is the soft start interval. If the inrush current is higher than the steady state input current during max load, then the input fuse should be rated accordingly, if one is used. DVOUT−DISCHARGE + 2 DIOUT 2 LOUT , COUT (VIN D * VOUT) where VOUT−DISCHARGE is the voltage deviation of VOUT due to the effects of discharge, LOUT is the output inductor value & VIN is the input voltage. It should be noted that ΔVOUT−DISCHARGE and VOUT−ESR are out of phase with each other, and the larger of these two voltages will determine the maximum deviation of the output voltage (neglecting the effect of the ESL). Calculating Soft Start Time To calculate the soft start time, the following equation can be used. tSS + ESRCOUT, (CP ) CC) * DV ISS Inductor Selection Both mechanical and electrical considerations influence the selection of an output inductor. From a mechanical perspective, smaller inductor values generally correspond to smaller physical size. Since the inductor is often one of the largest components in the regulation system, a minimum inductor value is particularly important in space−constrained applications. From an electrical perspective, the maximum current slew rate through the output inductor for a buck regulator is given by: Where CC is the compensation as well as the soft start capacitor, CP is the additional capacitor that forms the second pole. ISS is the soft start current DV is the comp voltage from zero to until it reaches regulation. DV V V SlewRateLOUT + IN * OUT . LOUT 1.1 V This equation implies that larger inductor values limit the regulator’s ability to slew current through the output inductor in response to output load transients. Consequently, output capacitors must supply the load current until the inductor current reaches the output load current level. This Vcomp Vout http://onsemi.com 8 NCP1582, NCP1582A, NCP1583 results in larger values of output capacitance to maintain tight output voltage regulation. In contrast, smaller values of inductance increase the regulator’s maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current. The peak−to−peak ripple current is given by the following equation: R1 EA Gm CC VOUT(1 * D) Ipk * pkLOUT + , LOUT 350 kHz CP VREF RC where Ipk−pkLOUT is the peak to peak current of the output. From this equation it is clear that the ripple current increases as LOUT decreases, emphasizing the trade−off between dynamic response and ripple current. + R2 Figure 12. Type II Transconductance Error Amplifier Feedback and Compensation Figure 12 shows a typical Type II transconductance error amplifier (EOTA). The compensation network consists of the internal error amplifier and the impedance networks ZIN (R1, R2) and external ZFB (Rc, Cc and Cp). The compensation network has to provide a closed loop transfer function with the highest 0 dB crossing frequency to have fast response (but always lower than FSW/8) and the highest gain in DC conditions to minimize the load regulation. A stable control loop has a gain crossing with −20 dB/decade slope and a phase margin greater than 45°. Include worst−case component variations when determining phase margin. Loop stability is defined by the compensation network around the EOTA, the output capacitor, output inductor and the output divider. Figure 13. shows the open loop and closed loop gain plots. The NCP158x allows the output of the DC−DC converter to be adjusted from 0.8 V to 5.0 V via an external resistor divider network. The controller will try to maintain 0.8 V at the feedback pin. Thus, if a resistor divider circuit was placed across the feedback pin to VOUT, the controller will regulate the output voltage proportional to the resistor divider network in order to maintain 0.8 V at the FB pin. VOUT R1 FB R2 Compensation Network Frequency: The inductor and capacitor form a double pole at the frequency The relationship between the resistor divider network above and the output voltage is shown in the following equation: R2 + R1 FLC + ǒVOUTVREF Ǔ. * VREF The ESR of the output capacitor creates a “zero” at the frequency, Resistor R1 is selected based on a design tradeoff between efficiency and output voltage accuracy. For high values of R1 there is less current consumption in the feedback network, However the trade off is output voltage accuracy due to the bias current in the error amplifier. The output voltage error of this bias current can be estimated using the following equation (neglecting resistor tolerance): Error% + 0.1 mA VREF R1 1 2p @ ǸLO @ CO FESR + 1 2p @ ESR @ CO The zero of the compensation network is formed as, FZ + 1 2p @ RCCC The pole of the compensation network is calculated as, FP + 100%. Once R1 has been determined, R2 can be calculated. http://onsemi.com 9 1 2p @ RC @ CP NCP1582, NCP1582A, NCP1583 Where: QBG = total lower MOSFET gate charge at VCC. The junction temperature of the control IC can then be calculated as: GAIN (dB) Open Loop, Unloaded Gain A TJ + TA ) PIC @ qJA. Closed Loop, Unloaded Gain FZ Where: TJ = the junction temperature of the IC, TA = the ambient temperature, θJA = the junction−to−ambient thermal resistance of the IC package. The package thermal resistance can be obtained from the specifications section of this data sheet and a calculation can be made to determine the IC junction temperature. However, it should be noted that the physical layout of the board, the proximity of other heat sources such as MOSFETs and inductors, and the amount of metal connected to the IC, impact the temperature of the device. Use these calculations as a guide, but measurements should be taken in the actual application. FP Gain = GMR1 Error Amplifier B Compensation Network 100 1000 10 k 100 k 1000 k FREQUENCY (Hz) Figure 13. Gain Plot of the Error Amplifier Thermal Considerations The power dissipation of the NCP158x varies with the MOSFETs used, VCC, and the boost voltage (VBST). The average MOSFET gate current typically dominates the control IC power dissipation. The IC power dissipation is determined by the formula: Layout Considerations As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible using ground plane construction or single point grounding. The figure below shows the critical power components of the converter. To minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. The components shown in the figure below should be located as close together as possible. Please note that the capacitors CIN and COUT each represent numerous physical capacitors. It is desirable to locate the NCP158x within 1 inch of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the NCP158x must be sized to handle up to 2 A peak current. PIC + (ICC @ VCC) ) PTG ) PBG. Where: PIC = control IC power dissipation, ICC = IC measured supply current, VCC = IC supply voltage, PTG = top gate driver losses, PBG = bottom gate driver losses. The upper (switching) MOSFET gate driver losses are: PTG + QTG @ fSW @ VBST. Where: QTG = total upper MOSFET gate charge at VBST, fSW = the switching frequency, VBST = the BST pin voltage. The lower (synchronous) MOSFET gate driver losses are: PBG + QBG @ fSW @ VCC. Vin TG Lout Vout PHASE NCP1582 Cin BG Cout GND RETURN Figure 14. Components to be Considered for Layout Specifications http://onsemi.com 10 L C A D NCP1582, NCP1582A, NCP1583 Design Example Pole of the compensation network is calculated as follows; Switching Frequency FSW = 350 KHZ Output Capacitance CESR = 45 mW/Each Output Capacitance Cout = 6630 mF Output Inductance Lout = 0.75 mH Input Voltage Vin = 12 V Output Voltage Vout = 3.3 V FP + 5 * FCO + 175 kHz 1 CP + 2 * p * FP * R C + Choose the loop gain crossover frequency; The recommended compensation values are; RC = 1500, CC = 46 nF, CP = 700 pF The NCP158x bode plot as measured from the network analyzer is shown below. FCO + 1 * FSW + 35 kHz 10 The corner frequency of the output filter is calculated below; FLC + 1 + 700 pF 2 * p * 175 kHz * 1500 1 + 2.3 kHz 2 * p * Ǹ0.75 mH * 6630 mF Let RC = 1500 Check that the ESR zero frequency is not too high; FESR + F 1 t SW 5 2 * p @ CESR @ CO This condition is mandatory for loop stability. Zero of the compensation network is calculated as follows; FZ + FLC 1 CC + 2 * p * FZ * R C + Top plot: Phase−Frequency (Phase Margin = 62.519°) Bottom plot: Gain−Frequency (UGBW= 5 MHz) 1 + 46 nF 2 * p * 2.3 kHz * 1500 Figure 15. Typical Bode plot of the Open−loop Frequency Response of the NCP158x The compensation capacitor also acts as the soft start capacitor. By adjusting the value of this compensation capacitor, the soft start time can be adjusted. http://onsemi.com 11 C8 + + + + + + C1 C2 C3 C4 C5 C6 C7 1500 mF 1500 mF 1500 mF 1500 mF 22 mF 22 22 mF mF + http://onsemi.com 12 MH1 MH2 MH3 MH4 R3 1.02 k R4 OPEN 1 mF 1 CR1 BAS116LT1 3 C10 R1 402 Q1 U1 5 + 7 1 BST 0.022 + C9 TP4 C11 VCC mF R7 0.1 100 pF COMP 2 TG 1 NCP1582 mF 0.0 SWITCH_NODE 40N03 8 PHASE R6 6 FB BG 4 R2 OPEN TP8 0.0 3 GND + 1 C20 OPEN 40N03 TP3 TP2 TP1 +12_VIN 3 4 4 TP5 C21 Q2 3 OPEN OPEN 1.0 R8 mH L1 + + C13 C14 C12 1800 mF 1800 mF1800 mF + C15 1800 mF + TP6 10 mF C16 10 mF C17 10 mF C18 10 mF C19 TP9 TP7 NCP1582, NCP1582A, NCP1583 Demo Board PCB Layout NCP1582, NCP1582A, NCP1583 Bill of Materials Item Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Part Reference C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 CR1 L1 Q1 Q2 R1 R2 R3 R4 R6 R7 R8 U1 Value 1500 mF 22 mF 1.0 mF 100 pF 0.022 mF 0.1 mF 1800 mF 10 mF OPEN OPEN BAS116LT1 0.75 mH 40N03 402 OPEN 1.02 K OPEN 0 OPEN NCP158x http://onsemi.com 13 Quantity 4 3 1 1 1 1 4 4 1 1 1 1 2 1 1 1 1 2 1 1 MFG PANASONIC TDK TAIYO YUDEN AVX KEMET AVX PANASONIC KEMET − − ON SEMICONDUCTOR TOKO ON SEMICONDUCTOR DALE − DALE − DALE − ON SEMICONDUCTOR NCP1582, NCP1582A, NCP1583 TYPICAL PERFORMANCE CHARACTERISTICS Figure 16. Start Up Figure 17. Gate Waveforms 15 A Load Sustaining Figure 18. Transient Response (0−10 A Step Load) Figure 19. Transient Response EFFICIENCY (%) 92 89 86 83 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LOAD CURRENT (A) Figure 21. Efficiency vs. Load Current Figure 20. Over Current Protection (22 A DC Trip) http://onsemi.com 14 NCP1582, NCP1582A, NCP1583 PACKAGE DIMENSIONS SOIC−8 D SUFFIX CASE 751−07 ISSUE AH NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 15 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8 _ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 NCP1582, NCP1582A, NCP1583 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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