NCP1579 D

NCP1579
Low Voltage Synchronous
Buck Controller
The NCP1579 is a low cost PWM controller designed to operate
from a 5 V or 12 V supply. This device is capable of producing an
output voltage as low as 0.8 V. This 8−pin device provides an optimal
level of integration to reduce size and cost of the power supply. The
NCP1579 provides a 1 A gate driver design and an internally set
275 kHz oscillator. In addition to the 1 A gate drive capability, other
efficiency enhancing features of the gate driver include adaptive
non−overlap circuitry. The device also incorporates an externally
compensated error amplifier and a capacitor programmable soft−start
function. Protection features include programmable short circuit
protection and undervoltage lockout (UVLO). The NCP1579 comes in
an 8−pin SOIC package.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Input Voltage Range from 4.5 to 13.2 V
275 kHz Internal Oscillator
Boost Pin Operates to 30 V
Voltage Mode PWM Control
0.8 V ±2.0 % Internal Reference Voltage
Adjustable Output Voltage
Capacitor Programmable Soft−Start
Internal 1 A Gate Drivers
80% Max Duty Cycle
Input Under Voltage Lockout
Programmable Current Limit
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
•
•
•
•
•
April, 2013 − Rev. 3
MARKING DIAGRAM
8
SOIC−8
D SUFFIX
CASE 751
8
1
1579
ALYW
G
1
1579
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Device
PIN CONNECTIONS
BST 1
8 PHASE
TG 2
7 COMP/DIS
GND 3
6 FB
BG 4
5 VCC
(Top View)
ORDERING INFORMATION
STB
Blue−Ray DVD
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DC−DC Regulator Modules
© Semiconductor Components Industries, LLC, 2013
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Device
NCP1579DR2G
Package
Shipping†
SOIC−8
(Pb−Free)
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1
Publication Order Number:
NCP1579/D
NCP1579
12 V
3.3 V
VCC
BST
FB
COMP/DIS
TG
VOUT
PHASE
BG
GND
VIN
VCC
FB
COMP/DIS
BST
TG
VOUT
PHASE
GND
BG
Figure 1. Typical Application Diagrams
POR
UVLO
5
VCC
1
BST
2
TG
8
PHASE
VOCTH
FAULT
FB
6
+
LATCH
GM
+
-
0.8 V
(VREF)
SCP
FAULT
R
S
PWM
OUT
Q
+
-
Clock
2V
+
-
Ramp
COMP/DIS
7
+
-
OSC
VCC
4
OSC
FAULT
Figure 2. Detailed Block Diagram
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2
3
BG
Rset
GND
NCP1579
PIN FUNCTION DESCRIPTION
Pin No.
Symbol
Description
1
BST
Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the
desired input voltage to this pin (cathode connected to BST pin). Connect a capacitor (CBST) between this pin
and the PHASE pin. Typical values for CBST range from 0.1 mF to 1 mF. Ensure that CBST is placed near the IC.
2
TG
Top gate MOSFET driver pin. Connect this pin to the gate of the top N−Channel MOSFET.
3
GND
4
BG
Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N−Channel MOSFET.
5
VCC
Supply rail for the internal circuitry. Operating supply range is 4.5 V to 13.2 V. Decouple with a 1 mF
capacitor to GND. Ensure that this decoupling capacitor is placed near the IC.
6
FB
This pin is the inverting input to the error amplifier. Use this pin in conjunction with the COMP pin to
compensate the voltage−control feedback loop. Connect this pin to the output resistor divider (if used) or directly to Vout.
7
COMP/DIS
8
PHASE
IC ground reference. All control circuits are referenced to this pin.
Compensation Pin. This is the output of the error amplifier (EA) and the non−inverting input of the PWM comparator. Use this pin in conjunction with the FB pin to compensate the voltage−control feedback loop. The compensation capacitor also acts as a soft−start capacitor. Pull this pin low for disable.
Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the top
MOSFET.
ABSOLUTE MAXIMUM RATINGS
Pin Name
Symbol
VMAX
VMIN
Main Supply Voltage Input
VCC
15 V
−0.3 V
Bootstrap Supply Voltage Input
BST
30 V wrt/GND
15 V wrt/PHASE
35 V wrt/GND for < 50
ns
−0.3 V
PHASE
26 V
−0.7 V
−5.0 V for < 50 ns
High−Side Driver Output (Top Gate)
TG
30 V wrt/GND
15 V wrt/PHASE
−0.3 V
wrt/PHASE
Low−Side Driver Output (Bottom Gate)
BG
15 V
−0.3 V
−2.0 V for < 200 ns
Feedback
FB
5.5 V
−0.3 V
COMP/DIS
5.5 V
−0.3 V
Switching Node (Bootstrap Supply Return)
COMP/DISABLE
MAXIMUM RATINGS
Symbol
Value
Unit
Thermal Resistance, Junction−to−Ambient
Rating
RqJA
165
°C/W
Thermal Resistance, Junction−to−Case
RqJC
45
°C/W
Operating Junction Temperature Range
TJ
0 to 125
°C
Operating Ambient Temperature Range
TA
0 to 70
°C
Storage Temperature Range
Tstg
−55 to +150
°C
260
°C
Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb−Free
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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NCP1579
ELECTRICAL CHARACTERISTICS (0_C < TA < 70_C; 4.5 V < VCC < 13.2 V, 4.5 V < [BST−PHASE] < 13.2 V, 4.5 V < BST < 30 V,
0 V < PHASE < 21 V, CTG = CBG = 1.0 nF, for min/max values unless otherwise noted.)
Characteristic
Conditions
Min
Typ
Max
Unit
Input Voltage Range
−
4.5
−
13.2
V
Boost Voltage Range
−
4.5
−
26.5
V
Quiescent Supply Current
VFB = 1.0 V, No Switching, VCC = 13.2 V
1.0
−
8.0
mA
Boost Quiescent Current
VFB = 1.0 V, No Switching, VCC = 13.2 V
0.1
−
1.0
mA
UVLO Threshold
VCC Rising Edge
3.8
−
4.2
V
UVLO Hysteresis
−
300
370
440
mV
VFB Feedback Voltage,
Control Loop in Regulation
TA = 0 to 70°C
784
800
816
mV
Oscillator Frequency
TA = 0 to 70°C
233
275
317
kHz
0.8
1.1
1.4
V
Minimum Duty Cycle
0
−
−
%
Maximum Duty Cycle
70
75
80
%
Supply Current
Under Voltage Lockout
Switching Regulator
Ramp−Amplitude Voltage
Error Amplifier (GM)
Transconductance
3.0
−
4.4
mmho
Open Loop DC Gain
55
70
−
DB
80
80
120
120
−
−
mA
−
0.1
1.0
mA
Output Source Current
Output Sink Current
VFB < 0.8 V
VFB > 0.8 V
Input Bias Current
Soft−Start
SS Source Current
VFB < 0.8 V
7.0
−
14
mA
Switch Over Threshold
VFB = 0.8 V
−
100
−
% of Vref
−
1.0
−
A
−
1.0
−
A
−
1.0
−
A
−
2.0
−
A
Gate Drivers
Upper Gate Source
Upper Gate Sink
Lower Gate Source
VCC = 12 V, VTG = VBG = 2.0 V
Lower Gate Sink
TG Falling to BG Rising Delay
VCC = 12 V, TG < 2.0 V, BG > 2.0 V
−
40
90
ns
BG Falling to TG Rising Delay
VCC = 12 V, BG < 2.0 V, TG > 2.0 V
−
35
90
ns
0.3
0.4
0.5
V
−
10
−
mA
OC Switch−Over Threshold
−
700
−
mV
Fixed OC Threshold
−
−375
−
mV
Enable Threshold
Over−Current Protection
OCSET Current Source
Sourced from BG pin, before SS
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NCP1579
5.0
203
4.7
202
FSW, FREQUENCY (Khz)
ICC (mA)
TYPICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
4.4
4.1
3.8
0
10
20
30
40
50
60
VCC = 12 V
199
VCC = 5 V
198
70
0
10
20
30
40
50
60
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. ICC vs. Temperature
Figure 4. Oscillator Frequency (FSW) vs.
Temperature
14
70
375
SCP THRESHOLD (mV)
13
12
11
10
9
8
200
TJ, JUNCTION TEMPERATURE (°C)
0
10
20
30
40
50
60
365
355
345
335
325
70
0
10
20
30
40
50
60
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Soft Start Sourcing Current vs.
Temperature
Figure 6. SCP Threshold vs. Temperature
808
806
Vref, REFERENCE (mV)
SOFT START SOURCING CURRENT (mA)
3.5
201
804
802
800
798
796
794
792
0
10
20
30
40
50
60
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Reference Voltage (Vref) vs.
Temperature
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5
70
70
NCP1579
DETAILED OPERATING DESCRIPTION
General
External Enable/Disable
The NCP1579 is a PWM controller intended for DC−DC
conversion from 5.0 V & 12 V buses. The devices have a 1
A internal gate driver circuit designed to drive N−channel
MOSFETs in a synchronous−rectifier buck topology. The
output voltage of the converter can be precisely regulated
down to 800 mV ±2.0% when the VFB pin is tied to VOUT.
The switching frequency, is internally set to 275 kHz. A high
gain operational transconductance error amplifier (OTA) is
used.
When the Comp pin voltage falls or is pulled externally
below the 400 mV threshold, it disables the PWM Logic and
the gate drive outputs. In this disabled mode, the operational
transconductance amplifier (EOTA) output source current is
reduced and limited to the Soft−Start mode of 10 mA.
Normal Shutdown Behavior
Normal shutdown occurs when the IC stops switching
because the input supply reaches UVLO threshold. In this
case, switching stops, the internal SS is discharged, and all
GATE pins go low. The switch node enters a high impedance
state and the output capacitors discharge through the load
with no ringing on the output voltage.
Duty Cycle and Maximum Pulse Width Limits
In steady state DC operation, the duty cycle will stabilize
at an operating point defined by the ratio of the input to the
output voltage. The devices can achieve an 80% duty cycle.
There is a built in off−time which ensures that the bootstrap
supply is charged every cycle. Both parts can allow a 12 V
to 0.8 V conversion at 275 kHz.
External Soft−Start
The NCP1579 features an external soft−start function,
which reduces inrush current and overshoot of the output
voltage. Soft−start is achieved by using the internal current
source of 10 mA (typ), which charges the external integrator
capacitor of the transconductance amplifier. Figure 8 is a
typical soft−start sequence. This sequence begins once VCC
surpasses its UVLO threshold and OCP programming is
complete. During soft−start, as the Comp Pin rises through
400 mV, the PWM Logic and gate drives are enabled. When
the feedback voltage crosses 800 mV, the EOTA will be
given control to switch to its higher regulation mode output
current of 120 mA.
Input Voltage Range (VCC and BST)
The input voltage range for both VCC and BST is 4.5 V to
13.2 V with respect to GND and PHASE, respectively.
Although BST is rated at 13.2 V with respect to PHASE, it
can also tolerate 26.4 V with respect to GND.
4.0 V
VCC
0.85 V
Comp
0.8 V
Vfb
550 mV
BG
50 mV
OCP
Program
ming
TG
Vout
POR
UVLO
SS
NORMAL
Figure 8. Soft−Start Implementation
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NCP1579
UVLO
go through a Power On Reset (POR) cycle to reset the OCP
fault.
Undervoltage Lockout (UVLO) is provided to ensure that
unexpected behavior does not occur when VCC is too low to
support the internal rails and power the converter. For the
NCP1579, the UVLO is set to permit operation when
converting from a 5.0 input voltage.
Drivers
The NCP1579 includes gate drivers to switch external
N−channel MOSFETs. This allows the devices to address
high−power as well as low−power conversion requirements.
The gate drivers also include adaptive non−overlap
circuitry. The non−overlap circuitry increase efficiency,
which minimizes power dissipation, by minimizing the
body diode conduction time.
A detailed block diagram of the non−overlap and gate
drive circuitry used in the chip is shown in Figure 9.
Overcurrent Threshold Setting
NCP1579 can easily program an Overcurrent Threshold
ranging from 50 mV to 550 mV, simply by adding a resistor
(RSET) between BG and GND. During a short period of
time following VCC rising over UVLO threshold, an internal
10 mA current (IOCSET) is sourced from BG pin,
determining a voltage drop across ROCSET. This voltage
drop will be sampled and internally held by the device as
Overcurrent Threshold. The OC setting procedure overall
time length is about 6 ms. Connecting a ROCSET resistor
between BG and GND, the programmed threshold will be:
I
@ ROCSET
IOCth + OCSET
RDS(on)
FAULT
1
BST
2
TG
8
PHASE
(eq. 1)
RSET values range from 5 kW to 55 kW. In case ROCSET
is not connected, the device switches the OCP threshold to
a fixed 375 mV value: an internal safety clamp on BG is
triggered as soon as BG voltage reaches 700 mV, enabling
the 375 mV fixed threshold and ending OC setting phase.
The current trip threshold tolerance is ±25 mV. The accuracy
of the set point is best at the highest set point (550 mV). The
accuracy will decrease as the set point decreases.
+
2V
+
-
VCC
4
BG
Rset
Current Limit Protection
In case of a short circuit or overload, the low−side (LS)
FET will conduct large currents. The controller will shut
down the regulator in this situation for protection against
overcurrent. The low−side RDS(on) sense is implemented at
the end of each of the LS−FET turn−on duration to sense the
over current trip point. While the LS driver is on, the Phase
voltage is compared to the internally generated OCP trip
voltage. If the phase voltage is lower than OCP trip voltage,
an overcurrent condition occurs and a counter is initiated.
When the counter completes, the PWM logic and both
HS−FET and LS−FET are turned off. The controller has to
3
FAULT
GND
Figure 9. Block Diagram
Careful selection and layout of external components is
required, to realize the full benefit of the onboard drivers.
The capacitors between VCC and GND and between BST
and SWN must be placed as close as possible to the IC. The
current paths for the TG and BG connections must be
optimized. A ground plane should be placed on the closest
layer for return currents to GND in order to reduce loop area
and inductance in the gate drive circuit.
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NCP1579
APPLICATION SECTION
Input Capacitor Selection
The above calculation includes the delay from comp
rising to when output voltage starts becomes valid.
To calculate the time of output voltage rising to when it
reaches regulation; DV is the difference between the comp
voltage reaching regulation and 0.88 V.
The input capacitor has to sustain the ripple current
produced during the on time of the upper MOSFET, so it
must have a low ESR to minimize the losses. The RMS value
of this ripple is:
Iin RMS + I OUT ǸD
(1 * D) ,
Output Capacitor Selection
The output capacitor is a basic component for the fast
response of the power supply. In fact, during load transient,
for the first few microseconds it supplies the current to the
load. The controller immediately recognizes the load
transient and sets the duty cycle to maximum, but the current
slope is limited by the inductor value.
During a load step transient the output voltage initial
drops due to the current variation inside the capacitor and the
ESR. ((neglecting the effect of the effective series
inductance (ESL)):
where D is the duty cycle, IinRMS is the input RMS current,
& IOUT is the load current. The equation reaches its
maximum value with D = 0.5. Loss in the input capacitors
can be calculated with the following equation:
P CIN + ESR CIN
Iin RMS 2 ,
where PCIN is the power loss in the input capacitors &
ESRCIN is the effective series resistance of the input
capacitance. Due to large dI/dt through the input capacitors,
electrolytic or ceramics should be used. If a tantalum must
be used, it must by surge protected. Otherwise, capacitor
failure could occur.
DV OUT−ESR + DI OUT
where VOUT- ESR is the voltage deviation of VOUT due to the
effects of ESR and the ESRCOUT is the total effective series
resistance of the output capacitors.
A minimum capacitor value is required to sustain the
current during the load transient without discharging it. The
voltage drop due to output capacitor discharge is given by
the following equation:
Calculating Input Start-up Current
To calculate the input start up current, the following
equation can be used.
C OUT
I inrush +
tSS
V OUT
,
where Iinrush is the input current during start-up, COUT is the
total output capacitance, VOUT is the desired output voltage,
and tSS is the soft start interval.
If the inrush current is higher than the steady state input
current during max load, then the input fuse should be rated
accordingly, if one is used.
DV OUT−DISCHARGE +
2
DIOUT 2 L OUT
,
C OUT (V IN D * V OUT)
where VOUT- DISCHARGE is the voltage deviation of VOUT
due to the effects of discharge, LOUT is the output inductor
value & VIN is the input voltage.
It should be noted that ΔVOUT- DISCHARGE and
ΔVOUT- ESR are out of phase with each other, and the larger
of these two voltages will determine the maximum deviation
of the output voltage (neglecting the effect of the ESL).
Calculating Soft Start Time
To calculate the soft start time, the following equation can
be used.
t ss +
ESR COUT
(C p ) C c) * DV
I ss
Inductor Selection
Both mechanical and electrical considerations influence
the selection of an output inductor. From a mechanical
perspective, smaller inductor values generally correspond to
smaller physical size. Since the inductor is often one of the
largest components in the regulation system, a minimum
inductor
value
is
particularly
important
in
space-constrained applications. From an electrical
perspective, the maximum current slew rate through the
output inductor for a buck regulator is given by:
Where Cc is the compensation as well as the soft start
capacitor,
Cp is the additional capacitor that forms the second pole.
Iss is the soft start current
DV is the comp voltage from zero to until it reaches
regulation
DV
880 mV
SlewRate LOUT +
V IN * V OUT
L OUT
This equation implies that larger inductor values limit the
regulator’s ability to slew current through the output
inductor in response to output load transients. Consequently,
output capacitors must supply the load current until the
inductor current reaches the output load current level. This
results in larger values of output capacitance to maintain
Vcomp
Vout
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NCP1579
tight output voltage regulation. In contrast, smaller values of
inductance increase the regulator’s maximum achievable
slew rate and decrease the necessary capacitance, at the
expense of higher ripple current. The peak-to-peak ripple
current for NCP1579 is given by the following equation:
Figure 10 shows a typical Type II transconductance error
amplifier (EOTA). The compensation network consists of
the internal error amplifier and the impedance networks ZIN
(R1, R2) and external ZFB (Rc, Cc and Cp). The
compensation network has to provide a closed loop transfer
function with the highest 0 dB crossing frequency to have
fast response (but always lower than FSW/8) and the highest
gain in DC conditions to minimize the load regulation. A
stable control loop has a gain crossing with -20 dB/decade
slope and a phase margin greater than 45°. Include
worst-case component variations when determining phase
margin. Loop stability is defined by the compensation
network around the EOTA, the output capacitor, output
inductor and the output divider. Figure 11 shows the open
loop and closed loop gain plots.
V OUT(1 * D)
,
L OUT 275 kHz
Ipk * pk LOUT +
where Ipk-pkLOUT is the peak to peak current of the output.
From this equation it is clear that the ripple current increases
as LOUT decreases, emphasizing the trade-off between
dynamic response and ripple current.
Feedback and Compensation
The NCP1579 allows the output of the DC-DC converter
to be adjusted from 0.8 V to 5.0 V via an external resistor
divider network. The controller will try to maintain 0.8 V at
the feedback pin. Thus, if a resistor divider circuit was
placed across the feedback pin to VOUT, the controller will
regulate the output voltage proportional to the resistor
divider network in order to maintain 0.8 V at the FB pin.
Compensation Network Frequency:
The inductor and capacitor form a double pole at the
frequency
F LC +
VOUT
ǸLo
Co
The ESR of the output capacitor creates a “zero” at the
frequency,
R1
F ESR +
FB
2p
1
ESR
Co
The zero of the compensation network is formed as,
R2
FZ +
ǒ
V REF
V OUT * V REF
2p
1
R cC c
The pole of the compensation network is calculated as,
The relationship between the resistor divider network above
and the output voltage is shown in the following equation:
R2 + R1
1
2p
Fp +
Ǔ
2p
1
Rc
Cp
Resistor R1 is selected based on a design tradeoff between
efficiency and output voltage accuracy. For high values of
R1 there is less current consumption in the feedback
network, However the trade off is output voltage accuracy
due to the bias current in the error amplifier. The output
voltage error of this bias current can be estimated using the
following equation (neglecting resistor tolerance):
Error% +
0.1 mA R 1
V REF
100%
Once R1 has been determined, R2 can be calculated.
Figure 11. Gain Plot of the Error Amplifier
R1
Thermal Considerations
EA
The power dissipation of the NCP1579 varies with the
MOSFETs used, VCC, and the boost voltage (VBST). The
average MOSFET gate current typically dominates the
control IC power dissipation. The IC power dissipation is
determined by the formula:
Gm
Cc
Rc
Cp
Vref
+
R2
−
P IC + (ICC
Figure 10. Type II Transconductance Error
Amplifier
Where:
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V CC) ) P TG ) P BG
NCP1579
PIC = control IC power dissipation,
ICC = IC measured supply current,
VCC = IC supply voltage,
PTG = top gate driver losses,
PBG = bottom gate driver losses.
The upper (switching) MOSFET gate driver losses are:
P TG + Q TG
f SW
NCP1579
V BST
Where:
QTG = total upper MOSFET gate charge at VBST,
fSW = the switching frequency,
VBST = the BST pin voltage.
The lower (synchronous) MOSFET gate driver losses are:
P BG + Q BG
fSW
Figure 12. Components to be Considered for
Layout Specifications
V CC
Where:
QBG = total lower MOSFET gate charge at VCC.
The junction temperature of the control IC can then be
calculated as:
T J + TA ) P IC
q JA
Where:
TJ = the junction temperature of the IC,
TA = the ambient temperature,
θJA = the junction−to−ambient thermal resistance of the
IC package.
The package thermal resistance can be obtained from the
specifications section of this data sheet and a calculation can
be made to determine the IC junction temperature. However,
it should be noted that the physical layout of the board, the
proximity of other heat sources such as MOSFETs and
inductors, and the amount of metal connected to the IC,
impact the temperature of the device. Use these calculations
as a guide, but measurements should be taken in the actual
application.
Layout Considerations
As in any high frequency switching converter, layout is
very important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding. The figure below shows the critical power
components of the converter. To minimize the voltage
overshoot the interconnecting wires indicated by heavy lines
should be part of ground or power plane in a printed circuit
board. The components shown in the figure below should be
located as close together as possible. Please note that the
capacitors CIN and COUT each represent numerous physical
capacitors. It is desirable to locate the NCP1579 within 1
inch of the MOSFETs, Q1 and Q2. The circuit traces for the
MOSFETs’ gate and source connections from the NCP1579
must be sized to handle up to 2 A peak current.
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NCP1579
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AK
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8 _
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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