STK14CA8 128K x 8 AutoStoreTM nvSRAM QuantumTrapTM CMOS Nonvolatile Static RAM FEATURES DESCRIPTION • 25ns, 35ns and 45ns Access Times • “Hands-off” Automatic STORE on Power Down with only a small capacitor • STORE to QuantumTrap™ Nonvolatile Elements is Initiated by Software , device pin or AutoStore™ on Power Down • RECALL to SRAM Initiated by Software or Power Up • Unlimited READ, WRITE and RECALL Cycles • 5mA Typical ICC at 200ns Cycle Time • 1,000,000 STORE Cycles to QuantumTrap™ • 100-Year Data Retention to QuantumTrap™ • Single 3V +20%, -10% Operation • Commercial and Industrial Temperatures • SOIC, SSOP and DIP Packages • RoHS Compliance The Simtek STK14CA8 is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate TM Simtek’s QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent, nonvolatile data resides in the TM highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. BLOCK DIAGRAM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 ROW DECODER STORE STATIC RAM ARRAY 1024 X 1024 RECALL VCC VCAP POWER CONTROL STORE/ RECALL CONTROL HSB SOFTWARE DETECT INPUT BUFFERS A5 A6 A7 A8 A9 A12 A13 A14 A15 A16 Quantum Trap 1024 X 1024 A15 – A0 COLUMN I/O COLUMN DEC A 0 A 1 A 2 A 3 A 4 A10 A11 G E W Figure 1. Block Diagram December 2004 1 Document Control #ML0022 rev 1.0 STK14CA8 PACKAGES A12 A7 A6 A5 A4 VSS DQ0 A3 A2 A1 A0 DQ1 DQ2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC A15 HSB W A13 A8 A9 VCAP A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS A11 VSS DQ6 G A10 E DQ7 DQ5 DQ4 DQ3 VCC 48 Pin SSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 HSB W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 32 Pin SOIC or PDIP SSOP VCAP A16 A14 Relative PCB area usage. See website for detailed package size specifications. PIN DESCRIPTIONS Pin Name I/O A16 – A0 Input DQ7 –DQ0 I/O E Input W Input G Input VCC Power Supply HSB I/O Description Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array. Data: Bi-directional 8-bit data bus for accessing the nvSRAM. Chip Enable: The active low E input selects the device. Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by the falling edge of E . Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high causes the DQ pins to tri-state. Power 3.0V +20%, -10% Hardware Store Busy: When low this output indicates a Hardware Store is in progress. When pulled low external to the chip it will initiate a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin high if not connected. (Connection Optional) VCAP Power Supply VSS Power Supply (Blank) No Connect December 2004 Autostore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements. Ground Unlabeled pins have no internal connection. 2 Document Control #ML0022 rev 1.0 STK14CA8 ABSOLUTE MAXIMUM RATINGSa -0.5V to +4.1V Power Supply Voltage -0.5V to (VCC + 0.5V) Voltage on Input Relative to VSS -0.5V to (VCC + 0.5V) Voltage on Outputs Temperature under Bias –55°C to 125°C Junction Temperature –55°C to 140°C Storage Temperature –65°C to 150°C Power Dissipation 1W DC Output Current (1 output at a time, 1s duration) 15mA Notes a: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Package Thermal Characteristics see website: http://www.simtek.com/ DC CHARACTERISTICS Symbol Parameter ICC1 Average VCC Current ICC2 Average VCC Current during STORE Commercial MIN MAX Industrial MIN MAX Units Notes 65 55 50 70 60 55 mA mA mA 3 3 mA tAVAV = 25ns tAVAV = 35ns tAVAV = 45ns Dependent on output loading and cycle rate. Values obtained without output loads. All Inputs Don’t Care, VCC = max Average current for duration of STORE cycle (tSTORE). Average VCC Current at tAVAV = 200ns ICC3 ICC4 3V, 25°C, Typical Average VCAP Current during AutoStore™ Cycle 5 5 mA 3 3 mA W ≥ (VCC – 0.2V) All Others Inputs Cycling, at CMOS Levels. Dependent on output loading and cycle rate. Values obtained without output loads. All Inputs Don’t Care Average current for duration of STORE cycle (tSTORE). mA E ≥ (VCC – 0.2V) All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V) Standby current level after nonvolatile cycle is complete. VCC Standby Current ISB IILK (Standby, Stable CMOS Input Levels) 2 2 VCC = max Input Leakage Current ±1 ±1 µA ±1 ±1 µA VIN = VSS to VCC, E or G ≥ VIH V All Inputs IOLK Off-State Output Leakage Current VIH Input Logic “1” Voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 VSS – 0.5 0.8 VSS – 0.5 0.8 VIL Input Logic “0” Voltage VOH Output Logic “1” Voltage VOL Output Logic “0” Voltage TA Operating Temperature 2.4 2.4 0.4 0.4 VIN = VSS to VCC VCC = max V All Inputs V IOUT = –2mA V IOUT = 4mA o 0 70 –40 85 VCC Operating Voltage 2.7 3.6 2.7 3.6 V 3.0V +20%, -10% VCAP Storage Capacitor 17 57 17 57 µF Between Vcap pin and Vss, 5V rated. December 2004 3 C Document Control #ML0022 rev 1.0 STK14CA8 AC TEST CONDITIONS 0V to 3V Input Pulse Levels Input Rise and Fall Times ≤ 5ns Input and Output Timing Reference Levels 1.5V Output Load See Figure 2 and Figure 3 CAPACITANCE b (TA = 25°C, f = 1.0MHz) SYMBOL PARAMETER MAX UNITS CONDITIONS CIN Input Capacitance 7 pF ∆V = 0 to 3V COUT Output Capacitance 7 pF ∆V = 0 to 3V Notes b: These parameters are guaranteed but not tested 3.0V 3.0V 577 Ohms 577 Ohms OUTPUT OUTPUT 789 Ohms 30 pF INCLUDING SCOPE AND FIXTURE 789 Ohms Figure 2. AC Output Loading December 2004 530 pFpF INCLUDING SCOPE AND FIXTURE Figure 3. AC Output Loading, for tristate specs ( tHZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ ) 4 Document Control #ML0022 rev 1.0 STK14CA8 SRAM READ CYCLES #1 & #2 SYMBOLS NO. #1 #2 1 2 3 c tAVAV STK14CA8-35 STK14CA8-45 MIN MIN MIN UNITS Alt. MAX tELQV tACS Chip Enable Access Time c tAVAV tRC Read Cycle Time tAA Address Access Time 25 tOE Output Enable to Data Valid 12 d tAVQV tGLQV 4 5 STK14CA8-25 PARAMETER d tAXQX 25 25 45 ns 35 45 ns 15 20 ns 35 45 ns Output Hold after Address Change 3 3 3 ns tLZ Chip Enable to Output Active 3 3 3 ns tELQX 7 tEHQZ tHZ Chip Disable to Output Inactive 8 tGLQX tOLZ Output Enable to Output Active 9 tGHQZ tOHZ Output Disable to Output Inactive 10 tELICCb tPA Chip Enable to Power Active 11 tEHICC b tPS Chip Disable to Power Standby e 35 MAX tOH 6 e MAX 10 0 13 0 10 0 15 0 13 0 15 0 25 35 ns ns ns ns 45 ns Notes c: W must be high during SRAM READ cycles d: Device is continuously selected with E and G both low e: Measured ± 200mV from steady state output voltage f: HSB must remain high during READ and WRITE cycles. SRAM READ CYCLE #1: Address Controlledc,d,f 2 tAVAV ADDRESS 3 tAVQV 5 tAXQX DQ (DATA OUT) DATA VALID SRAM READ CYCLE #2: E Controlledc,f 2 tAVAV ADDRESS E 1 tELQV 6 11 tEHICCL tELQX 7 tEHQZ G 9 tGHQZ 4 8 tGLQX DQ (DATA OUT) tGLQV DATA VALID 10 tELICCH ICC December 2004 ACTIVE STANDBY 5 Document Control #ML0022 rev 1.0 STK14CA8 SRAM WRITE CYCLES #1 & #2 SYMBOLS NO. #1 PARAMETER #2 Alt. STK14CA8-25 STK14CA8-35 STK14CA8-45 MIN MIN MIN MAX MAX UNITS MAX 12 tAVAV tAVAV tWC Write Cycle Time 25 35 45 ns 13 tWLWH tWLEH tWP Write Pulse Width 20 25 30 ns 14 tELWH tELEH tCW Chip Enable to End of Write 20 25 30 ns 15 tDVWH tDVEH tDW Data Set-up to End of Write 10 12 15 ns 16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 0 ns 17 tAVWH tAVEH tAW Address Set-up to End of Write 20 25 30 ns 18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 ns 19 tWHAX tEHAX tWR Address Hold after End of Write 0 20 tWLQZe,g tWZ Write Enable to Output Disable 21 tWHQX tOW Output Active after End of Write 0 10 3 0 13 ns 15 3 3 ns ns Notes g: If W is low when E goes low, the outputs remain in the high-impedance state. h: E or W must be ≥ VIH during address transitions. SRAM WRITE CYCLE #1: W Controlledh,f 12 tAVAV ADDRESS 19 tWHAX 14 tELWH E 17 tAVWH 18 13 tWLWH tAVWL W 15 tDVWH 16 tWHDX DATA VALID DATA IN 20 tWLQZ DATA OUT HIGH IMPEDANCE PREVIOUS DATA 21 tWHQX SRAM WRITE CYCLE #2: E Controlledh,f 12 tAVAV ADDRESS 14 tELEH 18 tAVEL 19 tEHAX E 17 tAVEH W 13 tWLEH 16 tEHDX 15 tDVEH DATA IN DATA OUT December 2004 DATA VALID HIGH IMPEDANCE 6 Document Control #ML0022 rev 1.0 STK14CA8 MODE SELECTION E W G A15 - A0 MODE I/O POWER H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Autostore Disable Output Data Output Data Output Data Output Data Output Data Output Data Active i, j, k L 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Autostore Enable Output Data Output Data Output Data Output Data Output Data Output Data Active i, j, k L 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Store Output Data Output Data Output Data Output Data Output Data Output High Z 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall Output Data Output Data Output Data Output Data Output Data Output High Z L L L L H H H H L NOTES Active i, j, k ICC2 Active i, j, k Notes i: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. j: While there are 17 addresses on the STK14CA8, only the lower 16 are used to control software modes k: I/O state depends on the state of G . The I/O table shown assumes G low. December 2004 7 Document Control #ML0022 rev 1.0 STK14CA8 AutoStore™ /POWER-UP RECALL SYMBOLS PARAMETER STK14CA8 NO. Standard 22 tHRECALL 23 tSTORE 24 VSWITCH 25 tVCCRISE Alternate MIN Power-up RECALL Duration tHLHZ STORE Cycle Duration 2.55 Low Voltage Trigger Level VCC Rise Time Notes l: tHRECALL starts from the time VCC rises above VSWITCH m: If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place UNITS NOTES 20 ms l 12.5 ms m MAX 2.65 µs STORE occurs only if a SRAM write has happened. AutoStore™/POWER-UP RECALL V 150 No STORE occurs without at least one SRAM write. VCC 24 VSWITCH 25 tVCCRISE AutoStoreTM 23 tSTORE 23 tSTORE POWER-UP RECALL 22 tHRECALL 22 tHRECALL Read & Write Inhibited POWER-UP RECALL BROWN OUT TM AutoStore POWER-UP RECALL POWER DOWN TM AutoStore Note: Read and Write cycles will be ignored during STORE, RECALL and while VCC is below VSWITCH. December 2004 8 Document Control #ML0022 rev 1.0 STK14CA8 SOFTWARE-CONTROLLED STORE/RECALL CYCLEn,o SYMBOLS NO. E G cont STK14CA8-25 STK14CA8-35 STK14CA8-45 MIN MIN MIN PARAMETER Alt. MAX MAX UNITS NOTES 45 ns o MAX cont 26 tAVAV tAVAV tRC STORE/RECALL Initiation Cycle Time 27 tAVEL 28 tELEH 29 tELAX tGLAX 25 35 tAVGL tAS Address Set-up Time 0 0 0 ns tGLGH tCW Clock Pulse Width 20 25 30 ns Address Hold Time 20 20 20 ns 30 tRECALL tRECALL 40 RECALL Duration Notes n: The software sequence is clocked with E controlled READs or G controlled READs. o: The six consecutive addresses must be read in the order listed in the Mode Selection Table. W 40 40 µs must be high during all six consecutive cycles. SOFTWARE STORE/RECALL CYCLE: E Controlledo ADDRESS E 27 tAVEL 26 tAVAV 26 tAVAV ADDRESS #1 ADDRESS #6 28 tELEH 29 tELAX G 23 tSTORE DQ (DATA) DATA VALID DATA VALID / 30 tRECALL HIGH IMPEDENCE SOFTWARE STORE/RECALL CYCLE: G Controlledo ADDRESS 26 tAVAV 26 tAVAV ADDRESS #1 ADDRESS #6 E 27 tAVGL 28 tGLGH G 23 tSTORE 29 tGLAX DQ (DATA) December 2004 DATA VALID DATA VALID 9 / 30 tRECALL HIGH IMPEDENCE Document Control #ML0022 rev 1.0 STK14CA8 HARDWARE STORE CYCLE SYMBOLS STK14CA8 NO. PARAMETER Standard 31 tDELAY 32 tHLHX Alternate tHLQZ MIN UNITS NOTES p MAX Time Allowed to Complete SRAM Cycle 1 µs Hardware STORE Pulse Width 15 ns tHLBL Hardware STORE Low to STORE Busy 33 Notes p: Read and Write cycles in progress before HSB is asserted are given this amount of time to complete. 300 ns HARDWARE STORE CYCLE 32 tHLHX HSB (IN) HSB (OUT) 33 tHLBL 23 tSTORE HIGH IMPEDENCE HIGH IMPEDENCE 31 tDELAY DQ (DATA OUT) December 2004 DATA VALID DATA VALID 10 Document Control #ML0022 rev 1.0 STK14CA8 DEVICE OPERATION nvSRAM The STK14CA8 nvSRAM is made up of two functional components paired in the same physical cell. These are a SRAM memory cell and a nonvolatile QuantumTrap™ cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM can be transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture allows all cells to be stored and recalled in parallel. During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited. The STK14CA8 supports unlimited reads and writes just like a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to 1 million STORE operations. SRAM READ The STK14CA8 performs a READ cycle whenever E and G are low while W and HSB are high. The address specified on pins A16-0 determines which of the 131,072 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G , the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high, or W or HSB is brought low. W 0.1µF VCC VCAP VCAP 10k Ohm VCC SRAM WRITE A WRITE cycle is performed whenever E and W are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low. AutoStore™ OPERATION The STK14CA8 stores data to nvSRAM using one of three storage operations. These three operations are Hardware Store, activated by HSB , Software Store, actived by an address sequence, and AutoStore™, on device power down. AutoStore™ operation is a unique feature of Simtek QuantumTrap™ technology and is enabled by default on the STK14CA8. During normal operation, the device will draw current from Vcc to charge a capacitor connected to the Vcap pin. This stored charge will be used by the chip to perform a single STORE operation. If the voltage on the Vcc pin drops below Vswitch, the part will automatically disconnect the Vcap pin from Vcc. A STORE operation will be initiated with power provided by the Vcap capacitor. Figure 4 shows the proper connection of the storage capacitor (Vcap) for automatic store operation. Refer to the DC CHARACTERISTICS table for the size of Vcap. The voltage on the Vcap pin is driven to 5V by a charge pump internal to the chip. A pull up should be placed on W to hold it inactive during power up. To reduce unneeded nonvolatile stores, AutoStore™ and Hardware Store operations will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. The HSB signal can be monitored by the system to detect an AutoStore™ cycle is in progress. Figure 4: AutoStoreTM Mode December 2004 11 Document Control #ML0022 rev 1.0 STK14CA8 HARDWARE STORE ( HSB ) OPERATION The STK14CA8 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin can be used to request a hardware STORE cycle. When the HSB pin is driven low, the STK14CA8 will conditionally initiate a STORE operation after tDELAY. An actual STORE cycle will only begin if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress. SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the STK14CA8 will continue SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low it will be allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high. During any STORE operation, regardless of how it was initiated, the STK14CA8 will continue to drive the HSB pin low, releasing it only when the STORE is complete. Upon completion of the STORE operation the STK14CA8 will remain disabled until the HSB pin returns high. If HSB is not used, it should be left unconnected. HARDWARE RECALL (POWER-UP) During power up, or after any low-power condition (VCC < VSWITCH), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tHRECALL to complete. SOFTWARE STORE Data can be transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK14CA8 software STORE cycle is initiated by executing sequential E controlled READ cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence, or the sequence will be aborted and no STORE or RECALL will take place. To initiate the software STORE cycle, the following READ sequence must be performed: 1. 2. 3. 4. 5. 6. 12 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE cycle The software sequence may be clocked with controlled READs or G controlled READs. E Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. SOFTWARE RECALL Data can be transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of E controlled READ operations must be performed: 1. 2. 3. 4. 5. 6. December 2004 Read address Read address Read address Read address Read address Read address Read address Read address Read address Read address Read address Read address 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL cycle Document Control #ML0022 rev 1.0 STK14CA8 Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the nonvolatile elements. PREVENTING AUTOSTORETM The AutoStore™ function can be disabled by initiating an AutoStore Disable sequence. A sequence of read operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore Disable sequence, the following sequence of E controlled read operations must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 Valid READ Valid READ Valid READ Valid READ Valid READ AutoStore Disable NOISE CONSIDERATIONS The STK14CA8 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1µF connected between VCC and VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, careful routing of power, ground and signals will reduce circuit noise. LOW AVERAGE ACTIVE POWER CMOS technology provides the STK14CA8 this the benefit of drawing significantly less current when it is cycled at times longer than 50ns. Figure 5 shows the relationship between ICC and READ/WRITE cycle time. Worst-case current consumption is shown for commercial temperature range, VCC = 3.6V, and chip enable at maximum frequency. Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK14CA8 depends on the following items: 1. 2. 3. 4. 5. 6. 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 Valid READ Valid READ Valid READ Valid READ Valid READ AutoStore Enable If the AutoStore™ function is disabled or re-enabled a manual STORE operation (Hardware or Software) needs to be issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore™ enabled. DATA PROTECTION The STK14CA8 protects data from corruption during low-voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The lowvoltage condition is detected when VCC < VSWITCH . If the STK14CA8 is in a WRITE mode (both E and W low ) at power-up, after a RECALL, or after a STORE, the WRITE will be inhibited until a negative transition on E or W is detected. This protects against inadvertent writes during power up or brown out conditions. December 2004 13 Average Active Current (mA) The AutoStore™ can be re-enabled by initiating an AutoStore Enable sequence. A sequence of read operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore Enable sequence, the following sequence of E controlled read operations must be performed: The duty cycle of chip enable. The overall cycle rate for accesses. The ratio of READs to WRITEs. The operating temperature. The VCC level. I/O loading. 50 40 30 Writes 20 10 Reads 0 50 100 150 200 300 Cycle Time (ns) Figure 5 Current vs. Cycle time Document Control #ML0022 rev 1.0 STK14CA8 ORDERING INFORMATION STK14CA8 – R F 45 I Temperature Range Blank = Commercial (0 to 70ºC) I = Industrial (-40 to 85ºC) Access Time 25 = 25ns 35 = 35ns 45 = 45ns Lead Finish Blank = 85% Sn / 15% Pb F = 100% Sn (Matte Tin) RoHS Compliant Package N = Plastic 32-pin 300 mil SOIC (50 mil pitch) R = Plastic 48-pin 300 mil SSOP (25 mil pitch) W = Plastic 32-pin 600 mil DIP (100 mil pitch) December 2004 14 Document Control #ML0022 rev 1.0 STK14CA8 Document Revision History Revision 0.0 Date January 2003 0.1 May 2003 0.2 September 2003 Summary Publish new datasheet Add 48 pin SSOP, Modify AutoStore drawing (Figure 2), Update Mode Selection Table and Absolute Maximum Ratings, Added G control software store Added lead-free lead finish Parameter 1.0 December 2004 Old Value New Value 10µF NA 35 mA 40 mA 50 mA 35 mA 45 mA 55 mA 1.5 mA 0.5 mA 5 ms 10 ms 20µs 10ns 17 µF 150 µs 50 mA 55 mA 65 mA 55 mA 60 mA 70 mA 3.0 mA 3 mA 20 ms 12.5 ms 40µs 12ns Vcap Min tVCCRISE ICC1 Max Com. ICC1 Max Com. ICC1 Max Com. ICC1 Max Ind. ICC1 Max Ind. ICC1 Max Ind. ICC2 Max ICC4 Max tHRECALL tSTORE tRECALL tGLQV Notes New Spec @ 45ns access @ 35ns access @ 25ns access @ 45ns access @ 35ns access @ 25ns access Com. & Ind. Com & Ind. 25 ns device SIMTEK STK14CA8 Data Sheet, December 2004 Copyright 2004, Simtek Corporation. All rights reserved. This datasheet may only be printed for the express use of Simtek Customers. No part of this datasheet may be reproduced in any other form or means without express written permission from Simtek Corporation. The information contained in this publication is believed to be accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein constitutes a license, grant or transfer of any rights to any Simtek patent, copyright, trademark or other proprietary right. December 2004 15 Document Control #ML0022 rev 1.0