CY2907 Single-PLL General-Purpose EPROM Programmable Clock Generator Features Benefits Single phase-locked loop architecture Generates a custom frequency from an external source EPROM programmability Easy customization and fast turnaround Factory-programmable (CY2907, CY2907I) or field-pro- Programming support available for all opportunities grammable (CY2907F & CY2907FI) device options Up to two configurable outputs Provides clocking requirements from a single device Low-skew, low-jitter, high-accuracy outputs Meets critical industry standard timing requirements Power management (Power-Down, OE) Supports low-power applications Frequency select option Up to 16 user-selectable frequencies Configurable 5V or 3.3V operation Supports industry-standard design platforms 8-pin or 14-pin SOIC packages Industry-standard packaging saves on board space Selector Guide Part Number Outputs Input Frequency Range Output Frequency Range CY2907 2 10 MHz–25 MHz (external crystal) 1 MHz–30 MHz (reference clock) 500 kHz–130 MHz (5V) 500 kHz–100 MHz (3.3V) Factory Programmable Commercial Temperature CY2907I 2 10 MHz–25 MHz (external crystal) 1 MHz–30 MHz (reference clock) 500 kHz–100 MHz (5V) 500 kHz–80 MHz (3.3V) Factory Programmable Industrial Temperature CY2907F8 CY2907F14 2 10 MHz–25 MHz (external crystal) 1 MHz–30 MHz (reference clock) 500 kHz–100 MHz (5V) 500 kHz–80 MHz (3.3V) Field Programmable Commercial Temperature CY2907F8I CY2907F14I 2 10 MHz–25 MHz (external crystal) 1 MHz–30 MHz (reference clock) 500 kHz–90 MHz (5V) 500 kHz–66.66 MHz (3.3V) Field Programmable Industrial Temperature Logic Block Diagram Specifics Pin Configurations Top View 14-Pin SOIC OEA OER REFCLK PD Output Multiplexer and Dividers XTALIN OSC. PLL XTALOUT CLKA S1 1 14 S0 S2 2 13 REFCLK S3 3 12 VDD VSS 4 11 CLKA VSS 5 10 PD XTALIN 6 9 OEA OER 7 8 XTALOUT EPROM Table Configuration EPROM and Test Logic S0 8-Pin SOIC S1 S2 S0 1 8 REFCLK VSS 2 7 VDD XTALIN 3 6 CLKA XTALOUT 4 5 S1 S3 CyClocks is a trademark of Cypress Semiconductor Corporation. Cypress Semiconductor Corporation Document #: 38-07137 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised September 26, 2001 CY2907 Pin Summary Pin Number Name 14-Pin SOIC 8-Pin SOIC S1 1 5 Frequency Select (CLKA) (Internal pull-up resistor to VDD) S2 2 NA Frequency Select (CLKA) (Internal pull-up resistor to VDD) S3 3 NA Frequency Select (CLKA) (Internal pull-up resistor to VDD) VSS 4 2 Ground VSS 5 NA Ground 6 NA Power-Down (active LOW) (Internal pull-up resistor to VDD) 7 3 Reference Crystal Input 8 4 Reference Crystal Feedback OER 9 NA REFCLK Output Enable (active HIGH) (Internal pull-up resistor to VDD) OEA 10 NA CLKA Output Enable (active HIGH) (Internal pull-up resistor to VDD) CLKA 11 6 Clock Output VDD 12 7 Voltage Supply REFCLK 13 8 Reference Clock Output (Default, can be driven by PLL if desired) S0 14 1 Frequency Select (CLKA) (Internal pull-up resistor to VDD) PD [1] XTALIN XTALOUT [1, 2] Description Notes: 1. For best accuracy, use a parallel-resonant crystal, CLOAD ≈ 17 pF. 2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal). Functional Description Cypress FTG Programmer The CY2907 is a general-purpose Clock Generator designed for use in a wide variety of applications—from graphics to PC peripherals to disk drives. It generates selectable system clock frequencies from a single reference input (crystal or reference clock). The CY2907 is configured with an EPROM array, much like the other devices in the Cypress EPROM Programmable Clock Family, making it easily customizable for any application. Furthermore, the CY2907 is compatible with all industry-standard 9107 and 9108 clock synthesizers. The Cypress Frequency Timing Generator (FTG) Programmers are portable programmers designed to custom program our family of EPROM Field Programmable Clock Devices. The FTG programmers connect to a PC serial port and allow users of CyClocks software to quickly and easily program any of the CY2291F, CY2292F, CY2071AF, and CY2907F devices. The ordering code for the Cypress FTG Programmer is CY3670. CyClocks™ Software CyClocks is an easy-to-use software application that allows you to configure any one of the EPROM Programmable Clocks offered by Cypress. You may specify the input frequency, PLL and output frequencies, and different functional options. Please note the output frequency ranges in this data sheet when specifying them in CyClocks to ensure that you stay within the limits. You can download a copy of CyClocks free on the Cypress Semiconductor website at www.cypress.com. Consider using the CY2081, CY2291, or CY2292 for applications that require unrelated and multiple output frequencies. Consider using the CY2071A for applications that require more than one output clock. Document #: 38-07137 Rev. ** Maximum Ratings (Beyond which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ................................................. –0.5 to +7.0V Input Voltage ........................................... –0.5V to VDD+0.5V Storage Temperature (Non-Condensing) ... –65°C to +150°C Max. Soldering Temperature (10 sec) ...................... +260°C Junction Temperature............................................... +150°C Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015) Page 2 of 10 CY2907 Operating Conditions[3] Parameter VDD TA Description Min. Max. Unit Supply Voltage, 5V Operation 4.5 5.5 V Supply Voltage, 3.3V Operation 3.0 3.6 V 0 70 °C –40 85 °C Commercial Operating Temperature, Ambient Industrial Operating Temperature, Ambient CL Max. Capacitive Load 15 pF fREF External Reference Crystal 10.0 25.0 MHz External Reference Clock[4, 5] 1.0 30.0 MHz Electrical Characteristics at 5.0V Commercial VDD = 4.5V to 5.5V, TA = 0°C to +70°C Parameter Description Test Conditions Min. VIH High-level Input Voltage Except Crystal Inputs VIL Low-level Input Voltage Except Crystal Inputs VOH[4] High-level Output Voltage VDD = VDD Min. IOH = –30 mA CLKA VOL[4] IOH[4] IOL[4] Low-level Output Voltage VDD = VDD Min. IOL = 10 mA CLKA Output High Current VOH = 2.0V Output Low Current VOL = 0.8V 22 IIH Input High Current VIH = VDD –2 Input Low Current Max. 2.0 Unit V 0.8 2.4 V V 0.4 V –35 mA mA 2 µA VIL = 0V 20 µA Power Supply Current PD HIGH, CLKA = 50 MHz 42 mA IDD Power Supply Current PD LOW, Logic Inputs LOW 100 µA IDD Power Supply Current PD LOW, Logic Inputs HIGH 40 µA Pull-up Resistor VIN = VDD – 1.0 V 700 kΩ IIL IDD [5] RPU [4] Electrical Characteristics at 3.3V Commercial VDD = 3.0V to 3.6V, TA = 0°C to +70°C Parameter Description Test Conditions Min. VIH High-level Input Voltage Except Crystal Inputs VIL Low-level Input Voltage Except Crystal Inputs VOH[4] High-level Output Voltage CLKA, IOH = –5 mA VOL[4] IOH[4] IOL[4] Low-level Output Voltage CLKA, IOL = 6 mA Output High Current VOH = 0.7*VDD Output Low Current VOL = 0.2*VDD 15 IIH Input High Current VIH = VDD –2 Input Low Current Max. 0.7*VDD Unit V 0.2*VDD 0.85*VDD V V 0.1*VDD V –10 mA mA 2 µA VIL = 0V 10 µA Power Supply Current PD HIGH, CLKA = 50 MHz 40 mA IDD Power Supply Current PD LOW, Logic Inputs LOW 40 µA IDD Power Supply Current PD LOW, Logic Inputs HIGH 12 µA Pull-up Resistor VIN = VDD – 0.5V 900 kΩ IIL IDD [5] RPU [4] Notes: 3. Electrical parameters are guaranteed with these operating conditions. 4. Guaranteed by design, not 100% tested in production. 5. Load = max. typical configuration, fREF = 14.318 MHz. Specific configurations may vary. A close approximation of IDD can be derived by the following formula: IDD (mA) = VDD * (6.25 + (0.055*FREF) + (0.0017*CLOAD*(FCLKA + REFCLK))). CLOAD is specified in pF and F is specified in MHz. Document #: 38-07137 Rev. ** Page 3 of 10 CY2907 Electrical Characteristics at 5.0V Industrial VDD = 4.5V to 5.5V, TA = –40°C to +85°C Parameter Description Test Conditions Min. VIH High-level Input Voltage Except Crystal Inputs VIL Low-level Input Voltage Except Crystal Inputs VOH[4] VOL[4] IOH[4] IOL[4] High-level Output Voltage VDD = VDD Min. IOH = –30 mA CLKA Low-level Output Voltage VDD = VDD Min. IOL = 10 mA CLKA Output High Current VOH = 2.0V Output Low Current VOL = 0.8V 20 IIH Input High Current VIH = VDD –2 Input Low Current IIL IDD [5] IDD IDD RPU [4] Max. 2.0 Unit V 0.8 V 2.4 V 0.4 V –45 mA mA 2 µA VIL = 0V 20 µA Power Supply Current PD HIGH, CLKA = 50 MHz 54 mA Power Supply Current PD LOW, Logic Inputs LOW 110 µA Power Supply Current PD LOW, Logic Inputs HIGH 45 µA Pull-up Resistor VIN = VDD – 1.0 V 700 kΩ Max. Unit Electrical Characteristics at 3.3V Industrial VDD = 3.0V to 3.6V, TA = –40°C to +85°C Parameter Description Test Conditions Min. VIH High-level Input Voltage Except Crystal Inputs VIL Low-level Input Voltage Except Crystal Inputs VOH[4] VOL[4] High-level Output Voltage CLKA, IOH = –5 mA Low-level Output Voltage CLKA, IOL = 6 mA IOH[4] Output High Current VOH = 0.7*VDD IOL[4] Output Low Current VOL = 0.2*VDD 14 IIH Input High Current VIH = VDD –2 IIL Input Low Current VIL = 0V [5] 0.7*VDD V 0.2*VDD 0.85*VDD V V 0.1*VDD V –12 mA mA 2 µA 10 µA Power Supply Current PD HIGH, CLKA = 50 MHz 50 mA IDD Power Supply Current PD LOW, Logic Inputs LOW 50 µA IDD Power Supply Current PD LOW, Logic Inputs HIGH 15 µA RPU[4] Pull-up resistor VIN = VDD – 0.5V 900 kΩ IDD Document #: 38-07137 Rev. ** Page 4 of 10 CY2907 Switching Characteristics at 5.0V Commercial[4] Parameter Output[6] tR CLKA Output Rise Time 0.8V to 2.0V tF CLKA Output Fall Time 2.0V to 0.8V tR CLKA tF Max. Unit 15-pF Load 1.40 ns 15-pF Load 1.00 ns Output Rise Time 20% to 80% 15-pF Load 3.5 ns CLKA Output Fall Time 80% to 20% 15-pF Load 2.5 ns tD CLKA Duty Cycle 15-pF Load at 1.4V 45.0 55.0 % FI XTALIN Input Frequency Crystal Oscillator 10 25 MHz FI XTALIN Input Frequency External Input Clock[7] 1 30 MHz FO CLKA Output Frequency CY2907, 15-pF Load 0.5 130.0 MHz CY2907F, 15-pF Load 0.5 100.0 MHz tJIS CLKA Jitter (One Sigma) 20 MHz to 130 MHz 150 ps tJIS CLKA Jitter (One Sigma) 14 MHz to 20 MHz 200 ps tJIS CLKA Jitter (One Sigma) Less than 14 MHz 1 % tJAB CLKA Jitter (Absolute) 20 MHz to 130 MHz –250 + 250 ps tJAB CLKA Jitter (Absolute) 14 MHz to 20 MHz –500 + 500 ps tJAB CLKA Jitter (Absolute) Less than 14 MHz 3 % 18 ms 13 ms Max. Unit tPU tFT Description Test Conditions Min. Power-up Time CLKA Transition Time 8 MHz to 66.6 MHz Switching Characteristics at 3.3V Commercial[4] Parameter Output[6] Description Test Conditions Min. tR CLKA Output Rise Time 20% to 80% 15-pF Load 3.5 ns tF CLKA Output Fall Time 80% to 20% 15-pF Load 2.5 ns tD CLKA Duty Cycle 15-pF Load at 1.4V 40.0 53.0 % FI XTALIN Input Frequency Crystal Oscillator 10 25 MHz FI XTALIN Input Frequency External Input Clock[7] 1 30 MHz FO CLKA Output Frequency CY2907, 15-pF Load 0.5 100.0 MHz CY2907F, 15-pF Load 0.5 80.0 MHz tJIS CLKA Jitter (One Sigma) 25 MHz to 100 MHz 150 ps tJIS CLKA Jitter (One Sigma) 14 MHz to 25 MHz 200 ps tJIS CLKA Jitter (One Sigma) Less than 14 MHz 1 % tJAB CLKA Jitter (Absolute) 25 MHz to 120 MHz –250 +250 ps tJAB CLKA Jitter (Absolute) 14 MHz to 25 MHz –500 +500 ps tJAB CLKA Jitter (Absolute) Less than 14 MHz 3 % 18 ms 13 ms Power-up Time tPU tFT CLKA Transition Time 8 MHz to 66.6 MHz Notes: 6. REFCLK output can also be configured to be driven by the PLL, in which case the above characteristics are valid. 7. Please refer to the application note “Crystal Oscillator Topics” when using an external reference clock as an input frequency source. : Document #: 38-07137 Rev. ** Page 5 of 10 CY2907 Switching Characteristics at 5.0V Industrial Parameter Output[6] tR CLKA Output Rise Time 0.8V to 2.0V tF CLKA tR Description Test Conditions Max. Unit 15-pF Load 1.40 ns Output Fall Time 2.0V to 0.8V 15-pF Load 1.00 ns CLKA Output Rise Time 20% to 80% 15-pF Load 3.5 ns tF CLKA Output Fall Time 80% to 20% 15-pF Load 2.5 ns tD CLKA Duty Cycle 15-pF Load at 1.4V 45.0 55.0 % FI XTALIN Input Frequency Crystal Oscillator 10 25 MHz 1 30 MHz [7] Min. FI XTALIN Input Frequency External Input Clock FO CLKA Output Frequency CY2907, 15-pF Load 0.5 100.0 MHz CY2907F, 15-pF Load 0.5 90 MHz tJIS CLKA Jitter (One Sigma) 20 MHz to 130 MHz 150 ps tJIS CLKA Jitter (One Sigma) 14 MHz to 20 MHz 200 ps tJIS CLKA Jitter (One Sigma) Less than 14 MHz 1 % tJAB CLKA Jitter (Absolute) 20 MHz to 130 MHz –250 + 250 ps tJAB CLKA Jitter (Absolute) 14 MHz to 20 MHz –500 + 500 ps tJAB CLKA Jitter (Absolute) Less than 14 MHz 3 % 18 ms 13 ms Max. Unit 3.5 ns tPU tFT Power-up Time CLKA Transition Time 8 MHz to 66.6 MHz Switching Characteristics at 3.3V Industrial Parameter Output[6] tR CLKA Output Rise Time 20% to 80% 15-pF Load tF CLKA Output Fall Time 80% to 20% 15-pF Load tD CLKA Duty Cycle 15-pF Load at 1.4V FI XTALIN Input Frequency Crystal Oscillator Description Test Conditions [7] Min. 2.5 ns 40.0 53.0 % 10 25 MHz 1 30 MHz FI XTALIN Input Frequency External Input Clock FO CLKA Output Frequency CY2907I, 15-pF Load 0.5 80.0 MHz CY2907FI, 15-pF Load 0.5 66.6 MHz tJIS CLKA Jitter (One Sigma) 25 MHz to 100 MHz 150 ps tJIS CLKA Jitter (One Sigma) 14 MHz to 25 MHz 200 ps tJIS CLKA Jitter (One Sigma) Less than 14 MHz 1 % tJAB CLKA Jitter (Absolute) 25 MHz to 120 MHz –250 +250 ps tJAB CLKA Jitter (Absolute) 14 MHz to 25 MHz –500 +500 ps tJAB CLKA Jitter (Absolute) Less than 14 MHz 3 % 18 ms 13 ms tPU tFT Power-up Time CLKA Transition Time Document #: 38-07137 Rev. ** 8 MHz to 66.6 MHz Page 6 of 10 CY2907 Switching Waveforms Frequency Select Change (Transition Time) OLD SELECT SELECT NEW SELECT STABLE Fold Fnew tFT CLKA 2907–4 2907–3 Duty Cycle Timing tD = t2 ÷ t1 t1 t2 CLKA 1.4V 2907–5 All Outputs Rise/Fall Time 80% 20% CLKA tR tF 2907–6 Test Circuit VDD VDD CLKA CLOAD 0.1 µF OUTPUTS REFCLK CLOAD Note: All capacitors should be placed as close to each pin as possible. Document #: 38-07137 Rev. ** Page 7 of 10 CY2907 Ordering Information Ordering Code Package Name Package Type Operating Range CY2907SC-xxx S8, S14 8-pin or 14-pin SOIC 5.0V, Commercial, Factory Programmable CY2907SL-xxx S8, S14 8-pin or 14-pin SOIC 3.3V, Commercial, Factory Programmable CY2907SI-xxx S8, S14 8-pin or 14-pin SOIC 5.0V/3.3V, Industrial, Factory Programmable CY2907F8 S8 8-pin SOIC 5.0V/3.3V, Commercial, Field Programmable CY2907F8I S8 8-pin SOIC 5.0V/3.3V, Industrial, Field Programmable CY2907F14 S14 14-pin SOIC 5.0V/3.3V, Commercial, Field Programmable CY2907F14I S14 14-pin SOIC 5.0V/3.3V, Industrial, Field Programmable Cypress FTG Programmer Custom Programming for Field Programmable Clocks CY3670 Package Characteristics θJA (C/W) θJC (C/W) Transistor Count 8-pin SOIC 170 35 5436 14-pin SOIC 140 31 5436 Package Package Diagrams 8-Lead (150-Mil) SOIC S8 51-85066-A Document #: 38-07137 Rev. ** Page 8 of 10 CY2907 Package Diagrams (continued) 14-Lead (150-Mil) SOIC S14 51-85067-A Document #: 38-07137 Rev. ** Page 9 of 10 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2907 Document Title: CY2907 Single-PLL General-Purpose EPROM Programmable Clock Generator Document Number: 38-07137 REV. ECN NO. Issue Date Orig. of Change ** 110246 12/18/01 SZV Document #: 38-07137 Rev. ** Description of Change Change from Spec number: 38-00505 to 38-07137 Page 10 of 10